Abstract: Disclosed are a semiconductor device and a method for fabricating the same which improve short channel effect and increase current driving force. The semiconductor device includes a first conductivity type semiconductor substrate, a gate electrode formed on the semiconductor substrate, a sidewall insulating film formed at both sides of the gate electrode, a second conductivity type first lightly doped impurity region and a second conductivity type second heavily doped impurity region formed in the semiconductor substrate at both sides of the gate electrode, a first conductivity type first impurity region for surrounding the second conductivity type first impurity region, and a first conductivity type second impurity region for surrounding the second conductivity type second impurity region.

Abstract: A vertical DMOSFET includes a buried layer which is of the same conductivity type as the drain and which extends into the heavily doped substrate and approaches or extends to the surface of the epitaxial layer at a central location in the MOSFET cell that is defined by the body regions of the MOSFET. In some embodiments the upper boundary of the buried layer generally conforms to the shape of the body region, forming a dish shaped structure under the body region. A significant portion of the current flowing through the channel is drawn into the buried layer and since the buried layer represents a relatively low-resistance path, the total resistance of the MOSFET is lowered without any significant effect on the breakdown voltage. The conformal buried layer can be formed by implanting dopant into the epitaxial layer at a high energy (0.5 to 3 MeV). Before the implant, a thick oxide layer is formed in a central region of the MOSFET cell.

Abstract: A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current driving capability of an NMOS device. The semiconductor device has halo impurity regions formed in either the NMOS region or the PMOS region such that a channel length of the PMOS device. Also, the source and drain regions of the PMOS device are prevented from forming deep source and drain regions, thus, preventing deterioration of the short channel properties for the PMOS device.

Abstract: The formation of lightly doped regions under a gate of a transistor that has a reduced gate oxide is disclosed. In one embodiment, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the gate oxide is etched to reduce the length of the gate oxide. In the third step, a first ion implantation is applied, at an angle other than perpendicular to the substrate. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.

Abstract: A high voltage MOS (Metal Oxide Semiconductor) transistor includes a semiconductor substrate of first conductivity type (P type). A pair of first diffused layers of second conductivity type (N type) are formed on the substrate. A pair of second diffused layers of second conductivity type (N type) are respectively formed in the first diffused layers and have a higher concentration than the first diffused layers. A gate region intervenes between the two first diffused layers facing each other. The gate region consists of a gate oxide film and a gate electrode. The distance between the first diffused layers is smaller in the deep region of the substrate than at the surface of the substrate. The MOS transistor has a great breakdown resisting quantity.

Abstract: Field effect transistors having tapered gate electrodes include a body region of first conductivity type extending to a surface of a semiconductor substrate. Source and drain regions of second conductivity type are formed in the substrate and a gate electrode is formed on a portion of the surface extending opposite the body region and between the source and drain regions. A gate electrode insulating layer is also disposed between the gate electrode and the surface. To improve the transistor's withstand voltage capability by reducing field crowding, the gate electrode insulating layer is preferably formed to have a tapered thickness which increases in a direction from the source region to the drain region, and to reduce on-state resistance the drain region is formed in a self-aligned manner to the gate electrode.

Abstract: A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower impurity concentration. The first doped region formed on the substrate by a high-energy ion-implantation process is kept at a predetermined distance from the surface of the substrate. The second doped region extends from the surface of the substrate toward the downside to connect to the first doped region, such that two third doped regions are formed. The second doped region is formed by an ion-implantation process through an opening of a mask. Furthermore, a gate is formed above the second doped region, and source and drain regions are formed on the substrate. Therefore, a device having an inverse T-shaped well region is completely fabricated.

Abstract: The invention comprises a transistor having a self-aligned implant under the gate. The transistor comprises a drain region, a source region opposite the drain region, and a channel region in a semiconductor substrate extending between the source region and the drain region. A front gate is disposed outwardly from the first substrate layer and is separated from the channel region by a dielectric layer. The front gate comprises a first gate layer disposed outwardly from the dielectric layer and a second gate layer disposed outwardly from the first gate layer. A self-aligned implant region is disposed inwardly from the channel region and in approximate vertical alignment with the front gate.

Abstract: A transistor formed in a semiconductor substrate having improved ESD protection is disclosed. The transistor includes a first ESD implant formed underneath the source region and the drain region of the transistor. The first ESD implant has the same impurity type as the source region and the drain region. Further, a second ESD implant is formed underneath the first ESD implant, the second ESD implant having an impurity type opposite to that of said first ESD implant. The second ESD implant also is spaced apart vertically from the first ESD implant.

Abstract: A method for fabricating an ultra-shallow semi-conductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Abstract: A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region.

Abstract: An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

Abstract: A semiconductor device is formed from a semiconductor substrate with a source and drain and a gate disposed thereon. The gate has a stepped profile with side portions with respective walls adjacent a respective one of the source and drain. The side portions of the gate are thinner than that of a center portion of the gate. The substrate is implanted with nitrogen forming first regions below the side portions of the gate and adjacent the surface of the substrate. The source and drain are implanted with nitrogen in second regions adjacent the side portions of the gate and spaced away from the surface of the substrate. The substrate is doped so that regions of the substrate lying above the second regions and to the side of the first regions are heavily doped, wherein the first and second regions implanted with nitrogen resist the doping.

Abstract: A cellular insulated gate bipolar transistor ("IGBT") device has a reduced length of the channels of the individual cells that is formed by reducing the channel drive in time from the customary 120 minutes at 1175.degree. C. to between 60 and 90 minutes at 1175.degree. C. The process also permits the use of a higher minority carrier lifetime killing electron radiation dose to improve switching power loss while reducing SOA by only a small value. Alternatively, the increased concentration region located in the active region between spaced bases is initially driven in at a temperature of about 1175.degree. C. for about 12 hours, rather than the customary 8 hours, and the channel drive in time is reduced from 120 minutes to 60 minutes. The shorter channel length, when combined with the deeper enhancement region, allows for higher lifetime electron irradiation doses or heavy metal diffusion temperatures.

Abstract: SOI FETs include an electrically insulating substrate, a semiconductor region on the electrically insulating substrate, a field effect transistor having source, drain and channel regions in the semiconductor region and a metal silicide region between the electrically insulating substrate and the semiconductor region. The metal silicide region (e.g., TiSi.sub.2) forms non-rectifying junctions with the source and channel regions of the field effect transistor so that holes accumulated in the channel region (upon impact ionization) can be readily transported to the source region (and contact thereto) via the metal silicide layer and recombination of the holes with electrons in the source region can be carried out with high efficiency. The metal silicide region ohmically contacts the source and channel regions, but does not form a junction with the drain region of said field effect transistor.

Abstract: A semiconductor device comprising a semiconductor substrate of a first conductivity type, an element separating field oxide film formed on the semiconductor substrate and a MOS transistor formed in an element area defined by the field oxide film. The MOS transistor includes a gate electrode and source and drain regions each comprising a diffusion layer of a second conductivity type opposite the conductivity type of the semiconductor substrate. The semiconductor device further comprises a channel stopper of the first conductivity type and a punch-through stopper of the first conductivity type provided below the field oxide film and gate electrode, respectively. Furthermore, a diffusion layer of the second conductivity type of the MOS transistor does not contact the channel stopper and the punch-through stopper. Also disclosed is a method of fabricating the semiconductor device.

Abstract: A ROM device structure, featuring a ROM memory cell, with the ROM memory cell exhibiting a concave shaped, channel region, has been developed. The ROM device structure is comprised of heavily doped, N type, bit line regions, located in flat regions of the ROM device structure, while lightly doped, P type regions. comprise the concave channel region for the ROM memory cell. The ROM device structure offers self-alignment of the P type, concave channel regions, to the heavily doped N type, bit line regions.

Abstract: A non-volatile semiconductor cell structure and method comprises a trenched floating gate, a sidewall doping and a corner doping and further includes a sidewall doped region, a corner doped region, a channel region, and an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate. In a preferred embodiment, the trenched floating gate has a top surface which is substantially planar with a top surface of the semiconductor substrate. The control gate and the inter-gate dielectric are formed on the top surface of the trenched floating gate. The sidewall doped region and the corner doped region are laterally separated by the trench in which the trenched floating gate is formed. The sidewall doped region has a depth which is greater than the depth of the trench, and the corner doped region has a depth which is less than the depth of the trench.

Abstract: A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface.

Abstract: An n.sup.- well region is formed at a surface of a semiconductor substrate. A MOS transistor of high breakdown voltage having a drain region and a source region is formed at the surface of the n.sup.- well region. The n.sup.- well region has an impurity concentration peak right below the drain region. Accordingly, a semiconductor device having a high breakdown voltage insulation gate type field effect transistor that can suppress increase of a depletion layer when high voltage is applied across the drain, that can reduce the electric field intensity across the drain, and that has superior breakdown voltage, and a fabrication method thereof, are obtained.

Abstract: The formation of a shortage protection region is disclosed. In one embodiment, a method includes three steps. In the first step, a first ion implantation is applied to form lightly doped regions within a semiconductor substrate adjacent to sidewalls of a gate over the substrate. In the second step, two spaces are formed on the substrate, each adjacent to a sidewall of the gate, so that a second ion implantation forms heavily doped regions within the substrate adjacent to the first spacers. In the third step, two additional spacers are formed on the substrate, each overlapping and extending beyond a corresponding spacer previously formed. Thus, a third ion implantation forms lightly doped shortage protection regions within the substrate adjacent to the spacers most recently formed.

Abstract: After a field oxide film is formed on a P-type semiconductor substrate, ion implantation of boron is carried out with respect to a whole surface of the substrate so that a channel stopper layer is formed. Then, a MOS FET is formed in an active region of the semiconductor substrate. Subsequently, ion implantation of phosphorus is carried out, by using a gate electrode of the MOS FET and the field oxide film as a mask, so that impurity layers which have the same type of conductivity as that of the channel stopper layer and has a concentration lower than that of the channel stopper layer are formed right under the source/drain regions of the MOS FET between the source/drain regions and the channel stopper layer.

Abstract: Impurity regions 110 that can form an energy barrier are artificially and locally disposed in a channel formation region 111. The impurity regions 110 restrain a depletion layer that extends from a drift region 102 toward a channel formation region 111, and prevents a short channel effect caused by the depletion layer, with the result that an insulated gate semiconductor device high in withstand voltage can be manufactured without lowering the operation speed.

Abstract: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.

Abstract: A MOS transistor includes a semiconductor substrate of a first conductivity type having a major surface, a source and drain of a second conductivity type formed on the major surface to define a channel region therebetween, and a gate arranged in the channel region via an insulating film. The MOS transistor includes an impurity-implanted region of the first conductivity type located at a substrate portion which is deeper than the channel region and is shifted to a source side from a region corresponding to the channel region.

Abstract: A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is ?Acm.sup.-1 !, the amount of charge of electrons is q?C!, and the drift speed of carriers is .upsilon..sub.drift ?cms.sup.-1 !, the dosage n.sub.2 of the second offset layer is given by n.sub.2 .gtoreq.I.sub.D /(q.upsilon..sub.drift)?cms.sup.-2 !.

Abstract: A CMOS device includes a first MOS transistor of a surface channel type and a second MOS transistor of a buried channel type on a common substrate wherein a doped layer is provided underneath a first channel layer of the first MOS transistor and a second channel layer of the second MOS transistor, such that the first channel layer is provided at a level closer to a principal surface of the substrate as compared with source and drain regions of the first and second MOS transistors.

Abstract: A semiconductor memory device is provided which includes: a memory cell portion including at least one gate electrode formed on a semiconductor substrate and a plurality of source/drain regions formed in the semiconductor substrate and extending parallel to each other and perpendicular to the gate electrode, the gate electrode and the plurality of source/drain regions constituting a plurality of first conductivity type channel transistors; and a peripheral circuitry portion including a first conductivity type channel transistor having a gate electrode formed on the semiconductor substrate and source/drain regions; wherein channels of the first conductivity type channel transistors in the memory cell portion each have a higher impurity concentration than a channel of the first conductivity type channel transistor in the peripheral circuitry portion.

Abstract: A field controlled semiconductor device of SiC comprises superimposed in the order mentioned at least a drain (12), a highly doped substrate layer (1) and a low doped n-type drift layer (2). It has also a highly doped n-type source region layer (6) and a source (11) connected thereto. A doped channel region layer (4) connects the source region layer to the drift layer, and a current is intended to flow therethrough when the device is in an on-state. The device has also a gate electrode (9). The channel region layer has a substantially lateral extension and is formed by a low doped n-type layer (4). The gate electrode (9) is arranged to influence the channel region layer from above for giving a conducting channel (17) created therein from the source region layer to the drift layer a substantially lateral extension.

Abstract: A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A gate oxide layer is grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. The source-side and drain-side junctions are implanted with a dopant to form LDD areas therein. The source-side junction may then be exclusively implanted to form a heavily doped source region in the source-side junction. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor.

Abstract: A peripheral circuit for a nonvolatile integrated circuit memory device includes a semiconductor substrate with a well region having a first conductivity type adjacent a face of the substrate. A first transistor on the well region includes a first gate insulating layer, a first gate electrode, first lightly doped regions in the well region adjacent opposite sides of the first gate electrode, and first heavily doped regions in the well region adjacent the first lightly doped regions opposite the first gate electrode. The first gate insulating layer is adjacent the first well region and has a first thickness. The first gate electrode is on the first gate insulating layer, and the first lightly doped regions define a first transistor channel therebetween and have a second conductivity type and a first light dopant concentration. The first heavily doped regions have the second conductivity and a first heavy dopant concentration.

Abstract: A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').

Abstract: An insulated-gate field-effect transistor formed in a substrate of a first conductive type or in a well of the first conductive type formed in the substrate is provided. The transistor includes a channel region containing an impurity of the first conductive type; and a source-drain region containing an impurity of a second conductive type. The source-drain region further contains an impurity of the first conductive type; and a concentration of the impurity of the first conductive type contained in the source-drain region is greater than a concentration of the impurity of the first conductive type contained in the channel region but is less than a concentration of the impurity of the second conductive type contained in the source-drain region.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: Reverse short-channel effect is suppressed in a field effect transistor with a gate having a short length. The field effect transistor comprises a p-type silicon substrate, a gate electrode, paired lightly doped source/drain regions, and paired heavily doped source/drain regions. A boron concentration peak region is formed in the silicon substrate. A boron concentration peak region positioned at an end of the gate electrode has a length d of one fourth of a length L of the gate electrode, and extends from the end to the center of the gate electrode.

Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region.

Abstract: An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a silicon substrate. A p type impurity concentration profile includes respective peak concentrations at a dope region for forming a p type well, a p type channel cut region, and a p type channel dope region. An impurity concentration profile of the n type source/drain region crosses the p type impurity concentration profile at a low concentration, and includes phosphorus implantation regions indicating impurity concentrations respectively higher than those of the p type channel cut region and the p type channel dope region and respective peaks in impurity concentration at the neighborhood of respective depth thereof.

Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

Abstract: A semiconductor integrated circuit device having an SOI structure is capable of preventing occurrence of leak current flowing from a diffusion layer even when a semiconductor element having a pn-junction is included in the semiconductor substrate. The semiconductor integrated circuit device having the SOI structure is formed with a semiconductor layer, or SOI layer, on a p-type semiconductor substrate through a buried insulating film and further with semiconductor circuit elements serving as functional elements at the SOI layer thus formed. As a protection transistor to protect the semiconductor circuit elements, a MOSFET may be formed in which n-type diffusion layers are formed in the semiconductor substrate. The n-type diffusion layers of the MOSFET are to be surrounded by p-type diffusion layers more highly doped than the semiconductor substrate.

Abstract: A thin film transistor (TFT) comprises a n.sup.+ source region and a p.sup.+ drain separated by an undoped offset region, or the complementary structure with a p.sup.+ source and a n.sup.+ drain. By means of this arrangement in the offset region is conduction is by way of both electron and hole carriers and the offset region is conductivity modulated. The TFT of the present invention has lower on-resistance than a conventional thin film transistor.

Abstract: The flash device is a field effect single cell device. The flash device has the source laying under the gate. The variance of gate voltage has the direct capacitor coupling and current injecting effects with the source to speed up the response of circuit. Furthermore, the process of the flash device is comparable with the CMOS device. It is an ideal device for the output buffer which has the anti-ground-bounce and anti-power-droop capabilities. The single cell technology is applied to the single cell active pixel to integrate four different components into one cell. The versatile operation is applied to have the super-flash EEPROM.

Abstract: The present invention provides a semiconductor device which includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drain region provided in a manner to form a channel region on the upper face of the element region across the gate electrode, and which has a high concentration impurity region containing a second conductivity type impurity at a concentration higher than that on the surface of the channel region in the central part of the projection-shaped semiconductor element region.

Abstract: A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.

Abstract: A MOS semiconductor device includes a first conductivity type silicon layer having a main surface; a gate insulating film selectively formed on the main surface of the silicon layer; a gate electrode provided on the gate insulating film; an insulating side wall formed on the side of the gate electrode; and source/drain regions formed in the silicon layer. The source/drain regions include a first diffusion layer of second conductivity type formed in the silicon layer; a second diffusion layer of second conductivity type formed in the silicon layer on the outside of the first diffusion layer and having a PN-junction depth larger than that of the first diffusion layer; and the MOS semiconductor device further includes a conductive layer covering at least part of the first diffusion layer and at least part of the second diffusion layer.

Abstract: An improved manufacturing process and an improved device made by the process for retarding diffusion of implanted dopants during subsequent high-temperature processing. A layer of an electrically inactive species is implanted well below the active dopant layers, and the excess interstitials due to damage from the electrically inactive species layer form a retarding gradient which opposes dopant diffusion. Using this process, shallow source-drain junctions can be achieved, and lateral encroachment of LDD implants under the gate can be minimized.

Abstract: A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type.

Abstract: A Fermi-threshold field effect transistor includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the lateral direction. In order to compensate for the junction with the substrate, the doping density of the substrate region is raised to counteract the shared charge. Furthermore, the proximity of the source and drain regions leads to a potential leakage due to the drain field which can be compensated for by reducing the maximum tub depth compared to a low capacitance Fermi-FET and a contoured-tub Fermi-FET while still satisfying the Fermi-FET criteria. The tub depth is maintained below a maximum tub depth. Short channel effects may also be reduced by providing source and drain extension regions in the substrate, adjacent the source and drain regions and extending towards the channel regions.

Abstract: An H-transistor, fabricated in a silicon-on-insulator ("SOI") substrate, includes opposing source and drain terminals or regions flanking a centrally-located body node or well. Above the body node or well is formed the H-shaped gate terminal of the transistor. One or more shunt body contacts or ties bisect the source terminal and connect the source terminal of the transistor to the underlying body node. In this way, the body node or well is no longer electrically "floating", but, instead, is connected to the fixed ground potential of the source terminal of the transistor.

Abstract: In an amplifying type solid-state imaging device having a pixel MOS transistor, the occurrence of blooming can be suppressed and an amount of signal charges can be increased. A second conductivity-type overflow-barrier region (23) and a first conductivity-type semiconductor region (24) are sequentially formed on a first conductivity-type semiconductor substrate (22). A pixel MOS transistor (29) comprising a source region (27), a drain region (28) and a gate portion (26) is formed on the first conductivity-type semiconductor region (24), and a second conductivity-type channel stopper region (41) for signal charges accumulated in the first conductivity-type semiconductor region (24) of the gate portion (26) is formed within the first conductivity-type semiconductor region (24) formed just below the drain region (28).

Abstract: A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p.sup.- impurity region and p.sup.+ impurity regions. The p.sup.- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p.sup.+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.