Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.

Abstract: Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction.

Abstract: A quantum computer architecture employs logical qubits that are constructed from a concatenation of doubly periodic Josephson junction circuits. The series concatenation of the doubly periodic Josephson junction circuits provides exponential robustness against local noise. It is possible to perform discrete Clifford group rotations and entangling operations on the logical qubits without leaving the protected state.

Abstract: Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers.

Abstract: Nanopatch antennas and related methods for enhancing and tailoring are disclosed. According to an aspect, an apparatus includes a conductive material defining a substantially planar surface. The apparatus also includes a conductive nanostructure defining a substantially planar surface. The conductive material and the conductive nanostructure are positioned such that the planar surface of the conductive material faces the planar surface of the conductive nanostructure, such that the planar surfaces are substantially parallel, and such that the planar surfaces are spaced by a selected distance. The apparatus also includes an optically-active material positioned between the planar surfaces.

Abstract: Light-emitting devices are disclosed. In some embodiments, the devices may emit light when a tunneling current is generated within the device.

Abstract: Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers.

Abstract: Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting amorphous carbon doped with nitrogen and carbon-13 into an undercooled state followed by quenching. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits.

Abstract: An interconnect may have a first end coupled to a superconducting system and a second end coupled to a non-superconducting system. The interconnect may include a superconducting element having a critical temperature. During operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end may have a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end may have a second temperature above the critical temperature of the superconducting element, and the interconnect may further be configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

Abstract: The use of rectennas, or antenna-coupled rectifiers, using metal-insulator-metal tunnel diodes as rectifiers for energy conversion has been explored with more fervor recently, given the advances in nanotechnology fabrication and increased resolution of features. Some have made these devices from symmetric metals (e.g. Ni—NiO—Ni) and asymmetric metals (e.g. Al—AlOx/Pt), and have used deposited oxides as well as native oxides. One key to obtaining a highly asymmetric device with efficient current generation needed for high conversion efficiency is to instead use dissimilar metals and a thin reproducible oxide. The described method allows for a thin, reproducible native oxide of nickel be integrated with any antenna metal to overcome oxide surface roughness problems that typically hamper the practicality of these devices.

Abstract: Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: A pyroelectric detector includes a substrate, a support member and a pyroelectric detection element, which includes a capacitor, first and second reducing gas barrier layers, an insulating layer, a plug and a second electrode wiring layer. The first reducing gas barrier layer covers at least a second electrode and a pyroelectric body of the capacitor, and has a first opening that overlaps the second electrode in plan view. The insulating layer covers at least the first reducing gas barrier layer, and has a second opening that overlaps the first opening in plan view. The plug is disposed in the first and second openings and connected to the second electrode. The second electrode wiring layer is formed on the insulating layer and connected to the plug. The second reducing gas barrier layer is formed on the insulating layer and the second electrode wiring layer and covers at least the plug.

Abstract: An electrically pumped optoelectronic semiconductor chip includes at least two radiation-active quantum wells comprising InGaN or consisting thereof. The optoelectronic semiconductor chip includes at least two cover layers which include AlGaN or consist thereof. Each of the cover layers is assigned to precisely one of the radiation-active quantum wells. The cover layers are each located on a p-side of the associated radiation-active quantum well. The distance between the radiation-active quantum well and the associated cover layer is at most 1.5 nm.

Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.

Abstract: Methods and apparatus characterized by distinct operating modes are provided. A thin graphite material defined by graphene layers is supported on a silicon substrate. The graphite material is defined by edge sites at the interface with the silicon. The graphite material is characterized by electrical superconductive-like behavior at room-temperatures while electrical current flows there through in a first direction. The graphite material is further characterized by a transition to Ohmic behavior while electrical current flows there through in a second direction opposite to the first. Devices exhibiting diode-like behavior can be formed accordingly.

Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.

Abstract: A multilayer structure with zirconium-oxide tunnel barriers. In one embodiment, the multilayer structure includes a first niobium (Nb) layer, a second niobium (Nb) layer, and a plurality of zirconium-oxide tunnel barriers sandwiched between the first niobium (Nb) layer and the second niobium (Nb) layer, wherein the plurality of zirconium-oxide tunnel barriers is formed with N layers of zirconium-oxide, N being an integer greater than 1, and M layers of zirconium, M being an integer no less than N, such that between any two neighboring layers of zirconium-oxide, a layer of zirconium is sandwiched therebetween.

Abstract: The present disclosure relates to a semiconductor light emitting device which generates light by recombination of electrons and holes, and which includes: a first finger electrode for supplying one of the electrons and holes, a second finger electrode supplying the other of the electrons and holes, and spaced apart from the first finger electrode at a first interval; and a third finger electrode electrically connected to the first finger electrode, and spaced apart from the second finger electrode at a second interval which is smaller than the first interval.

Abstract: A Josephson junction (JJ) device includes a buffered substrate comprising a first buffer layer formed on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer includes a hexagonal compound structure. A trilayer structure is formed on the buffered substrate comprising at least two layers of a superconducting material. A thin tunnel barrier layer is positioned between the at least two layers. The buffered substrate is used to minimize lattice mismatch and interdiffusion in the trilayer structure so as to allow the JJ device to operate above 20 K.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice. Various platforms can be used to physically implement such a quantum computer. Platforms include an optical lattice, a Josephson junction array, a quantum dot, and a crystal structure. Each platform comprises an appropriate array of associated sites that can be used to approximate a desired Kagome geometry. A charge controller is desirably electrically coupled to the platform so that the array may be manipulated as desired.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.

Abstract: A multilayer structure with zirconium-oxide tunnel barriers. In one embodiment, the multilayer structure includes a first niobium (Nb) layer, a second niobium (Nb) layer, and a plurality of zirconium-oxide tunnel barriers sandwiched between the first niobium (Nb) layer and the second niobium (Nb) layer, wherein the plurality of zirconium-oxide tunnel barriers is formed with N layers of zirconium-oxide, N being an integer greater than 1, and M layers of zirconium, M being an integer no less than N, such that between any two neighboring layers of zirconium-oxide, a layer of zirconium is sandwiched therebetween.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: A light-emitting device includes a GaN substrate; a n-type AlxGa1-xN layer on a first main surface side of the GaN substrate; a p-type AlxGa1-xN layer positioned further away from the GaN substrate compared to the n-type AlxGa1-xN layer; a multi-quantum well (MQW) positioned between the n-type AlxGa1-xN layer and the p-type AlxGa1-xN layer. In this light-emitting device, the p-type AlxGa1-xN layer side is down-mounted and light is emitted from the second main surface, which is the main surface of the GaN substrate opposite from the first main surface. hemispherical projections are formed on the second main surface of the GaN substrate.

Abstract: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate.

Abstract: An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 ?-?m2, and in some cases a minimum specific contact resistance.

Abstract: A method and apparatus that converts energy provided by a chemical reaction into energy for charging a quantum well device. The disclosed apparatus comprises a catalyst layer that catalyzes a chemical reaction and captures hot electrons and hot phonons generated by the chemical reaction, and an interface layer placed between the catalyst layer and a quantum well. The interface layer facilitates the transfer of hot electrons and hot phonons from the catalyst layer into the quantum well layer. The interface layer can also convert hot electrons into hot phonons, and vice versa, depending upon the needs of the particular quantum well device. Because the hot electrons and the hot phonons are unstable and readily degrade into heat energy, the dimensions of the catalyst layer and the interface layer are very small. To improve the efficiency of the transfer of hot electrons and hot phonons to the quantum well, other interface layers, such as a catalyst interlayer and a catalyst interface, may be utilized.

Abstract: A structure comprising a tank circuit inductively coupled to a flux qubit or a phase qubit. In some embodiments, a low temperature preamplifier is in electrical communication with the tank circuit. The tank circuit comprises an effective capacitance and an effective inductance that are in parallel or in series. In some embodiments, the effective inductance comprises a multiple winding coil of wire. A method that includes the steps of (i) providing a tank circuit and a phase qubit that are inductively coupled, (ii) reading out a state of the phase qubit, (iii) applying a flux to the phase qubit that approaches a net zero flux, (iv) increasing a level of flux applied to the phase qubit, and (v) observing a response of the tank circuit in a readout device.

Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.

Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).

Abstract: A MOS transistor with a controlled threshold voltage includes a SOI which includes a substrate composed of a semi-conducting material, a single crystal layer composed of a semi-conducting material and an insulating layer interposed between the substrate and the single crystal layer. The single crystal layer is formed therein with a source region, a drain region and a surrounded region surrounded by the source region and the drain region. The surrounded region includes a depletion layer having a composition surface which is in contact with the insulating layer. The MOS transistor comprises an EIB-MOS transistor of which the substrate is adapted to be applied with a voltage of a first polarity for inducing charges of a second polarity over the composition surface of the surrounded region.

Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.

Abstract: The present invention is related to methods and apparatus to produce a memory cell or resistance variable material with improved data retention characteristics and higher switching speeds. In a memory cell according to an embodiment of the present invention, silver selenide and a chalcogenide glass, such as germanium selenide (GexSe(1?x)) are combined in an active layer, which supports the formation of conductive pathways in the presence of an electric potential applied between electrodes. Advantageously, embodiments of the present invention can be fabricated with relatively wide ranges for the thicknesses of the silver selenide and glass layers.

Abstract: An assembly includes a device for receiving at least one input to produce an output. An antenna supports the device to transfer the input to the device and further to transfer the output from the device such that the antenna supports a selected one of the input and the output as a high frequency current. The antenna includes a peripheral configuration which confines high frequency current to at least one dominant path to oscillate therein. The other one of the input and the output is a lower frequency signal present at least generally throughout the antenna. At least one port is positioned away from the dominant path to isolate the lower frequency signal from high frequency current in the dominant path. The antenna is configured to support the lower frequency signal having a frequency in a low frequency range including zero to several terahertz.

Abstract: An assembly includes a device for receiving at least one input to produce an output. An antenna supports the device to transfer the input to the device and further to transfer the output from the device such that the antenna supports a selected one of the input and the output as a high frequency current. The antenna includes a peripheral configuration which confines high frequency current to at least one dominant path to oscillate therein. The other one of the input and the output is a lower frequency signal present at least generally throughout the antenna. At least one port is positioned away from the dominant path to isolate the lower frequency signal from high frequency current in the dominant path. The antenna is configured to support the lower frequency signal having a frequency in a low frequency range including zero to several terahertz.

Abstract: A Josephson junction includes first and second electrodes, each of which is formed of superconductive material. The first electrode has a first electrode face. A barrier of the junction extends from the first electrode to the second electrode. The barrier has a first barrier face opposing and adjoining the first electrode face. The barrier is formed of non-superconductive barrier material and superconductive barrier material. A concentration of the superconductive barrier material is greater than zero at the first barrier face, whereby the first barrier face is formed at least partially of the superconductive barrier material.

Abstract: An article including a substrate, a layer of an inert oxide material upon the surface of the substrate, a layer of an amorphous oxide or oxynitride material upon the inert oxide material layer, a layer of an oriented cubic oxide material having a rock-salt-like structure upon the amorphous oxide material layer, and a layer of a SrRuO3 buffer material upon the oriented cubic oxide material layer is provided together with additional layers such as a HTS top-layer of YBCO directly upon the layer of a SrRuO3 buffer material layer. With a HTS top-layer of YBCO upon at least one layer of the SrRuO3 buffer material in such an article, Jc's of up to 1.3×106 A/cm2 have been demonstrated with projected Ic's of over 200 Amperes across a sample 1 cm wide.

Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.

Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9° K having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.

Abstract: An active semiconductor device is made using planar lateral oxidation to define a core region that is surrounded by regions of buried oxidized semiconductor material in. The buried oxidized semiconductor material provides optical waveguiding, and or a defined electrical path.

Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A &lgr;/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.

Abstract: A superconductor integrated circuit (10) includes a silicon substrate (12) a niobium ground layer (14), an anodized niobium first ground insulator layer (16), a second ground insulator layer (22), a molybdenum nitrogen (MoNx) resistor (18) provided between the first and second ground insulator layers (16, 22), a Josephson junction (23) provided above the first and second ground insulator layers (16, 22), first and second oxide insulators (27, 30), and a niobium interconnect (28) for providing electrical communication with the Josephson junction. The MoNx first resistor (18) provides a sheet resistance of between 3-5 ohms/sq at 4° K with a thickness of approximately 95 nm and enables the superconductor integrated circuit (10) to have a critical current density between 6-8 kA/cm2.

Abstract: A superconducting qubit is presented. The qubit is a shaped long Josephson junction with a magnetic fluxon such that, in the presence of an externally applied magnetic field, a fluxon potential energy function indicating a plurality of pinning sites in the qubit is produced. In one embodiment, a heart-shaped Josephson junction is formed where a trapped fluxon has a double-welled potential energy function, indicating two pinning sites, when the junction is placed in an externally applied magnetic field. The qubit is manipulated by preparing an initial state, creating a superposition of the two states by decreasing the magnetic field, evolving of the quantum state with time, freezing in a final state by increasing the magnetic field, and reading out the final state. In other embodiments, qubit exhibiting potential energy functions having any number of pinning sites can be realized.

Abstract: Quantum computing systems and methods that use opposite magnetic moment states read the state of a qubit by applying current through the qubit and measuring a Hall effect voltage across the width of the current. For reading, the qubit is grounded to freeze the magnetic moment state, and the applied current is limited to pulses incapable of flipping the magnetic moment. Measurement of the Hall effect voltage can be achieved with an electrode system that is capacitively coupled to the qubit. An insulator or tunnel barrier isolates the electrode system from the qubit during quantum computing. The electrode system can include a pair of electrodes for each qubit. A readout control system uses a voltmeter or other measurement device that connects to the electrode system, a current source, and grounding circuits. For a multi-qubit system, selection logic can select which qubit or qubits are read.

Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.

Abstract: In a method of manufacturing a Josephson junction, a first superconductive layer is formed on a substrate. An insulating film is formed on the first superconductive layer. The insulating film is etched to have an inclination portion. The first superconductive layer is etched using the etched insulating film as a mask, to have an inclination portion. A barrier layer is formed on a surface of the inclination portion of the first superconductive layer. A second superconductive layer is formed on the barrier layer and the inclination portion of the insulating layer.

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.