At Least One Electrode Layer Of Semiconductor Material Patents (Class 257/37)
  • Patent number: 10014373
    Abstract: Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mattias Borg, Kirsten Moselund, Heinz Schmid, Heike Riel
  • Patent number: 8981347
    Abstract: A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: March 17, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8941151
    Abstract: In the condition where a nozzle for applying a coating liquid is disposed on the lower side of a substrate and a substrate surface controlled in wettability is faced down, the nozzle and the substrate are moved relative to each other, whereby the coating liquid is applied to a desired region of the substrate, and then the coating liquid is dried, to obtain a pattern included a dried coating layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 27, 2015
    Assignee: Sony Corporation
    Inventor: Akihiro Nomoto
  • Patent number: 8796669
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a source region of a first conductivity type disposed on a surface of the substrate. The device further includes a tunnel insulator disposed on the source region, and an impurity semiconductor layer of a second conductivity type disposed on the tunnel insulator, the second conductivity type being different from the first conductivity type. The device further includes a gate insulator disposed on the impurity semiconductor layer, and a gate electrode disposed on the gate insulator. The device further includes a drain region of the second conductivity type disposed on the substrate so as to be separated from the impurity semiconductor layer, or disposed on the substrate as a portion of the impurity semiconductor layer.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takahisa Kanemura
  • Patent number: 8710652
    Abstract: An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to is the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 29, 2014
    Assignee: SK Hynix Inc.
    Inventor: Qwan Ho Chung
  • Publication number: 20130321064
    Abstract: Systems and methods related to single molecule switching devices are disclosed. One example method can include the step of applying a tunneling current across a tunneling junction. The tunneling junction can include an endohedral fullerene that includes a fullerene cage and a trapped cluster or a trapped atom. Such a method can also include exciting one or more internal motions of the trapped cluster or the trapped atom based at least in part on the tunneling current, and changing the conductance of the endohedral fullerene based at least in part on the one or more excited internal motions. One or more electronic processes can be controlled based at least in part on the changed conductance of the endohedral fullerene.
    Type: Application
    Filed: May 21, 2013
    Publication date: December 5, 2013
    Applicant: University of Pittsburgh Of the Commonwealth System of Higher Education
    Inventors: Hrvoje Petek, Tian Huang, Jin Zhao
  • Patent number: 8546924
    Abstract: Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 1, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Kuang Yu, Chun-Kai Liu, Ra-Min Tain
  • Patent number: 8344353
    Abstract: A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: January 1, 2013
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Kuen-Ru Chuang, Shu-Wen Sung, Chia-Cheng Liu, Chao-Nien Huang, Shane-Shyan Wey, Chih-Chiang Lu, Ming-Jiunn Jou
  • Patent number: 8278650
    Abstract: An organic semiconductor includes: a compound represented by formula (I): wherein A1 represents O, S or N—R15; each of R11, R12, R13, R14 and R15 independently represents a hydrogen atom or a substituent W as defined in the specification, R11 and R12 may be linked to form a ring; B1 represents a ring structure containing at least one nitrogen atom; and n1 represents an integer of 0 to 2.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: October 2, 2012
    Assignee: FUJIFILM Corporation
    Inventors: Kimiatsu Nomura, Tetsuro Mitsui, Hideyuki Suzuki, Rui Shen
  • Patent number: 8274096
    Abstract: The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: September 25, 2012
    Assignee: University of Rochester
    Inventor: Gary W. Wicks
  • Patent number: 8263480
    Abstract: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: September 11, 2012
    Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry Foundation
    Inventors: Eun Kyung Lee, Byoung Lyong Choi, Young Kuk, Je Hyuk Choi, Hun Huy Jung
  • Patent number: 8242717
    Abstract: A light output device comprises a substrate arrangement comprising a plurality of light source circuits integrated into the structure of the substrate arrangement. Each light source circuit comprises a light source device arrangement (4) having two terminals and a transistor circuit (7). Each light source circuit is supplied with power from an associated pair the power connections (10,11,14,15,20), and at least two light source circuits (4,7) share the same pair of power connections. A set of control connections (18) are provided for receiving external control signals for controlling the transistor circuits (7). A set of non-overlapping electrodes (10,11,14,15,18,20) provide the internal connections between the power connections, the light source device terminals and the transistor circuits, and each light source device is individually independently controllable.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: August 14, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Maarten Marinus Johannes Wilhelmus Van Herpen, Petrus Johannes Bremer, Coen Theodorus Hubertus Fransiscus Liedenbaum
  • Patent number: 8173992
    Abstract: A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second block forming an anode. The first block and the second block are supported on the substrate, and are separated from each other by a channel insulating zone also supported on the substrate. A gate dielectric zone is supported on at least the channel insulating zone, and a gate is supported on the gate dielectric zone.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 8, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Thomas Skotnicki, Stephane Monfray
  • Patent number: 7807508
    Abstract: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts on the rear surface. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: October 5, 2010
    Assignee: Tessera Technologies Hungary Kft.
    Inventors: Vage Oganesian, Andrey Grinman, Charles Rosenstein, Felix Hazanovich, David Ovrutsky, Avi Dayan, Yulia Aksenton, Ilya Hecht
  • Patent number: 7745323
    Abstract: Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and an upper metal interconnection layer disposed on the intermetallic dielectric layer and electrically connected through the intermetallic dielectric layer and buffer layer to the lower metal interconnection layers.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 29, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong-Su Park, Su Ho Kim
  • Patent number: 7738280
    Abstract: An object of the present invention is to provide a resistive nonvolatile memory element having an electric current path which can be realized by a simple and convenient process, and capable of allowing for micro-fabrication. The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm arranged on the oxide semiconductor layer 204a, tunnel barrier layer 204c formed on the oxide semiconductor layer 204a and on the metal nanoparticles 204b, and second electrode 206 formed on the tunnel barrier layer 204c, in which the metal nanoparticles 204b are in contact with the oxide semiconductor layer 204a.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventors: Shigeo Yoshii, Ichiro Yamashita
  • Patent number: 7696097
    Abstract: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: April 13, 2010
    Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry Foundation
    Inventors: Eun Kyung Lee, Byoung Lyong Choi, Young Kuk, Je Hyuk Choi, Hun Huy Jung
  • Publication number: 20100044680
    Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the ?-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.
    Type: Application
    Filed: October 23, 2009
    Publication date: February 25, 2010
    Inventors: LIUBO HONG, Cheng Horng, Mao-Min Chen, Ru-Yin Tong
  • Patent number: 7598514
    Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ?=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 6, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael H. Freedman, Chetan V. Nayak, Sankar Das Sarma
  • Patent number: 7550757
    Abstract: A back-surface-electrode type semiconductor laser of GaN-based compound has low electric resistance and high light emitting efficiency, and includes negative electrodes made of Al having a contact surface that contacts with the n-type GaN substrate. The back-surface-electrode type semiconductor laser has GaN-based compound layers laminated on an n-type GaN substrate with an area of reversal of polarity with low electric resistance and a negative electrode is disposed on the side opposite to the side of GaN-based compound layer of the GaN substrate so as to come in contact with the area of reversal of polarity.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: June 23, 2009
    Assignee: Rohm Co., Ltd.
    Inventors: Hiroaki Ohta, Shinichi Kohda
  • Patent number: 7534710
    Abstract: The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts. Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter-well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yasunao Katayama, Dennis M. Newns, Chang C. Tsuei
  • Publication number: 20090057653
    Abstract: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.
    Type: Application
    Filed: March 19, 2008
    Publication date: March 5, 2009
    Applicants: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION
    Inventors: Eun Kyung LEE, Byoung Lyong CHOI, Young KUK, Je Hyuk CHOI, Hun Huy JUNG
  • Patent number: 7449713
    Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: November 11, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mizuki Ono
  • Patent number: 7405421
    Abstract: The present invention provides an optical device integrating an active device with a passive device without any butt joint structure between two devices. The optical integrated device of the invention includes a GaAs substrate, first and second cladding layers, and an active layer sandwiched by the first and second cladding layers. These layers are disposed on the GaAs substrate. The GaAs substrate provides a first region and a second region. The active layer comprises of the first active layer disposed on the first region and the second active layer disposed on the second region of the GaAs substrate. The first active layer has a quantum well structure whose band-gap energy smaller than 1.3 eV, while the second active layer has a quantum well structure whose band-gap energy is greater than that of the first active layer.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: July 29, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun-ichi Hashimoto, Tsukuru Katsuyama, Kenji Koyama
  • Publication number: 20080149920
    Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Michael L. Chabinyc, William S. Wong
  • Patent number: 7259406
    Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content)guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 21, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
  • Patent number: 7250648
    Abstract: Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: July 31, 2007
    Assignee: Intematix Corporation
    Inventors: Yi-Qun Li, Young Yoo, Qizhen Xue, Ning Wang, Daesig Kim
  • Patent number: 7167387
    Abstract: The present invention lowers a drive voltage of a RRAM, which is a promising low power consumption, high-speed memory and suppresses variations in the width of an electric pulse for realizing a same resistance change. The present invention provides a variable resistance element including: a first electrode; a layer in which its resistance is variable by applying an electric pulse thereto, the layer being formed on the first electrode; and a second electrode formed on the layer; wherein the layer has a perovskite structure; and the layer has at least one selected from depressions and protrusions in an interface with at least one electrode selected from the first electrode and the second electrode.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: January 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Sugita, Akihiro Odagawa, Hideaki Adachi, Satoshi Yotsuhashi, Tsutomu Kanno, Kiyoshi Ohnaka
  • Patent number: 7157731
    Abstract: In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: January 2, 2007
    Assignee: Fujitsu Limited
    Inventors: Toshio Taniguchi, Taiji Ema, Toru Anezaki
  • Patent number: 7078855
    Abstract: A light device includes an electron supply defining an emitter surface. A dielectric tunneling layer is disposed between the electron supply and a cathode layer. The cathode layer has at least partial photon transparency that is substantially uniform across the emitter surface.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: July 18, 2006
    Inventors: Zhizhang Chen, Sriram Ramamoorthi, Terry E McMahon, Timothy F. Myers
  • Patent number: 6914256
    Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 5, 2005
    Assignee: North Carolina State University
    Inventors: Zhibo Zhang, Veena Misra, Salah M. A. Bedair, Mehmet Ozturk
  • Patent number: 6888156
    Abstract: The invention provides a thin film device where ionic crystals are epitaxially grown on a Si single crystal substrate through a proper buffer layer, and its for fabrication method. A ZnS layer is first deposited on a Si single crystal substrate. Ionic crystal thin films (an n-GaN layer, a GaN layer, and a p-GaN layer) are deposited thereon. The ZnS thin film is an oriented film excellent in crystallinity and has excellent surface flatness. When ZnS can be once epitaxially grown on the Si single crystal substrate, the ionic crystal thin films can be easily epitaxially grown subsequently. Therefore, ZnS is formed to be a buffer layer, whereby even ionic crystals having differences in lattice constants from Si can be easily epitaxially grown in an epitaxial thin film with few lattice defects on the Si single crystal substrate. The characteristics of a thin film device utilizing it can be enhanced.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: May 3, 2005
    Assignees: National Institute for Materials Science, Tokyo Institute of Technology, Fuji Electric Corporate Research & Development, Ltd.
    Inventors: Toyohiro Chikyow, Hideomi Koinuma, Masashi Kawasaki, Yoo Young Zo, Yoshinori Konishi, Yoshiyuki Yonezawa
  • Patent number: 6882100
    Abstract: A light device includes an electron supply defining an emitter surface. A dielectric tunneling layer is disposed between the electron supply and a cathode layer. The cathode layer has at least partial photon transparency that is substantially uniform across the emitter surface.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: April 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhizhang Chen, Sriram Ramamoorthi, Terry E McMahon, Timothy F. Myers
  • Patent number: 6878958
    Abstract: A vertical cavity surface-emitting laser (VCSEL) structure and related fabrication methods are described, the VCSEL comprising amorphous dielectric distributed Bragg reflectors (DBRs) while also being capable of fabrication in a single-growth process. Beginning with a substrate such as InP, a first amorphous dielectric DBR structure is deposited thereon, but is limited in width such that some substrate material remains uncovered by the dielectric material. A lateral overgrowth layer is then formed by epitaxially growing material such as InP onto the substrate, the lateral overgrowth layer eventually burying the dielectric DBR structure as well as the previously-uncovered substrate material. Active layers may then be epitaxially grown on the lateral overgrowth layer, and a top dielectric DBR may be deposited thereon using conventional techniques. To save vertical space between DBRs, the first DBR may be deposited in a non-reentrant well formed in the surface of a substrate.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 12, 2005
    Assignee: Gazillion Bits, Inc.
    Inventor: Zuhua Zhu
  • Patent number: 6844571
    Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: January 18, 2005
    Assignee: Lumileds Lighting U.S., LLC
    Inventors: Michael R Krames, Daniel A. Steigerwald, Fred A. Kish, Jr., Pradeep Rajkomar, Jonathan J. Wierer, Jr., Tun S Tan
  • Patent number: 6833556
    Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 &OHgr;-&mgr;m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: December 21, 2004
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 6750477
    Abstract: In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: June 15, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Toshiyuki Ohno, Hidekatsu Onose, Saburo Oikawa
  • Patent number: 6710382
    Abstract: A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 23, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroko Kubo, Kenji Yoneda
  • Patent number: 6670652
    Abstract: The monolithically integrated Enhancement/Depletion mode HEMT (high-electron-mobility transistor) of the present invention comprises: a buffer layer, a channel layer, a spacer layer, a first barrier layer, a second barrier layer, a third barrier layer, and an ohmic layer consecutively formed on a semiconductor substrate from bottom to top; the first exposed region (a gate region for a Depletion-mode HEMT) formed by selective etching of the ohmic layer to expose the third barrier layer; a second exposed region (a gate region for an Enhancement-mode HEMT) formed by selective etchings of the ohmic layer and the third barrier layer to expose the second barrier layer; and gate electrodes formed on the first and second exposed gate regions. According to the present invention, a monolithically integrated Enhancement/Depletion mode HEMT having a uniform threshold voltage can easily be fabricated.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: December 30, 2003
    Assignee: Kwangju Institute of Science and Technology
    Inventor: Jong-In Song
  • Publication number: 20030173562
    Abstract: A particle detector assembly comprises a superconducting absorber to which is coupled at least two superconducting tunnel junction detectors for detecting particles incident on the absorber. Each superconducting tunnel junction detector comprises at least two superconducting tunnel junction devices connected in parallel.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 18, 2003
    Applicant: Oxford Instruments Superconductivity Ltd.
    Inventor: David John Goldie
  • Publication number: 20030160233
    Abstract: Predetermined regions of a transistor are activated using a buried energy absorbing layer. The buried energy absorbing layer is under a semiconductor layer, in which a transistor is being formed. Amorphous regions are formed within the semiconductor layer on either side of a control electrode and a gate dielectric. An energy source with a wavelength that is not absorbed by the amorphous regions or the control electrode is applied to the transistor and absorbed by the energy absorbing layer. The energy absorbing layer transfers the energy into heat, which is at a temperature greater than or equal to the melting temperature of the amorphous regions and less than the melting temperature of the semiconductor layer. Due to the heat, the amorphous regions melt and recrystallize, thereby becoming electrically active. However, the control electrode does not melt.
    Type: Application
    Filed: February 28, 2002
    Publication date: August 28, 2003
    Inventors: Michael J. Rendon, William J. Taylor, David C. Sing
  • Publication number: 20030107034
    Abstract: The invention concerns an optoelectronic device comprising at alteration of at least three semiconductor layers with selected shape, and two air layers. The semiconductor layers having N-type or P-type doping which may differ or not from one layer to the next layer, are separated by spacers whereof the doping is non-intentional (I-type) or intentional (N-type or P-type) to define a PINIP or NIPIN structure with air cavities, and are adapted to be set at selected respective electric potentials. The respective thicknesses and compositions of the layers and the spacers are selected so that the structure has at least an optical transfer function adapted to light to be treated and adjustable in accordance with the selected potentials applied to the semiconductor layers.
    Type: Application
    Filed: September 3, 2002
    Publication date: June 12, 2003
    Applicants: Centre National De La Recherche Scientifique, Ecole Centrale De Lyon
    Inventors: Pierre Viktorovitch, Jean-Louis Leclercq, Christian Seassal, Alain Spisser, Michel Garrigues
  • Patent number: 6525379
    Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: February 25, 2003
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
  • Patent number: 6518673
    Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: February 11, 2003
    Assignee: TRW Inc.
    Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber
  • Patent number: 6479863
    Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, and a floating gate electrode disposed adjacent the retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: November 12, 2002
    Inventor: John M. Caywood
  • Patent number: 6337293
    Abstract: A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: January 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Ishii, Kazuo Yano, Koichi Seki, Toshiyuki Mine, Takashi Kobayashi
  • Publication number: 20010054709
    Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.
    Type: Application
    Filed: July 17, 2001
    Publication date: December 27, 2001
    Inventors: James R. Heath, R. Stanley Williams, Philip J. Kuekes
  • Patent number: 6087711
    Abstract: The present invention discloses an integrated circuit that is wired with a high-temperature superconductive material that is superconductive at temperatures of about 70.degree. K and above, and methods of making the integrated circuit. The front-end manufactured semiconductor structure is patterned with a preferred precursor metal or metal oxide and a complementary compound is superposed and reacted to form wiring lines of superconductor ceramics that complete integrated circuits within the front-end manufactured semiconductor structure. The front-end manufactured semiconductor structure is alternatively patterned first with the complementary compound and the precursor metal is thinly patterned by ion implantation. The front-end manufactured semiconductor structure is then treated to form wiring lines of superconductor ceramics that complete integrated circuits within structure.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: July 11, 2000
    Assignee: Micron Technology Inc.
    Inventor: John H. Givens
  • Patent number: 6037606
    Abstract: In an MIM or MIS electron source that is formed by a first conductive layer 101, an insulating layer 103 that is formed onto said first conductive layer 101, and a second conductive layer 104 that is formed onto said insulating layer 103, wherein a voltage is applied between said first and second conductive layers 101,104, so as to cause a tunneling current to occur in said insulating layer 103, the film thickness of said insulating layer 103 and the film thickness of said second conductive layer 104 are formed so as to be uniform.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: March 14, 2000
    Assignee: NEC Corporation
    Inventor: Takahiro Ema
  • Patent number: RE42422
    Abstract: A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: June 7, 2011
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Kuen-Ru Chuang, Shu-Wen Sung, Chia-Cheng Liu, Chao-Nien Huang, Shane-Shyan Wey, Chih-Chiang Lu, Ming-Jiunn Jou