Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Abstract: Disclosed are an ultrasound imaging system for analysis of a body composition and an operation method of an ultrasound imaging system which is designed for analysis of a body composition. An ultrasound imaging system may include: a scan device into which an object is insertable; an ultrasonic probe connected to a part of the scan device; a controller configured to control the ultrasonic probe to emit a transmission ultrasonic signal to the object at multiple positions at the scan device, and receive a reflection ultrasonic signal reflected from the object; and an image processor configured to generate multiple 2D ultrasound images based on reflection ultrasonic signals received at the multiple positions at the scan device, respectively, and generate a 3D ultrasound image based on the multiple 2D ultrasound images.

Abstract: Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package.

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

Abstract: In some embodiments, a laminate substrate for mounting RF components can include a plurality of layers vertically stacked on top of each other. The laminate substrate includes a plurality of conductor pads, such that a respective conductor pad is positioned within a respective layer of the laminate substrate. The plurality of conductor pads includes an input pad on a first layer, an output pad on a second layer such that the output pad does not completely overlap with the input pad, and at least one intermediate pad between the input and output pads. The at least one intermediate pad defines a cutout reducing overlap between the at least one intermediate pad and one or more neighboring conductor pads. The laminate substrate can further include a plurality of connection features between the plurality of conductor pads to provide a signal path between the input pad and the output pad.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Abstract: A method of forming a semiconductor structure in which a III-V compound semiconductor channel fin portion is formed on a dielectric material is provided. The method includes forming a III-V material stack on a surface of a bulk semiconductor substrate. Patterning of the III-V material stack is then employed to provide a pre-fin structure that is located between, and in contact with, pre-pad structures. The pre-pad structures are used as an anchoring agent when a III-V compound semiconductor channel layer portion of the III-V material stack and of the pre-fin structure is suspended by removing a topmost III-V compound semiconductor buffer layer portion of the material stack from the pre-fin structure. A dielectric material is then formed within the gap provided by the suspending step and thereafter a fin cut process is employed.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: In one embodiment, a semiconductor device includes a substrate, and a source region of a first conductivity type disposed on a surface of the substrate. The device further includes a tunnel insulator disposed on the source region, and an impurity semiconductor layer of a second conductivity type disposed on the tunnel insulator, the second conductivity type being different from the first conductivity type. The device further includes a gate insulator disposed on the impurity semiconductor layer, and a gate electrode disposed on the gate insulator. The device further includes a drain region of the second conductivity type disposed on the substrate so as to be separated from the impurity semiconductor layer, or disposed on the substrate as a portion of the impurity semiconductor layer.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract: Flexible remote control systems and methods avoiding customized control schemes for industrial vehicles are disclosed. The industrial vehicle has a base station and at least one auxiliary system to be remotely controlled by an operator using at least one of a plurality of different control input devices. The remote control system includes a processor-based remote control unit having a plurality of substantially identical connector interface ports each configured to receive associated ones of the plurality of different control input devices.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract: A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.

Abstract: A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TPET, the drain region comprises p-doped silicon, while the source region comprises n-doped SiC.

Abstract: A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential of data to be stored, and making the storage gate an insulator. Data is read by making the storage gate an insulator, supplying a potential to a read signal line connected to one of a source and a drain of the transistor, supplying a potential for reading data to the first control gate, and then detecting a potential of a bit line connected to the other of the source and the drain.

Abstract: A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.

Abstract: An organic semiconductor includes: a compound represented by formula (I): wherein A1 represents O, S or N—R15; each of R11, R12, R13, R14 and R15 independently represents a hydrogen atom or a substituent W as defined in the specification, R11 and R12 may be linked to form a ring; B1 represents a ring structure containing at least one nitrogen atom; and n1 represents an integer of 0 to 2.

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract: A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second block forming an anode. The first block and the second block are supported on the substrate, and are separated from each other by a channel insulating zone also supported on the substrate. A gate dielectric zone is supported on at least the channel insulating zone, and a gate is supported on the gate dielectric zone.

Abstract: A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A method for forming a nanowire tunnel device includes forming a nanowire suspended by a first pad region and a second pad region over a semiconductor substrate, forming a gate structure around a channel region of the nanowire, implanting a first type of ions at a first oblique angle in a first portion of the nanowire and the first pad region, and implanting a second type of ions at a second oblique angle in a second portion of the nanowire and the second pad region.

Abstract: A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The at least one of the source electrode, drain electrode, and the gate electrode includes a metallic carbon nanotube layer. The metallic carbon nanotube layer includes a plurality of metallic carbon nanotubes.

Abstract: A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths, which pass energy to quantum structures. Quantum structures may include quantum dot particles on the surface of the fiber or electrodes on top of barrier layers and a transport layer, which form quantum dot devices. The energy passing through the control paths drives charge carriers into the quantum dots, leading to the formation of “artificial atoms” with real-time, tunable properties. These artificial atoms then serve as programmable dopants, which alter the behavior of surrounding materials. The fiber can be used as a programmable dopant inside bulk materials, as a building block for new materials with unique properties, or as a substitute for quantum dots or quantum wires in certain applications.

Abstract: The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts. Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter-well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.

Abstract: More sensitive (especially due to reduced interference of flux noise) than a conventional SQUID, an inventive SQUID's major component is a hollow cylindric structure comprising one or more annular Josephson junctions. Each annular Josephson junction is defined by two superconductive annuli and an interposed non-superconductive annulus. Inventive practice is variable, e.g., in terms of number and/or spacing of Josephson junctions, and/or as having one or more shunts connecting two or more Josephson junctions, and/or as having one or more vortices each threaded through a Josephson junction. The inventive cylindric structure is positioned proximate a magnetic field of interest so that the latter is aligned with the longitudinal axis of the former.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: In a liquid crystal display device substrate, an insulating layer covers a thin film transistor. Another insulating layer covers a black matrix, which is formed on the insulating layer and covers the thin film transistor, a gate line, and a data line except a portion of a drain electrode. A first transparent conductive layer covers the top insulating layer and contacts the exposed portions of the drain electrode, a gate pad and a data pad. A buffer layer is formed on the first conductive layer and a color filter is formed on the buffer layer. The buffer layer is exposed by the color filter to reveal portions of the first conductive layer. A second transparent conductive layer covers the color filter and the revealed portions of the first conductive layer. The conductive layers are patterned to form pixel electrodes and double-layered gate and data pad terminals.

Abstract: To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract: Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract: A structure (and method) for a piezoelectric device, including a layer of piezoelectric material. A nanotube structure is mounted such that a change of shape of the piezoelectric material causes a change in a stress in the nanotube structure.

Abstract: In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.

Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 &OHgr;-&mgr;m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, and a floating gate electrode disposed adjacent the retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: The present invention relates on an interferometer arrangement comprising a source electrode and a drain electrode, a base electrode to which the source electrode and the drain electrode are connected through tunnel barriers, the base electrode thus forming a double barrier quantum well, and first and second superconducting gate electrodes to control the source-drain current. The base electrode comprises a ferromagnetic material enabling resonant tunneling of source-drain electrons when there are bound states within the quantum well structure matching the energy of said source-drain electrons. The invention also relates to a logical element comprising such an interferometer arrangement and to a method of controlling the conductance of an interferometer.

Abstract: An electron emission device exhibits a high electron emission efficiency. The device includes an electron supply layer of metal or semiconductor, an insulator layer formed on the electron supply layer, and a thin-film metal electrode formed on the insulator layer. The insulator layer is made of an amorphous dielectric substance and has a film thickness of 50 nm or greater and has an amorphous phase with an average grain size of 5 to 100 nm as a major component and a polycrystal phase as a minor component. When an electric field is applied between the electron supply layer and the thin-film metal electrode, the electron emission device emits electrons.

Abstract: A FET type superconducting device comprises a substrate having a principal surface, a thin superconducting channel formed of an oxide superconductor layer over the principal surface of the substrate, a superconducting source region and a superconducting drain region formed of an oxide superconductor layer over the principal surface of the substrate at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode, wherein the superconducting device is isolated by a isolation layer directly formed on the principal surface of the substrate, the superconducting layer of the su