Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a ferroelectric structure overlying a substrate. A pair of source/drain regions are disposed in the substrate. A gate dielectric layer overlies the substrate and is spaced laterally between the pair of source/drain regions. The ferroelectric structure overlies the gate dielectric layer. The ferroelectric structure includes a ferroelectric layer and a sidewall spacer structure, where the sidewall spacer structure continuously laterally wraps around the ferroelectric layer. The ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different than the first metal oxide.

Abstract: A photosensitive detector includes an array of detection units, each detection unit having a light-sensing transistor (1), a charge storage transistor (2) and a reading transistor (3), or comprising a light-sensing transistor, a charge transfer transistor (4), a charge storage transistor and a reading transistor. The light-sensing transistor is configured to realize the light-sensing function of the photosensitive detector; the charge storage transistor is configured to store photogenerated charges; the reading transistor is configured to read a signal; and, the charge transfer transistor is configured to control the transfer of the photogenerated charges. The photosensitive detector can realize global shutter and fast reading, and is compatible with the existing floating gate CMOS process, and the failure of any pixel will not affect the normal operation of the whole imaging array.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

Abstract: A method for fabricating MOSFET is disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures with reduced shorting and uniform chamfering, and methods of manufacture. The structure includes: a long channel device composed of a conductive gate material with a capping layer over the conductive gate material and extending to sides of the conductive gate material; and a short channel device composed of the conductive gate material and the capping layer over the conductive gate material.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of dummy gate structures on a substrate. Each dummy gate structure includes a gate dielectric layer, a dummy gate electrode, and two sidewall spacers. The method also includes forming a dielectric layer on the substrate between neighboring dummy gate structures and removing a portion of each dummy gate electrode to form a first opening. The first opening is surrounded by a remaining portion of the dummy gate electrode and the two sidewall spacers. The method further includes removing a portion of each sidewall spacer along a direction perpendicular to the sidewall of the first opening to form a second opening, removing the remaining portion of the gate electrode on the bottom of each second opening to form a third opening, and then filling each third opening with a gate electrode material to form a gate electrode.

Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.

Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal feature, and a semiconductor feature. The metal feature is disposed on the gate dielectric layer. The semiconductor feature is disposed on the gate dielectric layer. The metal feature and the semiconductor feature are stacked on the gate dielectric layer side by side.

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device comprises: a semiconductor substrate with an active area defined by a plurality of isolation features; a gate stack extending across the active area onto portions of the isolation features, wherein the gate stack comprising a gate dielectric layer on the active area and the portions of the isolation features, and a gate electrode on the gate dielectric layer; and a protective seal comprising a vertical portion lining sidewalls of the gate stack and a horizontal portion extending onto a top surface of the isolation features, wherein the horizontal portion surrounding portions of the gate stack outside the active area in a top view.

Abstract: A passive device and method of fabricating the passive device are disclosed herein. The capacitor structure incorporates a resistor and a capacitor. An exemplary method includes receiving a substrate that has undergone front end of line (FEOL) processing, and performing back end of line (BEOL) processing on the substrate, wherein a capacitor structure is formed over the substrate during the BEOL processing, the capacitor structure incorporating a resistor with a capacitor. The BEOL processing can include performing a first metallization process to form a bottom plate of the capacitor structure; forming a dielectric spacer of the capacitor structure over the bottom plate; forming a top plate of the capacitor structure over the dielectric spacer; and performing a second metallization process to form contacts coupled to the top plate and the bottom plate of the capacitor structure.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

Abstract: A high voltage device includes drift regions formed in a substrate, an isolation layer formed in the substrate to isolate neighboring drift regions, wherein the isolation layer has a depth greater than that of the drift region, a gate electrode formed over the substrate, and source and drain regions formed in the drift regions on both sides of the gate electrode.

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

Abstract: An exemplary embodiment provides a method which etches a second layer in a base body to be processed having a first layer containing Ni and Si and a second layer containing Si and N which are exposed to a surface thereof. The method according to the exemplary embodiment includes (a) preparing a base body to be processed in a processing chamber, and (b) supplying a first processing gas which contains carbon and fluorine but does not contain oxygen into the processing chamber and generating plasma in the processing chamber.

Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. A top of the protection element is wider than a bottom of the protection element. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function meta layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.

Abstract: High density films of semiconducting single-walled carbon nanotubes having a high degree of nanotube alignment are provided. Also provided are methods of making the films and field effect transistors (FETs) that incorporate the films as conducting channel materials. The single-walled carbon nanotubes are deposited from a thin layer of organic solvent containing solubilized single-walled carbon nanotubes that is continuously supplied to the surface of an aqueous medium, inducing evaporative self-assembly upon contacting a solid substrate.

Abstract: A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.

Abstract: The disclosure generally relates to a method for forming multiple III-V Tunnel Field-Effect Transistors (III-V TFETs) microchips in which each TFET has a different threshold voltage (Vt) or work-function. In one embodiment of the disclosure, four TFETs are formed on a substrate. Each TFET has a source, drain and a gate electrode. Each gate electrode is then processed independently to provide a substantially different threshold voltage. Each TFET will have an intrinsic channel.

Abstract: An integrated circuit includes a first FET structure and a second FET structure, both of which being formed over a silicon substrate. The first FET structure includes a high-k material layer, a layer of a first workfunction material formed over the high-k material layer, a layer of a barrier material formed over the first workfunction material layer; and a layer of a gate fill material formed over the barrier material layer. The entirety of the barrier material layer and the gate fill material layer are formed above the first workfunction material layer. The second FET structure includes a layer of the high-k material, a layer of a second workfunction material formed over the high-k material layer, a low-resistance material layer formed over the second workfunction material layer and a layer of the barrier material formed over the low-resistance material layer.

Abstract: A device having a first active transistor, a second active transistor, an isolation gate structure, and an active region underlying each of the first active transistor, the second active transistor, and the isolation gate structure is provided. The first and second active transistors each have a metal gate with a first type of conductivity (e.g., one of n-type and p-type). The isolation gate structure interposes the first and second active transistors. The isolation gate structure has a metal gate with a second type of conductivity (e.g., the other one of n-type and p-type). A method of fabricating devices such as this are also described.