With Permanent Threshold Adjustment (e.g., Depletion Mode) Patents (Class 257/402)
  • Patent number: 10714613
    Abstract: The present disclosure provides a fabrication method for forming a semiconductor device, including: forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between a first fin and an adjacent fin; forming a first mask layer on the substrate, the first fins, and the second fins; and removing portions of the first mask layer neighboring a first trench to expose a portion of a top surface of a first fin and a portion of a top surface of the adjacent second fin to form a first opening, a portion of the top surface of the first fin covered by a remaining portion of the first mask layer being a first fin device region, a portion of the top surface of the second fin covered by a remaining portion of the first mask layer being a second fin device region.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10707135
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Hao Tseng, Chien-Ting Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
  • Patent number: 10680088
    Abstract: A tunnel field effect transistor (TFET) device includes a substrate, heavily doped source and drain regions disposed at opposite ends of a channel region forming a PiN or NiP structure, the channel region including a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion having a second length defined along the longitudinal axis larger than the first length, the TFET device having an effective channel length that is an average of the first and second lengths. The channel region includes a channel material with a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, the first effective mass being greater than the second effective mass.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 9, 2020
    Assignee: Purdue Research Foundation
    Inventors: Hesameddin Ilatikhameneh, Tarek Ameen Beshari, Bozidar Novakovic, Gerhard Klimeck, Rajib Rahman
  • Patent number: 10553721
    Abstract: A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type. The semiconductor device further includes an isolation region over the substrate between a first fin of the plurality of fins and a second fin of the plurality of fins adjacent to the first fin. The semiconductor device further includes a second doped region extends continuously across the isolation region, the second doped region extends into each fin of the plurality of fins, and a dimension of the second doped region in the isolation region in a second direction perpendicular to the first direction is less than a dimension of the at least one isolation region in the second direction.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Chia-Chung Chen
  • Patent number: 10475788
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 10446672
    Abstract: A tunnel field-effect transistor (TFET) is provided. In the TFET, a channel region (202) connects a source region (201) and a drain region (203); a pocket layer (204) and a gate oxide layer (205) are successively produced between the source region and a gate region (206); a metal layer (208) is produced in a first area in the source region, the first area is located on a side on which the source region is in contact with the pocket layer, and the pocket layer covers at least a part of the metal layer; and the pocket layer and a second area in the source region form a first tunnel junction of the TFET, and the pocket layer and the metal layer form a second tunnel junction of the TFET.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 15, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xichao Yang, Chen-Xiong Zhang
  • Patent number: 10355081
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10340358
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate, a first active pattern disposed on the substrate and spaced apart from the substrate, a gate insulating film which surrounds the first active pattern, a first work function adjustment film which surrounds the gate insulating film and includes carbon, and a first barrier film which surrounds the first work function adjustment film, in which a carbon concentration of the first work function adjustment film increases as it goes away from the first barrier film.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung In Suh, Hoon Joo Na, Min Woo Song, Byoung Hoon Lee, Chan Hyeong Lee, Hu Yong Lee, Sang Jin Hyun
  • Patent number: 10304927
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10186598
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: January 22, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 10163908
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
  • Patent number: 10038080
    Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with the first dummy gate; forming a spacer layer in contact with the first dummy gate and the epitaxy structure; and replacing the first dummy gate with a metal gate stack.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Jung-Piao Chiu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10002948
    Abstract: A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9882048
    Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre, Junli Wang
  • Patent number: 9812370
    Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9793351
    Abstract: A tunneling field effect transistor, comprising a gate electrode layer, a gate dielectric layer, a source region, a connected region and a drain region, wherein the source region comprises a first source region and a second source region, the second source region comprising an inner layer source region and an outer layer source region. The connected region comprises an expansion region and a high-resistance region. The doping types of materials of the inner layer source and the outer layer source region are opposite, and the forbidden bandwidth of the material of the inner layer source region is less than that of the outer layer source region. The contact surface formed by way of covering the inner layer source region by the outer layer source region is a curved surface.
    Type: Grant
    Filed: September 1, 2014
    Date of Patent: October 17, 2017
    Assignee: Peking University Shenzhen Graduate School
    Inventors: Haijun Lou, Xinnan Lin, Dan Li, Jin He
  • Patent number: 9793397
    Abstract: A method is presented for forming a semiconductor device. The method includes forming an oxygen containing interfacial layer on a semiconductor substrate, forming a hafnium oxide layer on the interfacial layer, the hafnium oxide layer crystallizing to a non-centrosymmetric phase in a final structure, forming a first electrode containing a scavenging metal, which reduces a thickness of the interfacial layer via an oxygen scavenging reaction in the final structure, on the hafnium oxide layer, and forming a second electrode on the first electrode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Vijay Narayanan
  • Patent number: 9780189
    Abstract: Various methods and devices that involve body contacted transistors are disclosed. An exemplary method comprises forming a gate on a planar surface of a semiconductor wafer. The gate covers a channel of a first conductivity type that is opposite to a second conductivity type. The method also comprises implanting a body dose of dopants on a source side of the gate using the gate to mask the body dose of dopants. The body dose of dopants spreads underneath the channel to form a deep well. The body dose of dopants has the first conductivity type. The method also comprises implanting, subsequent to implanting the body dose of dopants, a source dose of dopants on the source side of the gate to form a source. The method also comprises forming a source contact that is in contact with the deep well at the planar surface of the semiconductor wafer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: October 3, 2017
    Assignee: Silanna Asia Pte Ltd
    Inventor: George Imthurn
  • Patent number: 9716155
    Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9704910
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 9647123
    Abstract: A semiconductor structure including vertical transistors is provided in which a sigma shaped source/drain extension region is formed between a top faceted surface of a first region of an epitaxial semiconductor channel material and a bottom faceted surface of a second region of the epitaxial semiconductor channel material. The sigma shaped source/drain extension region is formed after formation of a functional gate structure on each side of an epitaxial semiconductor channel material by first removing a sacrificial bottom spacer layer of a bottom spacer material stack, performing a sigma etch on an exposed lower portion of the epitaxial semiconductor channel material to provide the first region of epitaxial semiconductor channel material and the second region of the epitaxial semiconductor channel material, and then epitaxially growing the sigma shaped source/drain extension region from the faceted surfaces of the first and second regions of epitaxial semiconductor channel material.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9613961
    Abstract: According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiki Kamata
  • Patent number: 9525076
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho Lee, Hyun-jong Chung, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jin-seong Heo
  • Patent number: 9490334
    Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 9484459
    Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Stephan Kronholz, Gunda Beernink
  • Patent number: 9450063
    Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Prechtl
  • Patent number: 9431504
    Abstract: A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 30, 2016
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Yongkui Zhang, Zhiguo Zhao, Zhiyong Lu, Huilong Zhu
  • Patent number: 9412865
    Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning a dummy gate stack above an active channel layer formed on a base. The method also includes selectively etching the active channel layer leaving a remaining active channel layer, and epitaxially growing silicon doped active channel material adjacent to the remaining active channel layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9397116
    Abstract: A semiconductor device may include a first dielectric layer. The semiconductor device may further include a second dielectric layer overlapping the first dielectric layer and having a closed cavity structure. The semiconductor device may further include a first transistor disposed between the first dielectric layer and the closed cavity structure. The semiconductor device may further include a second transistor disposed between the first dielectric layer and the closed cavity structure. The semiconductor device may further include a trench isolation structure disposed between the first transistor and the second transistor and disposed between the first dielectric layer and the closed cavity structure.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: July 19, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Herb He Huang, Clifford I. Drowley
  • Patent number: 9362318
    Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 9236435
    Abstract: Tunneling field effect transistors are provided. The tunneling field effect transistor includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region and a second region adjacent to the drain region. A first energy band gap of the first region is lower than a second energy band gap of the second region, and the first region has a direct energy band gap.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xin-Gui Zhang, Tae-Yong Kwon, Sang-Su Kim
  • Patent number: 9236462
    Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 12, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9236122
    Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: January 12, 2016
    Assignee: SANDISK 3D LLC
    Inventors: Tianhong Yan, George Samachisa, Tz-yi Liu, Tim Chen, Perumal Ratnam
  • Patent number: 9093302
    Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Vimal K. Kamineni, Abner F. Bello, Nicholas V. LiCausi, Wenhui Wang, Michael Wedlake, Jason R. Cantone
  • Patent number: 9070769
    Abstract: According to embodiments, a semiconductor device includes a semiconductor substrate and an element isolation insulating film which isolates a element formation region in a surface portion of the semiconductor substrate. A depletion-type channel region of a first conductivity type is formed in an inner region which is in the element formation region of the semiconductor substrate and is a predetermined distance or more away from the element isolation insulating film. A gate electrode is formed above the element formation region with a gate insulating film located in between in such a manner as to traverse over the channel region and to overlap with portions of the element isolation insulating film which are located on both sides of the element formation region. Source/drain regions of the first conductivity type are formed in the channel region respectively on both sides of the gate electrode.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: June 30, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiki Kato
  • Patent number: 9059277
    Abstract: A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, wherein a lightly doped n-type drain region has a laterally non-uniform n-type dopant concentration distribution, which is achieved by forming a moderately n-type doped region, having a higher doping concentration and a greater depth than the rest portion of the lightly doped n-type drain region, in a portion of the lightly n-type doped region proximate to the polysilicon gate. The structure enables the RF LDMOS device of the present invention to have both a high breakdown voltage and a significantly reduced on-resistance. A method of fabricating such a RF LDMOS device is also disclosed.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: June 16, 2015
    Assignee: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventors: Juanjuan Li, Wensheng Qian, Feng Han, Pengliang Ci
  • Patent number: 9041126
    Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim
  • Publication number: 20150137268
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a channel layer formed of a Germanium compound having a Germanium concentration B formed on a semiconductor substrate having a Germanium concentration of A, the Germanium concentration of the substrate A being less than the Germanium concentration of the channel layer B. The structure further includes a capping layer formed to separate the channel layer from a metal gate, the capping layer having a Germanium concentration of C, the Germanium concentration of the channel layer B being greater than the Germanium concentration of the capping layer C.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANFACTURING COMPANY LIMITED
    Inventor: KA-HING FUNG
  • Patent number: 9029956
    Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: May 12, 2015
    Assignee: Global Foundries, Inc.
    Inventors: Randy W. Mann, Scott D. Luning
  • Publication number: 20150108586
    Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Jerome Ciavatti, Johannes M. van Meer
  • Patent number: 9006843
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 14, 2015
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Patent number: 8994117
    Abstract: A semiconductor chip having a P? substrate and an N+ epitaxial layer grown on the P? substrate is shown. A P? circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joel T. Ficke, David M. Friend, James D. Strom, Erik S. Unterborn
  • Publication number: 20150084136
    Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a polysilicon oxide layer, a central conductive layer, ion implantation layer, a channel region, and a metallic sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer, and a polysilicon oxide layer formed on the polysilicon structure. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. An ion implantation layer is formed within the guard ring and the central conductive layer. Afterwards, a metallic sputtering layer is formed, and the mask layer is partially exposed.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Inventors: Hung-Hsin Kuo, Mei-Ling Chen
  • Publication number: 20150076622
    Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Inventors: Bharat Krishnan, Jinping Liu, Zhao Lun, Hui Zhan, Bongki Lee
  • Patent number: 8981494
    Abstract: The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok Il Kwon, Hoijin Lee, Hyejoo Lee
  • Patent number: 8963249
    Abstract: A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Suvolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade
  • Publication number: 20150041904
    Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8952455
    Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8952462
    Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
  • Publication number: 20150035082
    Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventor: Chandra V. Mouli