Including Lightly Doped Drain Portion Adjacent Channel (e.g., Lightly Doped Drain, Ldd Device) Patents (Class 257/408)
  • Patent number: 10297602
    Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
  • Patent number: 10256344
    Abstract: The present disclosure relates to an oxide thin film transistor and a fabricating method thereof. In the oxide thin film transistor, which uses amorphous zinc oxide (ZnO) semiconductor as an active layer, damage to the oxide semiconductor due to dry etching may be minimized by forming source and drain electrodes in a multilayered structure having at least two layers, and improving stability and reliability of a device by employing a dual passivation layer structure, which includes a lower layer for overcoming an oxygen deficiency and an upper layer to minimize effects of an external environment on the multilayered source and drain electrodes.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 9, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventor: JongUk Bae
  • Patent number: 10249730
    Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Belyansky, Andrew Greene, Fee Li Lie, Huimei Zhou
  • Patent number: 10224418
    Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu
  • Patent number: 10217828
    Abstract: A method of forming a bulk transistor integrated with silicon-on-insulator (SOI) field plates, and related device, are provided. Embodiments include forming a silicon-on-insulator (SOI) substrate as a field plate on a field plate oxide; forming a high-voltage p-type well in a p-type substrate of a bulk transistor on which the SOI substrate is formed, the high-voltage p-type formed between shallow trench isolation (STI) region of the p-type substrate; forming an n-drift region in the high-voltage p-type well; forming a first gate on the high-voltage p-type well; and implanting a first n-type region adjacent to the gate as a source region and a second n-type region adjacent to the SOI substrate as a drain region.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yinjie Ding, Eng Huat Toh, Shyue Seng Tan
  • Patent number: 10163657
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun-Feng Nieh
  • Patent number: 10115820
    Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 30, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Chao Feng Yeh, TianChen Dong
  • Patent number: 10074736
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 10062692
    Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir K. Ray, Bharat V. Krishnan, Jinping Liu, Meera S. Mohan, Joseph K. Kassim
  • Patent number: 10032909
    Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10026840
    Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10020268
    Abstract: A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 10, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Zhe Wong, Ching-Hsiang Hsu, Ching-Sung Yang
  • Patent number: 10020394
    Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rui Tze Toh, Guan Huei See, Shaoqiang Zhang, Purakh Raj Verma
  • Patent number: 10002957
    Abstract: Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 19, 2018
    Assignee: Power Integrations, Inc.
    Inventor: Alexei Koudymov
  • Patent number: 9997417
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Tsun Liu
  • Patent number: 9985031
    Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9947595
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Tsun Liu
  • Patent number: 9941363
    Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun
  • Patent number: 9935186
    Abstract: A SOI lateral heterojunction Si-emitter SiGe-base bipolar transistor is provided that contains an intrinsic base region that includes a small band gap region (i.e., a silicon germanium alloy base of a first conductivity type) and a large band gap region (i.e., a silicon region of the first conductivity type) A silicon emitter of a second conductivity type that is opposite the first conductivity type is formed on the large-band gap side of the intrinsic base region and a silicon collector of the second conductivity type is formed on the small-band gap side of the intrinsic base region.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 9929269
    Abstract: Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Zhiqiang Wu, Jean-Pierre Colinge
  • Patent number: 9929059
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 27, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9899514
    Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rui Tze Toh, Guan Huei See, Shaoqiang Zhang, Purakh Raj Verma
  • Patent number: 9893193
    Abstract: A method of fabricating a thin-film transistor includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a gate electrode above the gate insulating layer; forming a cover layer on the gate electrode; forming a side wall insulating layer on a side wall portion of the gate electrode by heat treatment, after the forming of a cover layer; forming an interlayer insulating layer covering the gate electrode and the oxide semiconductor layer, after the forming of a side wall insulating layer; and forming, above the interlayer insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 13, 2018
    Assignee: JOLED INC.
    Inventors: Arinobu Kanegae, Emi Kobayashi, Yusuke Fukui
  • Patent number: 9875908
    Abstract: The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 23, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Lei Fang
  • Patent number: 9875972
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shou-Zen Chang, Chi-Ming Huang, Kai-Chiang Wu, Sen-Kuei Hsu, Hsin-Yu Pan, Han-Ping Pu, Albert Wan
  • Patent number: 9859295
    Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9847330
    Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, first and second gates, an opening, first and second dielectric layers. The substrate includes first and second semiconductor fins and a trench therebetween. The insulator is disposed in the trench. The first and second gates are respectively disposed on the first and second semiconductor fins. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first and second gates and includes a slit. The second dielectric layer is filled in the slit, wherein the opening has a first width in a direction along which the first and second gates extend, the slit has a second width in the direction, and a ratio of the first width to the second width is larger than 2.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9847329
    Abstract: A semiconductor device includes a first fin feature embedded within an isolation structure disposed over a semiconductor substrate, the first fin structure having a first sidewall and a second opposing sidewall and a top surface extending from the first sidewall to the second sidewall. The device also includes a second fin feature disposed over the isolation structure and having a third sidewall and a fourth sidewall. The third sidewall is aligned with the first sidewall of the first fin structure. The device also includes a gate dielectric layer disposed directly on the top surface of the first fin structure, the third sidewall and the fourth sidewall of the second fin feature and a gate electrode disposed over the gate dielectric.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yao Wen, Bo-Yu Lai
  • Patent number: 9812550
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 7, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 9799773
    Abstract: A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiromichi Godo, Satoshi Kobayashi, Masashi Tsubuku
  • Patent number: 9755069
    Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroki Fujii
  • Patent number: 9754935
    Abstract: A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Lavoie, Effendi Leobandung
  • Patent number: 9741788
    Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 22, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuo Takahashi, Takami Otsuki
  • Patent number: 9741855
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 22, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Patent number: 9735159
    Abstract: An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor performance.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: August 15, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Younsung Choi, Greg Charles Baldwin
  • Patent number: 9728616
    Abstract: The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate. Then, the conductive layer is patterned to form a gate and a dummy gate disposed at a first side of the gate and followed by forming a first spacer between the gate and the dummy gate and a second spacer at a second side of the gate opposite to the first side, wherein the first spacer includes an indentation. Subsequently, the dummy gate is removed.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 8, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang
  • Patent number: 9721806
    Abstract: The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 1, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Lei Fang
  • Patent number: 9704754
    Abstract: Semiconductor devices and methods of forming the same include laterally etching a dummy gate to recess the dummy gate underneath a spacer layer, such that the spacer layer overhangs the dummy gate. A sidewall of the dummy gate is nitridized. The dummy gate is etched away without removing the nitridized sidewall. A gate is formed within a boundary defined by the nitridized sidewall. A conductive contact to the gate is formed.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Patent number: 9698243
    Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9640635
    Abstract: A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 2, 2017
    Assignee: NXP USA, INC.
    Inventors: Zhihong Zhang, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9614041
    Abstract: A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially separated from each other, a first region of a second dopant type, having a pocket of the first dopant type, formed in the substrate between the first and second gate electrodes, the pocket being spaced apart from the first and second gate electrodes, a silicide block over the first region, a source region formed in the substrate on an opposing side of the first gate electrode from the first region and having the second dopant type, a drain region formed in the substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type, and a second pocket of the first dopant type formed in the drain region adjacent to the second gate electrode.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: April 4, 2017
    Assignee: NXP USA, Inc.
    Inventors: Zhihong Zhang, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9608218
    Abstract: An N-type thin film transistor includes an insulating substrate, a semiconductor carbon nanotube layer, an MgO layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is located on the insulating substrate. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode. The MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covers the MgO layer. The gate electrode is located on the functional dielectric layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 28, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Guan-Hong Li, Qun-Qing Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 9608054
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Patent number: 9601616
    Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu
  • Patent number: 9590072
    Abstract: The present invention provides a method of forming a semiconductor device including following steps. Firstly, a fin shaped structure is formed on a substrate, and a gate structure is formed to be across the fin shaped structure. Next, a dielectric layer is formed on the substrate, covering the gate structure, and a gate electrode of the gate structure is removed, to form a first gate trench. Then, a threshold voltage implantation process and a compensated threshold voltage implantation process are sequentially performed in the first gate trench, to implant compensated two dopants respectively. Following these, a work function layer and a conductive layer are formed to fill the first gate trench.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: March 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ling-Chun Chou
  • Patent number: 9525066
    Abstract: Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET (Qn) to cause both the well region and the low-concentration region to partially overlap each other, whereby an overlap region formed of an n-type semiconductor region having a higher resistance than that of the n-type low-concentration region is provided between the p-type well region and each of the n-type low-concentration regions. In this way, the overlap region can relieve an electric field concentration at the end of the n-type low-concentration region, thereby suppressing the occurrence of hot carriers without elongating an offset length of the LDD, which can promote the miniaturization of the MISFET (Qn), particularly, that operates at high voltage.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 20, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kiyotaka Miwa
  • Patent number: 9502412
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Yung-Tsun Liu
  • Patent number: 9496362
    Abstract: A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on source-drain areas between the sacrificial gates. A contact liner and contact material are deposited. The liner and the contact material are removed from above the sacrificial gates. Contact areas are blocked with one or more masking materials and etched. The masking material is removed. The contact material is partially recessed and a nitride liner deposited. An oxide layer is deposited and the sacrificial gate is removed. A metal gate is formed on the channel region and recessed. Insulator material and metal gate material are recessed and a cap is formed over the gate.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Ravikumar Ramachandran, Viraj Y. Sardesai
  • Patent number: 9484414
    Abstract: A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 1, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hirofumi Yamamoto, Toru Hiyoshi, Shinji Matsukawa
  • Patent number: 9478638
    Abstract: The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen