Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

Abstract: A model parameter test structure for a transistor includes: a substrate, having a first conductivity type, a plurality of isolation structures being provided in the substrate and the isolation structures being used to isolate different doped regions; a first test device, formed in the substrate and configured to obtain characteristic parameters of a source side of the transistor; and a second test device, formed in the substrate and configured to obtain characteristic parameters of a drain side of the transistor; wherein a structure of the first test device is different from a structure of the second test device.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Abstract: A semiconductor device with a small variation in transistor characteristics is provided. An oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode over the oxide semiconductor film are included; an opening is formed overlapping with a region between the source electrode and the drain electrode in the interlayer insulating film; the gate electrode is placed in the opening in the interlayer insulating film; and the source electrode and the drain electrode include a conductive film having compressive stress.

Abstract: A semiconductor device includes an active gate metal structure disposed over a substrate, the active gate metal structure having a first sidewall and a second sidewall opposite to each other. The semiconductor device includes a first source/drain region disposed adjacent the first sidewall of the active gate metal structure with a first lateral distance. The semiconductor device includes a second source/drain region disposed adjacent the second sidewall of the active gate metal structure with a second lateral distance, wherein the second lateral distance is substantially greater than the first lateral distance. The semiconductor device includes a resist protective oxide (RPO) comprising a first portion extending over a portion of a major surface of the substrate that is laterally located between the second sidewall and the second source/drain region, wherein the RPO has no portion extending over a top surface of the active gate metal structure.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: A device includes a substrate with upper/lower surfaces, including hydrogen containing region having hydrogen chemical concentration peaks in a depth direction. A carrier concentration distribution of the hydrogen containing region includes a first carrier concentration peak, a second carrier concentration peak closest to the first carrier concentration peak, a third carrier concentration peak arranged closer to the upper surface than the second carrier concentration peak, a first inter peak region arranged between the first and second carrier concentration peaks, a second inter peak region arranged between the second and third carrier concentration peaks, and an inter-peaks concentration peak arranged in the second inter peak region such that the concentration peak does not overlap the hydrogen chemical concentration peaks in the second and third carrier concentration peaks. A local minimum value of a carrier concentration in the first inter peak region is smaller than that of the second inter peak region.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

Abstract: Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Abstract: A method of forming a semiconductor structure including: forming a drift well in a substrate, in which the drift well includes first dopants having a first conductivity type; forming an isolation structure over the drift well; forming a well region in the drift well and spaced apart from the isolation structure, such that a top portion of the drift well is between the well region and the isolation structure; doping the top portion with second dopants having a second conductivity type different from the first conductivity type, such that a doping concentration of the second dopants in the top portion is lower than a doping concentration of the first dopants in the top portion after doping the top portion; and forming a gate structure extending from the isolation structure to the well region and covering the top portion of the drift well.

Abstract: Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune RF switch FET device performance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.

Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.

Abstract: The present invention relates to an improved apparatus and method for harmonizing both Sign Bit Hiding (SBH) and Residual Sign Prediction (RSP) techniques in video coding. In order to improve coding efficiency, a list of transform coefficients, to which RSP is to be applied is prepared in advance of selecting a coefficient to which SBH is applied. Thereby, the RSP list can be populated in such a manner that the highest coding efficiency may be expected. Subsequently, one or more coefficients for applying SBH are selected so as not to be included in the list.

Abstract: A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.

Abstract: A transistor and a method for forming the same are provided. The transistor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate includes a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a substrate, at least a portion of one or more of the fins providing one or more channels for one or more fin field-effect transistors. The method also includes forming a plurality of active gate structures over the fins, forming at least one single diffusion break trench between a first one of the active gate structures and a second one of the active gate structures, and forming at least one double diffusion break trench between a third one of the active gate structures and a fourth one of the active gate structures. The double diffusion break trench has a stepped height profile in the substrate, the stepped height profile comprising a first depth with a first width and a second depth less than the first depth with a second width greater than the first width.

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract: The disclosure discloses a display panel, a method for driving the same, and a display device, where a control electrode is arranged on the side of an active layer of a thin film transistor away from a gate electrode, and the thickness of a buffer layer between the control electrode and the active layer is controlled so that the buffer layer is thicker than a gate insulation layer between the gate electrode and the active layer, to adjust the distance between the control electrode and the active layer to be larger than the distance between the gate electrode and the active layer; and at least when a gate off voltage is applied to the gate electrode so that the thin film transistor is switched off, a first control voltage is applied to the control electrode to vary a voltage Vg of the thin film transistor.

Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.

Abstract: Some embodiments include a transistor having a gate, with the gate being over a semiconductor base. The gate has sidewalls. A channel region is under the gate. Spacers are along the sidewalk. The spacers each include a spacer structure and a void between the spacer structure and the gate. The spacer structures each include a vertical segment extending upwardly from a horizontal segment. The vertical segments join to the horizontal segments at corners. Source/drain regions are adjacent the channel region. The voids may be along the entirety of the vertical segments of the spacer structures, and may extend around the corners and to under the horizontal segments of the spacer structures. Additionally, or alternatively, bottoms of the voids may be adjacent fill material which includes silicon, nitrogen, boron and oxygen. Some embodiments include methods of forming transistors.

Abstract: High-voltage transistor devices with two-step field plate structures and methods of fabricating the transistor devices are provided. An example high voltage transistor device includes: a gate electrode disposed over a substrate between a source region and a drain region, a first film laterally extending from over the gate electrode to over a drift region laterally arranged between the gate electrode and the drain region, a second film laterally extending over a portion of the drift region adjacent to the drain region and away from the gate electrode, and a field plate laterally extending from over the first film to over the second film. A first thickness vertically from a top surface of the gate electrode to a bottom surface of the field plate is smaller than a second thickness vertically from a top surface of the portion of the drift region to the bottom surface of the field plate.

Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs), and disclosed are the associated devices. An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

Abstract: A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.

Abstract: Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (SPD) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the source region and the drain region of fin structure. In some implementations, the SPD layer is disposed over the fin structure, such that the dopant diffuses laterally and vertically into the source region and the drain region to form heavily doped source/drain features.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

Abstract: A pixel array substrate including a substrate, a first signal line, a second signal line, a third signal line, a first active element and a conductive pattern is provided. The first signal line and the second signal line are disposed on the substrate and intersect with each other. The third signal line is disposed on the substrate and overlapped with the second signal line. The extending direction of the third signal line is parallel to the extending direction of the second signal line. The first active element is electrically connected to the first signal line. The first active element includes a semiconductor pattern, a first gate and a second gate. The semiconductor pattern is located between the first gate and the second gate. The first gate is overlapped with the second gate and connected to the third signal line. The second gate is connected to the first gate via the conductive pattern.

Abstract: A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Abstract: The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.

Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.