Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 Patents (Class 257/410)
  • Patent number: 11417750
    Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11396698
    Abstract: Processing methods comprising exposing a substrate to a first reactive gas comprising a cyclopentadienyl nickel complex and a second reactive gas comprising a sub-saturative amount of oxygen to form a nickel oxide film with a carbon content in the range of about 2 to about 10 atomic percent are described.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 26, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jeffrey W. Anthis, Ghazal Saheli, Feng Q. Liu, David Thompson
  • Patent number: 11398384
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
  • Patent number: 11362089
    Abstract: Semiconductor structures and method for forming the same are provided. The method for manufacturing the semiconductor structure includes forming a first gate dielectric layer over a substrate and forming a first capping layer over the first gate dielectric layer. The method for manufacturing the semiconductor structure includes oxidizing the first capping layer to form a first capping oxide layer and forming a first work function metal layer over the first capping oxide layer. The method for manufacturing the semiconductor structure includes forming a first gate electrode layer over the first work function metal layer.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo, Cheng-Wei Lian
  • Patent number: 11355620
    Abstract: A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Che-Yu Lin, Hsueh-Chang Sung, Yee-Chia Yeo
  • Patent number: 11335796
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Jack T. Kavalieros
  • Patent number: 11329169
    Abstract: A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 10, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin-Hong Park, Jae-Woong Choi, Kwan-Ho Kim, Maksim Andreev
  • Patent number: 11309402
    Abstract: A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Yosuke Kita
  • Patent number: 11289583
    Abstract: A method of forming a semiconductor device includes providing a substrate; forming mandrel patterns over the substrate; forming sacrificial patterns in openings between the mandrel patterns; removing the mandrel patterns; forming a dielectric layer in openings between the sacrificial patterns; removing the sacrificial patterns, resulting in a plurality of trenches; and forming a gate stack in each of the plurality of trenches.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi-On Chui, Kai-Hsuan Lee, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11270994
    Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over the work function layer. The barrier layer is sandwiched between the metal layer and the work function layer. The barrier layer includes silicon or aluminum.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
  • Patent number: 11239258
    Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 1, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
  • Patent number: 11239337
    Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: February 1, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuya Yoshida
  • Patent number: 11227763
    Abstract: A method for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition in a reaction chamber is disclosed. The method may include: depositing a hafnium oxide film on the substrate utilizing a first sub-cycle of the cyclical deposition process and depositing a lanthanum oxide film utilizing a second sub-cycle of the cyclical deposition process.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 18, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Tatiana Ivanova, Perttu Sippola, Michael Eugene Givens
  • Patent number: 11201094
    Abstract: A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Wei-Hao Wu
  • Patent number: 11195938
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi-On Chui, Ziwei Fang
  • Patent number: 11189789
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 11164866
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin
  • Patent number: 11152264
    Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices. The method includes forming first, second, and third nanosheet stacks, removing sacrificial layers of the first, second, and third nanosheet stacks, and depositing an interfacial layer and a high-k layer within the first, second, and third nanosheet stacks. The method further includes depositing a first work function metal (WFM) layer within the first nanosheet stack having a first thickness, depositing a second WFM layer within the second nanosheet stack having a second thickness, wherein the second thickness is greater than the first thickness, depositing a third WFM layer within the third nanosheet stack having a third thickness, wherein the third thickness is greater than the second thickness, depositing a dipole material, and diffusing the dipole material into the IL to provide different gate threshold voltages for the plurality of FET devices.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Takashi Ando, Alexander Reznicek
  • Patent number: 11114565
    Abstract: Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 7, 2021
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroyuki Ota, Shinji Migita
  • Patent number: 11107830
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H Fabreguette, Richard J. Hill, Shyam Surthi
  • Patent number: 11107692
    Abstract: An etching method of etching a silicon nitride region with high selectivity is provided. In the etching method, a processing target object, having a silicon nitride region and a silicon-containing region having a composition different from the silicon nitride region, is accommodated in a processing vessel, and the silicon nitride region is selectively etched. In a first process, a deposit containing hydrofluorocarbon is formed on the silicon nitride region and the silicon-containing region by generating plasma of a processing gas containing a hydrofluorocarbon gas within the processing vessel. In a second process, the silicon nitride region is etched by radicals of the hydrofluorocarbon contained in the deposit. The first process and the second process are repeated alternately.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 31, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hikaru Watanabe, Ryosuke Ebihara
  • Patent number: 11094827
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Yanping Shen, Xiaoxiao Zhang, Shesh Mani Pandey, Hui Zang
  • Patent number: 10964530
    Abstract: A method of forming a blocking silicon oxide film on a target surface on which a silicon oxide film and a silicon nitride film are exposed, includes: placing a workpiece having the target surface on which the silicon oxide film and the silicon nitride film are exposed in a processing container under a depressurized atmosphere; forming a spacer polysilicon film to be a sacrificial film on the target surface on which the silicon oxide film and the silicon nitride film are exposed; and substituting the spacer polysilicon film with a substitution silicon oxide film by supplying thermal energy, oxygen radicals and hydrogen radicals onto the workpiece.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kyungseok Ko, Hiromi Shima, Eiji Kikama, Keisuke Suzuki, Shingo Hishiya
  • Patent number: 10944010
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 10936013
    Abstract: An apparatus is described. The apparatus includes a transparent display having pixels that appear transparent when in an off mode, and appear as one or more colors when in an on mode. The apparatus also includes a frame surrounding a perimeter of the transparent display. The frame includes non-transparent components that present images on the transparent display. The apparatus additionally includes a connected member that is connected with the transparent display. The connected member provides a contrast to the transparent display when the connected member is positioned opposite a viewing side of the transparent display.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Praveen Vishakantaiah, Zhiming J. Zhuang
  • Patent number: 10930777
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 23, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ignasi Cortes Mayol, Alban Zaka, Tom Herrmann, El Mehdi Bazizi
  • Patent number: 10923586
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 16, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
  • Patent number: 10916499
    Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Manish Chandhok
  • Patent number: 10903506
    Abstract: Provided is a separator for a fuel cell that can suppress a decrease in the power generation performance of the fuel cell by reducing the contact resistance of the separator. Specifically, provided is a separator for a fuel cell, the separator being adapted to be in contact with a MEGA (power generation portion) including a membrane electrode assembly of the fuel cell so as to separate the MEGA from a MEGA of an adjacent fuel cell, the separator including a metal substrate made of metal; and a tin oxide film covering a surface of the metal substrate on the side of the MEGA. The tin oxide film is made of tin oxide containing 0.2 to 10 atom % of antimony.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 26, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Satoshi Takata, Tomonari Kogure
  • Patent number: 10879392
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
  • Patent number: 10872965
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10868142
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 10861752
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 10833155
    Abstract: A vertical field effect transistor (VFET) having a bottom airgap spacer located beneath a gate structure and a top airgap spacer located above the gate structure is provided. The top airgap spacer reduces overlap capacitance between the gate structure and a top source/drain structure of the VFET, while the bottom airgap spacer reduces the overlap capacitance and a coupling capacitance that is present between the gate structure and a bottom source/drain structure of the VFET.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chun-Chen Yeh, Veeraraghavan S. Basker, Junli Wang, Alexander Reznicek
  • Patent number: 10833091
    Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 10, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-De Lin, Heng-Yuan Lee, Po-Chun Yeh, Chih-Yao Wang, Hsin-Yun Yang
  • Patent number: 10804367
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, I-Sheng Chen, Shao-Ming Yu, Tzu-Chiang Chen, Chih Chieh Yeh
  • Patent number: 10797156
    Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10797051
    Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonjae Kim, Cheol Kim, Yong-Hoon Son, Jin-Hyuk Yoo, Woojin Jung
  • Patent number: 10756194
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10749007
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ricky Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Patent number: 10741689
    Abstract: A semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming a first dielectric layer on the base substrate; forming a target gate structure in the first dielectric layer and on the base substrate, where a first groove is formed above the target gate structure and in the first dielectric layer; forming a second groove by etching the first dielectric layer on sidewalls of the first groove to expand an opening of the first groove; forming a protective layer in the second groove; and forming conductive plugs in the first dielectric layer on sides of the target gate structure and the protective layer. The protective layer has a dielectric constant greater than the first dielectric layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: August 11, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10720430
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Patent number: 10692773
    Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 10686049
    Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh
  • Patent number: 10672665
    Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu
  • Patent number: 10665720
    Abstract: The present invention provides a pixel structure, an array substrate, a liquid crystal display panel and a pixel structure manufacture method. The pixel structure includes a pixel electrode layer and a thin film transistor. The thin film transistor includes a gate, a source and a drain which are isolated with the gate and an organic semiconductor layer. The pixel structure further includes an Indium Tin Oxide layer and a metal layer, and the metal layer is located on a portion of the ITO layer. The source, the drain are formed on the ITO layer. A pattern formed by the organic semiconductor layer is electrically coupled to the ITO layer and the metal layer, and the pixel electrode layer is electrically coupled to the metal layer and the ITO layer.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 26, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Mian Zeng
  • Patent number: 10651286
    Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura, Richard S. Wise
  • Patent number: 10644125
    Abstract: A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
  • Patent number: 10593786
    Abstract: The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10573755
    Abstract: A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Kangguo Cheng, Nicolas Loubet, Ruilong Xie