Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 Patents (Class 257/410)
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Patent number: 12191412Abstract: Compositions, thin films, devices, and methods involving doped oxide semiconductor materials are described. Indium gallium doped zinc oxide (IGZO) with advantageous properties that may be useful as a transparent conductive oxide (TCO) is described. Methods of digital doping to create doped oxide semiconductor materials are described.Type: GrantFiled: October 15, 2020Date of Patent: January 7, 2025Assignee: Bowling Green State UniversityInventor: Farida Selim
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Patent number: 12040237Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.Type: GrantFiled: May 24, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
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Patent number: 12014979Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: GrantFiled: November 21, 2022Date of Patent: June 18, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11990522Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.Type: GrantFiled: December 9, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 11866453Abstract: Described are precursor compounds and methods for atomic layer deposition of films containing scandium(III) oxide or scandium(III) sulfide. Such films may be utilized as dielectric layers in semiconductor manufacturing processes, particular for depositing dielectric films and the use of such films in various electronic devices.Type: GrantFiled: October 7, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventor: Patricio E. Romero
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Patent number: 11798874Abstract: A semiconductor device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip, an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board, and an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element. The electrical redistribution layer includes a ground line connected to a ground potential and a signal line configured to carry an electrical signal having a wavelength.Type: GrantFiled: November 29, 2021Date of Patent: October 24, 2023Assignee: Infineon Technologies AGInventors: Walter Hartner, Francesca Arcioni, Tuncay Erdoel, Vincenzo Fiore, Helmut Kollmann, Arif Roni, Emanuele Stavagna, Christoph Wagner
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Patent number: 11784239Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.Type: GrantFiled: December 14, 2016Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Sean T. Ma, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Willy Rachmady, Gilbert W. Dewey, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
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Patent number: 11728393Abstract: An object is to provide a technology that can enhance electrical characteristics of a semiconductor device. A semiconductor device is a semiconductor device provided with a semiconductor element. The semiconductor device includes: an n-type single-crystal gallium oxide layer including a first main surface; an electrode disposed on the first main surface of the n-type single-crystal gallium oxide layer or above the first main surface, the electrode being an electrode of the semiconductor element; a p-type oxide semiconductor layer disposed between the n-type single-crystal gallium oxide layer and the electrode; and an amorphous gallium oxide layer disposed between the n-type single-crystal gallium oxide layer and the p-type oxide semiconductor layer.Type: GrantFiled: March 13, 2019Date of Patent: August 15, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yohei Yuda, Tatsuro Watahiki
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Patent number: 11721735Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.Type: GrantFiled: January 20, 2022Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Gilbert Dewey, Aaron Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani, Willy Rachmady, Rishabh Mehandru, Nazila Haratipour, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Shriram Shivaraman
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Patent number: 11682735Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.Type: GrantFiled: April 15, 2021Date of Patent: June 20, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Hun Lee, Dong Woo Kim, Dong Chan Suh, Sun Jung Kim
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Patent number: 11605649Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.Type: GrantFiled: May 3, 2021Date of Patent: March 14, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Mark D. Levy, Siva P. Adusumilli, Alvin J. Joseph, Ramsey Hazbun
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Patent number: 11569131Abstract: A semiconductor device and its fabrication method are provided in the present disclosure. The method includes providing a substrate; forming a plurality of fins spaced apart on the substrate; forming a dummy gate structure across the plurality of fins and on the substrate; forming a first sidewall spacer on a sidewall of the dummy gate structure; forming an interlayer dielectric layer on the substrate and the fins, and on a portion of a sidewall of the first sidewall spacer, where a top of the interlayer dielectric layer is lower than a top of the first sidewall spacer; and forming a second sidewall spacer on the interlayer dielectric layer and on a sidewall of the first sidewall spacer.Type: GrantFiled: April 24, 2020Date of Patent: January 31, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Fei Zhou
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Patent number: 11538905Abstract: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires.Type: GrantFiled: September 30, 2016Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy, Nabil G. Mistkawi, Karthik Jambunathan, Tahir Ghani
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Patent number: 11508656Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: GrantFiled: June 28, 2021Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11508823Abstract: A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner.Type: GrantFiled: December 23, 2020Date of Patent: November 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Ekmini Anuja De Silva, Jing Guo, Hao Tang, Cheng Chi
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Patent number: 11495664Abstract: A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.Type: GrantFiled: June 29, 2020Date of Patent: November 8, 2022Assignee: Adamantite Technologies LLCInventor: Eric David Bauswell
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Patent number: 11430656Abstract: Methods are provided herein for deposition of oxide films. Oxide films may be deposited, including selective deposition of oxide thin films on a first surface of a substrate relative to a second, different surface of the same substrate. For example, an oxide thin film such as an insulating metal oxide thin film may be selectively deposited on a first surface of a substrate relative to a second, different surface of the same substrate. The second, different surface may be an organic passivation layer.Type: GrantFiled: November 29, 2016Date of Patent: August 30, 2022Assignee: ASM IP HOLDING B.V.Inventors: Suvi P. Haukka, Elina Färm, Raija H. Matero, Eva E. Tois, Hidemi Suemori, Antti Juhani Niskanen, Sung-Hoon Jung, Petri Räisänen
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Patent number: 11417750Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.Type: GrantFiled: December 15, 2020Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11396698Abstract: Processing methods comprising exposing a substrate to a first reactive gas comprising a cyclopentadienyl nickel complex and a second reactive gas comprising a sub-saturative amount of oxygen to form a nickel oxide film with a carbon content in the range of about 2 to about 10 atomic percent are described.Type: GrantFiled: January 5, 2018Date of Patent: July 26, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Jeffrey W. Anthis, Ghazal Saheli, Feng Q. Liu, David Thompson
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Patent number: 11398384Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.Type: GrantFiled: February 11, 2020Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
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Patent number: 11362089Abstract: Semiconductor structures and method for forming the same are provided. The method for manufacturing the semiconductor structure includes forming a first gate dielectric layer over a substrate and forming a first capping layer over the first gate dielectric layer. The method for manufacturing the semiconductor structure includes oxidizing the first capping layer to form a first capping oxide layer and forming a first work function metal layer over the first capping oxide layer. The method for manufacturing the semiconductor structure includes forming a first gate electrode layer over the first work function metal layer.Type: GrantFiled: December 30, 2019Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo, Cheng-Wei Lian
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Patent number: 11355620Abstract: A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.Type: GrantFiled: July 1, 2019Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Wei Lee, Che-Yu Lin, Hsueh-Chang Sung, Yee-Chia Yeo
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Patent number: 11335796Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.Type: GrantFiled: December 30, 2017Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Jack T. Kavalieros
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Patent number: 11329169Abstract: A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip.Type: GrantFiled: October 15, 2020Date of Patent: May 10, 2022Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Jin-Hong Park, Jae-Woong Choi, Kwan-Ho Kim, Maksim Andreev
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Patent number: 11309402Abstract: A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.Type: GrantFiled: March 5, 2020Date of Patent: April 19, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Fumitaka Amano, Yosuke Kita
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Patent number: 11289583Abstract: A method of forming a semiconductor device includes providing a substrate; forming mandrel patterns over the substrate; forming sacrificial patterns in openings between the mandrel patterns; removing the mandrel patterns; forming a dielectric layer in openings between the sacrificial patterns; removing the sacrificial patterns, resulting in a plurality of trenches; and forming a gate stack in each of the plurality of trenches.Type: GrantFiled: June 26, 2019Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sai-Hooi Yeong, Chi-On Chui, Kai-Hsuan Lee, Kuan-Lun Cheng, Chih-Hao Wang
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Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor
Patent number: 11270994Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over the work function layer. The barrier layer is sandwiched between the metal layer and the work function layer. The barrier layer includes silicon or aluminum.Type: GrantFiled: April 20, 2018Date of Patent: March 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu -
Patent number: 11239337Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.Type: GrantFiled: December 3, 2020Date of Patent: February 1, 2022Assignee: Renesas Electronics CorporationInventor: Tetsuya Yoshida
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Patent number: 11239258Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.Type: GrantFiled: July 11, 2017Date of Patent: February 1, 2022Assignee: Applied Materials, Inc.Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
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Patent number: 11227763Abstract: A method for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition in a reaction chamber is disclosed. The method may include: depositing a hafnium oxide film on the substrate utilizing a first sub-cycle of the cyclical deposition process and depositing a lanthanum oxide film utilizing a second sub-cycle of the cyclical deposition process.Type: GrantFiled: February 14, 2020Date of Patent: January 18, 2022Assignee: ASM IP Holding B.V.Inventors: Tatiana Ivanova, Perttu Sippola, Michael Eugene Givens
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Patent number: 11201094Abstract: A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.Type: GrantFiled: April 1, 2019Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lung-Kun Chu, Mao-Lin Huang, Wei-Hao Wu
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Patent number: 11195938Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.Type: GrantFiled: July 30, 2019Date of Patent: December 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi-On Chui, Ziwei Fang
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Patent number: 11189789Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.Type: GrantFiled: September 4, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Tai Tseng, Shih-Chang Liu
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Patent number: 11164866Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure.Type: GrantFiled: February 20, 2019Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin
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Patent number: 11152264Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices. The method includes forming first, second, and third nanosheet stacks, removing sacrificial layers of the first, second, and third nanosheet stacks, and depositing an interfacial layer and a high-k layer within the first, second, and third nanosheet stacks. The method further includes depositing a first work function metal (WFM) layer within the first nanosheet stack having a first thickness, depositing a second WFM layer within the second nanosheet stack having a second thickness, wherein the second thickness is greater than the first thickness, depositing a third WFM layer within the third nanosheet stack having a third thickness, wherein the third thickness is greater than the second thickness, depositing a dipole material, and diffusing the dipole material into the IL to provide different gate threshold voltages for the plurality of FET devices.Type: GrantFiled: January 8, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jingyun Zhang, Takashi Ando, Alexander Reznicek
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Patent number: 11114565Abstract: Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.Type: GrantFiled: September 11, 2018Date of Patent: September 7, 2021Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Hiroyuki Ota, Shinji Migita
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Patent number: 11107830Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.Type: GrantFiled: August 22, 2019Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Byeung Chul Kim, Francois H Fabreguette, Richard J. Hill, Shyam Surthi
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Patent number: 11107692Abstract: An etching method of etching a silicon nitride region with high selectivity is provided. In the etching method, a processing target object, having a silicon nitride region and a silicon-containing region having a composition different from the silicon nitride region, is accommodated in a processing vessel, and the silicon nitride region is selectively etched. In a first process, a deposit containing hydrofluorocarbon is formed on the silicon nitride region and the silicon-containing region by generating plasma of a processing gas containing a hydrofluorocarbon gas within the processing vessel. In a second process, the silicon nitride region is etched by radicals of the hydrofluorocarbon contained in the deposit. The first process and the second process are repeated alternately.Type: GrantFiled: May 2, 2017Date of Patent: August 31, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Hikaru Watanabe, Ryosuke Ebihara
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Patent number: 11094827Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.Type: GrantFiled: June 6, 2019Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Yanping Shen, Xiaoxiao Zhang, Shesh Mani Pandey, Hui Zang
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Patent number: 10964530Abstract: A method of forming a blocking silicon oxide film on a target surface on which a silicon oxide film and a silicon nitride film are exposed, includes: placing a workpiece having the target surface on which the silicon oxide film and the silicon nitride film are exposed in a processing container under a depressurized atmosphere; forming a spacer polysilicon film to be a sacrificial film on the target surface on which the silicon oxide film and the silicon nitride film are exposed; and substituting the spacer polysilicon film with a substitution silicon oxide film by supplying thermal energy, oxygen radicals and hydrogen radicals onto the workpiece.Type: GrantFiled: October 29, 2018Date of Patent: March 30, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Kyungseok Ko, Hiromi Shima, Eiji Kikama, Keisuke Suzuki, Shingo Hishiya
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Patent number: 10944010Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.Type: GrantFiled: December 19, 2019Date of Patent: March 9, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Patent number: 10936013Abstract: An apparatus is described. The apparatus includes a transparent display having pixels that appear transparent when in an off mode, and appear as one or more colors when in an on mode. The apparatus also includes a frame surrounding a perimeter of the transparent display. The frame includes non-transparent components that present images on the transparent display. The apparatus additionally includes a connected member that is connected with the transparent display. The connected member provides a contrast to the transparent display when the connected member is positioned opposite a viewing side of the transparent display.Type: GrantFiled: May 30, 2019Date of Patent: March 2, 2021Assignee: INTEL CORPORATIONInventors: Praveen Vishakantaiah, Zhiming J. Zhuang
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Patent number: 10930777Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.Type: GrantFiled: November 21, 2017Date of Patent: February 23, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Ignasi Cortes Mayol, Alban Zaka, Tom Herrmann, El Mehdi Bazizi
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Patent number: 10923586Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.Type: GrantFiled: July 24, 2019Date of Patent: February 16, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Patent number: 10916499Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers.Type: GrantFiled: September 30, 2016Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Kevin Lin, Manish Chandhok
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Patent number: 10903506Abstract: Provided is a separator for a fuel cell that can suppress a decrease in the power generation performance of the fuel cell by reducing the contact resistance of the separator. Specifically, provided is a separator for a fuel cell, the separator being adapted to be in contact with a MEGA (power generation portion) including a membrane electrode assembly of the fuel cell so as to separate the MEGA from a MEGA of an adjacent fuel cell, the separator including a metal substrate made of metal; and a tin oxide film covering a surface of the metal substrate on the side of the MEGA. The tin oxide film is made of tin oxide containing 0.2 to 10 atom % of antimony.Type: GrantFiled: May 16, 2018Date of Patent: January 26, 2021Assignee: Toyota Jidosha Kabushiki KaishaInventors: Satoshi Takata, Tomonari Kogure
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Patent number: 10879392Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: June 25, 2019Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Patent number: 10872965Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.Type: GrantFiled: June 29, 2020Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
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Patent number: 10868142Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.Type: GrantFiled: January 11, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
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Patent number: 10861752Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.Type: GrantFiled: October 2, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu