Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 Patents (Class 257/410)
  • Patent number: 10964530
    Abstract: A method of forming a blocking silicon oxide film on a target surface on which a silicon oxide film and a silicon nitride film are exposed, includes: placing a workpiece having the target surface on which the silicon oxide film and the silicon nitride film are exposed in a processing container under a depressurized atmosphere; forming a spacer polysilicon film to be a sacrificial film on the target surface on which the silicon oxide film and the silicon nitride film are exposed; and substituting the spacer polysilicon film with a substitution silicon oxide film by supplying thermal energy, oxygen radicals and hydrogen radicals onto the workpiece.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kyungseok Ko, Hiromi Shima, Eiji Kikama, Keisuke Suzuki, Shingo Hishiya
  • Patent number: 10944010
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 10936013
    Abstract: An apparatus is described. The apparatus includes a transparent display having pixels that appear transparent when in an off mode, and appear as one or more colors when in an on mode. The apparatus also includes a frame surrounding a perimeter of the transparent display. The frame includes non-transparent components that present images on the transparent display. The apparatus additionally includes a connected member that is connected with the transparent display. The connected member provides a contrast to the transparent display when the connected member is positioned opposite a viewing side of the transparent display.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Praveen Vishakantaiah, Zhiming J. Zhuang
  • Patent number: 10930777
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 23, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ignasi Cortes Mayol, Alban Zaka, Tom Herrmann, El Mehdi Bazizi
  • Patent number: 10923586
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 16, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
  • Patent number: 10916499
    Abstract: Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Manish Chandhok
  • Patent number: 10903506
    Abstract: Provided is a separator for a fuel cell that can suppress a decrease in the power generation performance of the fuel cell by reducing the contact resistance of the separator. Specifically, provided is a separator for a fuel cell, the separator being adapted to be in contact with a MEGA (power generation portion) including a membrane electrode assembly of the fuel cell so as to separate the MEGA from a MEGA of an adjacent fuel cell, the separator including a metal substrate made of metal; and a tin oxide film covering a surface of the metal substrate on the side of the MEGA. The tin oxide film is made of tin oxide containing 0.2 to 10 atom % of antimony.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 26, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Satoshi Takata, Tomonari Kogure
  • Patent number: 10879392
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
  • Patent number: 10872965
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10868142
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 10861752
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 10833091
    Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 10, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-De Lin, Heng-Yuan Lee, Po-Chun Yeh, Chih-Yao Wang, Hsin-Yun Yang
  • Patent number: 10833155
    Abstract: A vertical field effect transistor (VFET) having a bottom airgap spacer located beneath a gate structure and a top airgap spacer located above the gate structure is provided. The top airgap spacer reduces overlap capacitance between the gate structure and a top source/drain structure of the VFET, while the bottom airgap spacer reduces the overlap capacitance and a coupling capacitance that is present between the gate structure and a bottom source/drain structure of the VFET.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chun-Chen Yeh, Veeraraghavan S. Basker, Junli Wang, Alexander Reznicek
  • Patent number: 10804367
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, I-Sheng Chen, Shao-Ming Yu, Tzu-Chiang Chen, Chih Chieh Yeh
  • Patent number: 10797156
    Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10797051
    Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonjae Kim, Cheol Kim, Yong-Hoon Son, Jin-Hyuk Yoo, Woojin Jung
  • Patent number: 10756194
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10749007
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ricky Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Patent number: 10741689
    Abstract: A semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming a first dielectric layer on the base substrate; forming a target gate structure in the first dielectric layer and on the base substrate, where a first groove is formed above the target gate structure and in the first dielectric layer; forming a second groove by etching the first dielectric layer on sidewalls of the first groove to expand an opening of the first groove; forming a protective layer in the second groove; and forming conductive plugs in the first dielectric layer on sides of the target gate structure and the protective layer. The protective layer has a dielectric constant greater than the first dielectric layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: August 11, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10720430
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Patent number: 10692773
    Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 10686049
    Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh
  • Patent number: 10672665
    Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin, Yi-Hsun Chiu
  • Patent number: 10665720
    Abstract: The present invention provides a pixel structure, an array substrate, a liquid crystal display panel and a pixel structure manufacture method. The pixel structure includes a pixel electrode layer and a thin film transistor. The thin film transistor includes a gate, a source and a drain which are isolated with the gate and an organic semiconductor layer. The pixel structure further includes an Indium Tin Oxide layer and a metal layer, and the metal layer is located on a portion of the ITO layer. The source, the drain are formed on the ITO layer. A pattern formed by the organic semiconductor layer is electrically coupled to the ITO layer and the metal layer, and the pixel electrode layer is electrically coupled to the metal layer and the ITO layer.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 26, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Mian Zeng
  • Patent number: 10651286
    Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura, Richard S. Wise
  • Patent number: 10644125
    Abstract: A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
  • Patent number: 10593786
    Abstract: The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10573755
    Abstract: A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Kangguo Cheng, Nicolas Loubet, Ruilong Xie
  • Patent number: 10566280
    Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Takeshi Ishizaki, Hiroshi Itokawa, Daisuke Ikeno, Kei Watanabe, Atsuko Sakata
  • Patent number: 10566188
    Abstract: Embodiments of the present disclosure generally relate to a film treatment process. In one embodiment, a transition metal oxide layer including a dopant is deposited on a substrate. After the doped transition metal oxide layer is deposited, a high pressure annealing process is performed on the doped transition metal oxide layer to densify the doped transition metal oxide without outgassing of the dopant. The high pressure annealing process is performed in an ambient environment including the dopant and at a pressure greater than 1 bar.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 18, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Maximillian Clemons, Michel Ranjit Frei, Mahendra Pakala, Mehul B. Naik, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 10535774
    Abstract: A fin field effect transistor (finFET) includes a semiconductor substrate including at least one fin feature, a diffusion region formed on the semiconductor substrate and extending through the diffusion region, and a gate formed on the diffusion region and the at least one fin feature. The gate includes a split gate structure including a first gate region, a second gate region, a gap separating the first gate region and the second gate region, and a contact region electrically connecting the first gate region and the second gate region. A plurality of source/drain regions are formed in the diffusion region. The plurality of source/drain regions includes a source drain region in the gap between the first gate region and the second gate region. A plurality of pocket dopant regions are formed in the diffusion region. The plurality of pocket dopant regions includes at least one pocket dopant region in the gap between the first gate region and the second gate region.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Marvell International Ltd.
    Inventors: Hui Wang, Runzi Chang
  • Patent number: 10522344
    Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 10490645
    Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yoshikazu Moriwaki
  • Patent number: 10468494
    Abstract: A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Mou Lin, Chin-Chia Kuo, Ming-Hua Tsai, Su-Hua Tsai, Pai-Tsang Liu, Chiao-Yu Li, Chun-Ning Wu, Wei-Hsuan Chang
  • Patent number: 10461169
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ruei Yeh, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 10461158
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Patent number: 10453756
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mirco Cantoro, Maria Toledano Luque, Yeoncheol Heo, Dong Il Bae
  • Patent number: 10424504
    Abstract: A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N2) and ammonia (NH3) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200. Watts to about 4500. Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 10411106
    Abstract: A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method includes forming a gate above the substrate, forming a source contact above the source region and a drain contact above the drain region, and forming air spacers within a dielectric between the gate and each of the source contact and the drain contact. Metal caps are formed on the source contact and the drain contact, and a gate cap is formed between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Peng Xu, Chen Zhang
  • Patent number: 10403660
    Abstract: An image sensor and a method of manufacturing the same are disclosed. The image sensor includes a photodiode disposed in a substrate, and transistors disposed on the substrate and electrically connected with the photodiode. A gate insulating layer of a source follower transistor among the transistors includes fluorine so as to remove defects such as dangling bonds.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 3, 2019
    Assignee: DB HITEK CO., LTD.
    Inventor: Man Lyun Ha
  • Patent number: 10403816
    Abstract: Subject matter herein disclosed relates to a method for the manufacture of a switching device comprising a silicon-containing correlated electron material. In embodiments, processes are described for forming the silicon-containing correlated electron material. These processes may use comparatively lower temperatures as compared to those used for forming a correlated electron material comprising a transition metal oxide.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 3, 2019
    Assignee: Arm Limited
    Inventors: Kimberly Gay Reid, Lucian Shifren
  • Patent number: 10396172
    Abstract: A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method includes forming a gate above the substrate, forming a source contact above the source region and a drain contact above the drain region, and forming air spacers within a dielectric between the gate and each of the source contact and the drain contact. Metal caps are formed on the source contact and the drain contact, and a gate cap is formed between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Peng Xu, Chen Zhang
  • Patent number: 10367078
    Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yuan Chang, Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
  • Patent number: 10361290
    Abstract: Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Yukinori Shima
  • Patent number: 10347763
    Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Soo Kim, Dong Hyun Roh, Koung Min Ryu, Sang Jin Hyun
  • Patent number: 10304826
    Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
  • Patent number: 10290538
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
  • Patent number: 10269900
    Abstract: Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide includes a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material that includes the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds. An interface between a dummy gate and a gate dielectric layer of a gate-last transistor structure may be similarly formed.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Liao, Chun-Heng Chen, Sheng-Po Wu, Ming-Feng Hsieh, Hongfa Luan
  • Patent number: 10256161
    Abstract: A method for forming a semiconductor device includes forming a first channel region and a second channel region on a substrate, depositing a dielectric material layer on the first channel region and the second channel region, and depositing a barrier layer on the dielectric material layer on the first channel region and the second channel region. A metal layer is deposited on the barrier layer on the first channel region and the second channel region. A portion of the metal layer and the barrier layer on the first channel region and a portion of the metal layer on the second channel region are removed to expose the barrier layer on the second channel region. A layer of workfunction material is deposited on an exposed portion of the dielectric material layer on the first channel region and over the barrier layer on the second channel region.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Muthumanickam Sankarapandian, Koji Watanabe
  • Patent number: 10256403
    Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: April 9, 2019
    Assignee: IMEC
    Inventors: Christoph Adelmann, Malgorzata Jurczak