Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride) Patents (Class 257/411)
  • Patent number: 10700073
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
  • Patent number: 10680108
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiOx (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 9, 2020
    Assignee: IMEC vzw
    Inventor: Hiroaki Arimura
  • Patent number: 10665601
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10642077
    Abstract: A MOSCAP phase adjuster includes two conductive regions with a thin insulating region therebetween, where charge is accumulated or depleted. In conventional MOSCAP modulators, the conductive and insulating regions are superposed layers, extending horizontally parallel to the substrate, which limits waveguide design and mode confinement, resulting in reduced phase shift performance. An improved MOSCAP phase adjuster and method of fabricating a MOSCAP phase adjuster includes depositing the material for the second conductive region beside and over top of the first conductive region after oxidation, and selectively etching the material to form the second conductive region.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Lim Eu-Jin Andy, Yangjin Ma, Alexandre Horth, Yang Liu
  • Patent number: 10629684
    Abstract: Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10566430
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10566457
    Abstract: Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; an oxide semiconductor layer that is used as a channel layer; and a gate insulator film that is arranged between the gate electrode and the channel layer. The oxide semiconductor layer is configured of at least one metal element that is selected from the group consisting of In, Ga, Zn and Sn (excluding the cases where the oxide semiconductor layer is constituted of metal elements Sn, and at least one of In and Zn). The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: February 18, 2020
    Assignee: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Toshihiro Kugimiya, Hiroaki Tao, Kenta Hirose
  • Patent number: 10553691
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10529817
    Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Su-young Bae, Dong-soo Lee, Jong-han Lee, Hyung-suk Jung, Sang-jin Hyun
  • Patent number: 10522633
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
  • Patent number: 10504998
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
  • Patent number: 10505017
    Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Blandine Duriez, Mark van Dal
  • Patent number: 10483269
    Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric layer having a first thickness on the semiconductor substrate, a first opening having a first width in the first dielectric layer, a second dielectric layer having a second thickness disposed in a middle region of the first opening, and a third dielectric layer having a first portion and a second portion disposed on opposite sides of second dielectric layer. The first portion and the second portion have a second width smaller than the first width, and the third dielectric layer has a third thickness smaller than the first thickness and the second thickness.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 19, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Peng Huang, Jun Li, Honggang Dai, Guanguan Gu
  • Patent number: 10453861
    Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 22, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10453862
    Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 22, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10431745
    Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 1, 2019
    Assignee: BASF SE
    Inventors: Mathias Duggeli, Mahmoud Zaher Eteish, Pascal Hayoz, Olivier Aebischer, Marta Fonrodona Turon, Margherita Fontana, Marian Lanz, Mathieu G. R. Turbiez, Beat Schmidhalter, Jean-Charles Flores
  • Patent number: 10418457
    Abstract: The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 17, 2019
    Assignee: IQE plc
    Inventors: Rytis Dargis, Richard Hammond, Andrew Clark, Rodney Pelzel
  • Patent number: 10367071
    Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 30, 2019
    Assignee: NXP USA, INC.
    Inventor: Rama I. Hegde
  • Patent number: 10340285
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 10304677
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 10290723
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10256335
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 9, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Patent number: 10224484
    Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 5, 2019
    Assignee: BASF SE
    Inventors: Mathias Duggeli, Mahmoud Zaher Eteish, Pascal Hayoz, Olivier Frederic Aebischer, Marta Fonrodona Turon, Margherita Fontana, Marian Lanz, Mathieu G. R. Turbiez, Beat Schmidhalter, Jean-Charles Flores
  • Patent number: 10211302
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10192972
    Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 29, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
  • Patent number: 10186594
    Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: January 22, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
  • Patent number: 10177042
    Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Keun Chung, Hu-Yong Lee, Taek-Soo Jeon, Sang-Jin Hyun
  • Patent number: 10164070
    Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Patent number: 10109710
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Patent number: 10103186
    Abstract: A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Katsunori Hirota
  • Patent number: 10103254
    Abstract: Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 16, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Michael Joseph McPartlin
  • Patent number: 10090306
    Abstract: A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 2, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10043883
    Abstract: A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 7, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima, Tatsuo Shimizu
  • Patent number: 10043672
    Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 7, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Daniel Peter, Samantha Tan, Reza Arghavani, Yang Pan
  • Patent number: 10043881
    Abstract: While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Yamamoto
  • Patent number: 10026828
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 17, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10014395
    Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Krishna Bhuwalka
  • Patent number: 10002944
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 19, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hao Deng
  • Patent number: 9991278
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 9978601
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yen Tsai, Hsin-Yi Lee, Chung-Chiang Wu, Da-Yuan Lee, Weng Chang, Ming-Hsing Tsai
  • Patent number: 9966474
    Abstract: Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 8, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9960053
    Abstract: A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack at least partially over a fin extending from a substrate. In various embodiments, a barrier metal layer is deposited over the gate stack. By way of example, a thermal fluorine treatment is performed, where the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and where the fluorinated layer includes a plurality of fluorine atoms. In some embodiments, after forming the fluorinated layer, an anneal is performed to drive at least some of the plurality of fluorine atoms into the gate stack (e.g., into the interfacial layer and the high-K dielectric layer), thereby conformally doping the gate stack with the at least some of the plurality of fluorine atoms.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Xiong-Fei Yu, Chia-Wei Hsu
  • Patent number: 9947147
    Abstract: A novel vehicle electronic logging authorization and handover system is configured to provide commercial vehicle driver log handover requests and authorizations to improve and preserve robustness and non-overlapping uniqueness of electronically-generated commercial vehicle driver log data among a plurality of drivers who time-share a vehicle. In one embodiment, the novel vehicle electronic logging authorization and handover system includes a vehicle OBD device, a vehicle ELD, a remote ELD log handover authorization application executed on a first driver's portable electronic device, a remote ELD log handover request application executed on a second driver's portable electronic device, and a commercial fleet operation vehicle electronic logging database and management system. The drivers are able to remotely request or authorize ELD log handovers to other drivers, even if they are not inside or near the time-shared vehicle at the time of ELD log handover request or authorization.
    Type: Grant
    Filed: March 4, 2017
    Date of Patent: April 17, 2018
    Assignee: Truelite Trace, Inc.
    Inventor: Sung Bok Kwak
  • Patent number: 9923086
    Abstract: A method, and the resulting structure, of making a CMOS device from carbon nanotube substrate, where a carbide contact is formed in a source drain region. The carbide is formed prior to the gate structure by reacting a glassy carbon and a metal.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Shu-Jen Han
  • Patent number: 9905459
    Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9893288
    Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 13, 2018
    Assignee: BASF SE
    Inventors: Mathias Duggeli, Mahmoud Zaher Eteish, Pascal Hayoz, Olivier Aebischer, Marta Fonrodona Turon, Margherita Fontana, Marian Lanz, Mathieu G. R. Turbiez, Beat Schmidhalter, Jean-Charles Flores
  • Patent number: 9859169
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 9859392
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
  • Patent number: 9818847
    Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Robert S. Chau, Marko Radosavljevic, Han Wui Then, Scott B. Clendenning, Ravi Pillarisetty
  • Patent number: 9806075
    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Oh-seong Kwon, Hyeok-jun Son, Sang-jin Hyun, Hoon-joo Na