Composite Or Layered Gate Insulator (e.g., Mixture Such As Silicon Oxynitride) Patents (Class 257/411)
  • Patent number: 10304677
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 10290723
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10256335
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 9, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Patent number: 10224484
    Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 5, 2019
    Assignee: BASF SE
    Inventors: Mathias Duggeli, Mahmoud Zaher Eteish, Pascal Hayoz, Olivier Frederic Aebischer, Marta Fonrodona Turon, Margherita Fontana, Marian Lanz, Mathieu G. R. Turbiez, Beat Schmidhalter, Jean-Charles Flores
  • Patent number: 10211302
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10192972
    Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 29, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
  • Patent number: 10186594
    Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: January 22, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
  • Patent number: 10177042
    Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Keun Chung, Hu-Yong Lee, Taek-Soo Jeon, Sang-Jin Hyun
  • Patent number: 10164070
    Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Patent number: 10109710
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Patent number: 10103186
    Abstract: A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Katsunori Hirota
  • Patent number: 10103254
    Abstract: Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 16, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Michael Joseph McPartlin
  • Patent number: 10090306
    Abstract: A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 2, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10043883
    Abstract: A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 7, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima, Tatsuo Shimizu
  • Patent number: 10043672
    Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 7, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Daniel Peter, Samantha Tan, Reza Arghavani, Yang Pan
  • Patent number: 10043881
    Abstract: While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Yamamoto
  • Patent number: 10026828
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 17, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10014395
    Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Krishna Bhuwalka
  • Patent number: 10002944
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 19, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hao Deng
  • Patent number: 9991278
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 9978601
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yen Tsai, Hsin-Yi Lee, Chung-Chiang Wu, Da-Yuan Lee, Weng Chang, Ming-Hsing Tsai
  • Patent number: 9966474
    Abstract: Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 8, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9960053
    Abstract: A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack at least partially over a fin extending from a substrate. In various embodiments, a barrier metal layer is deposited over the gate stack. By way of example, a thermal fluorine treatment is performed, where the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and where the fluorinated layer includes a plurality of fluorine atoms. In some embodiments, after forming the fluorinated layer, an anneal is performed to drive at least some of the plurality of fluorine atoms into the gate stack (e.g., into the interfacial layer and the high-K dielectric layer), thereby conformally doping the gate stack with the at least some of the plurality of fluorine atoms.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Xiong-Fei Yu, Chia-Wei Hsu
  • Patent number: 9947147
    Abstract: A novel vehicle electronic logging authorization and handover system is configured to provide commercial vehicle driver log handover requests and authorizations to improve and preserve robustness and non-overlapping uniqueness of electronically-generated commercial vehicle driver log data among a plurality of drivers who time-share a vehicle. In one embodiment, the novel vehicle electronic logging authorization and handover system includes a vehicle OBD device, a vehicle ELD, a remote ELD log handover authorization application executed on a first driver's portable electronic device, a remote ELD log handover request application executed on a second driver's portable electronic device, and a commercial fleet operation vehicle electronic logging database and management system. The drivers are able to remotely request or authorize ELD log handovers to other drivers, even if they are not inside or near the time-shared vehicle at the time of ELD log handover request or authorization.
    Type: Grant
    Filed: March 4, 2017
    Date of Patent: April 17, 2018
    Assignee: Truelite Trace, Inc.
    Inventor: Sung Bok Kwak
  • Patent number: 9923086
    Abstract: A method, and the resulting structure, of making a CMOS device from carbon nanotube substrate, where a carbide contact is formed in a source drain region. The carbide is formed prior to the gate structure by reacting a glassy carbon and a metal.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Shu-Jen Han
  • Patent number: 9905459
    Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9893288
    Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 13, 2018
    Assignee: BASF SE
    Inventors: Mathias Duggeli, Mahmoud Zaher Eteish, Pascal Hayoz, Olivier Aebischer, Marta Fonrodona Turon, Margherita Fontana, Marian Lanz, Mathieu G. R. Turbiez, Beat Schmidhalter, Jean-Charles Flores
  • Patent number: 9859392
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
  • Patent number: 9859169
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 9818847
    Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Robert S. Chau, Marko Radosavljevic, Han Wui Then, Scott B. Clendenning, Ravi Pillarisetty
  • Patent number: 9806075
    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Oh-seong Kwon, Hyeok-jun Son, Sang-jin Hyun, Hoon-joo Na
  • Patent number: 9799656
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 9793369
    Abstract: The present invention provides a MIS-type semiconductor device having a ZrOxNy gate insulating film in which threshold voltage shift is suppressed, thereby achieving stable operation. In the MIS-type semiconductor device having a gate insulating film on the semiconductor layer and a gate electrode on the gate insulating film, with a gate applied voltage of 5 V or more, the gate insulating film is formed of ZrOxNy (x and y satisfy the relation: x>0, y>0, 0.8?y/x?10, and 0.8?0.59x+y?1.0). The MIS-type semiconductor device having such a gate insulating film can perform stable operation because there is no shift in the threshold voltage even if a high voltage is applied to the gate electrode.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 17, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tohru Oka, Takahiro Sonoyama, Kiyotaka Mizukami
  • Patent number: 9780199
    Abstract: A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Shih-Fang Tzou
  • Patent number: 9773696
    Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang
  • Patent number: 9754941
    Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9741798
    Abstract: According to one embodiment, a semiconductor device includes a structure, an insulating film, a control electrode, first and second electrodes. The structure has a first surface, and includes a first, a second, and a third semiconductor region. The structure has a portion including the first, second, and third semiconductor regions arranged in a first direction along the first surface. The insulating film is provided on the first surface. The control electrode is provided on the insulating film. The first electrode is electrically connected to the third semiconductor region. The second electrode is electrically connected to the first semiconductor region. The insulating film includes a charge trap region. A bias voltage is applied to the first and second electrodes, and includes a shift voltage. The shift voltage shifts a reference potential of a voltage applied to the first and second electrodes by a certain voltage.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: August 22, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 9735251
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 15, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hao Deng
  • Patent number: 9691846
    Abstract: A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 27, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tohru Oka, Kazuya Hasegawa, Noriaki Murakami, Takahiro Sonoyama, Nariaki Tanaka
  • Patent number: 9646824
    Abstract: To form a MOSFET over a silicon carbide substrate, when a heat treatment accompanied by nitration is carried out to reduce the interface state density in the vicinity of the boundary between a gate insulating film and a silicon carbide substrate, CV hysteresis occurs due to the relationship between the capacitance and gate voltage of the MOSFET, thereby reducing the reliability of a semiconductor device. To solve the above problem, a heat treatment accompanied by nitration is carried out on the insulating film formed over the silicon carbide substrate (step S7). Then, the insulating film is heated in an inert gas atmosphere (step S9). Thereafter, a field effect transistor having a gate insulating film which is composed of the insulating film is formed over the silicon carbide substrate.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 9, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaki Hama, Yasuaki Kagotoshi
  • Patent number: 9607892
    Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Yu-Cheng Tung
  • Patent number: 9589853
    Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: March 7, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Monica Titus, Gowri Kamarthy, Harmeet Singh, Yoshie Kimura, Meihua Shen, Baosuo Zhou, Yifeng Zhou, John Hoang
  • Patent number: 9583505
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 9559177
    Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Patent number: 9559016
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 9552114
    Abstract: The disclosure is related to a touch panel including a substrate; a low-temperature poly-silicon layer, a first isolating layer, a gate and a second isolating layer arranged in sequence and disposed on a surface of the substrate; a source and a drain disposed on the second isolating layer, the source and the drain disposed separately and respectively connected to the low-temperature poly-silicon layer through a through hole; a planar layer disposed on the source, the drain and the second isolating layer, the planar layer having a first via corresponding to the drain; a filling part filling the first via and the filling part electrically connected to the drain; a third isolating layer disposed on the planar layer, the third isolating layer having a second via corresponding to the filling part; a pixel electrode disposed on the third isolating layer and electrically connected to the filling part through the second via.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: January 24, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Jingfeng Xue, Xin Zhang
  • Patent number: 9543426
    Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 10, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9515082
    Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Digh Hisamoto, Daisuke Okada
  • Patent number: 9508816
    Abstract: A first sacrificial gate structure of a first width and a second sacrificial gate structure of a second width greater than the first width are provided on a semiconductor material portion. A dielectric spacer and a planarizing dielectric material are provided surrounding each sacrificial gate structure. Each sacrificial gate structure is then removed forming gate cavities. A high k dielectric material, a metal nitride hard mask and a physical vapor deposited (PVD) amorphous-silicon cap are provided. Vertical portions of the metal nitride hard mask and the high k dielectric material are removed from a portion of each gate cavity. Additional PVD amorphous silicon is then deposited and then all amorphous silicon and remaining metal nitride hard mask portions are removed. A work function portion having a stair-like surface, a diffusion barrier portion, a conductive metal structure and a dielectric cap are then formed into to each of the gate cavities.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
  • Patent number: RE46271
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama