Sensor With Region Of High Carrier Recombination (e.g., Magnetodiode With Carriers Deflected To Recombination Region By Magnetic Field) Patents (Class 257/424)
  • Patent number: 10424476
    Abstract: Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 24, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Toshiya Suzuki, Viljami J. Pore
  • Patent number: 10060991
    Abstract: Provided is a semiconductor device including a vertical Hall element with improved sensitivity. The vertical Hall element includes: a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a plurality of electrodes aligned along a straight line on a surface of the semiconductor layer and being impurity regions of the second conductivity type being higher in concentration than the semiconductor layer; a plurality of electrode isolation diffusion layers of the first conductivity type respectively arranged between adjacent electrodes of the plurality of electrodes on the surface of the semiconductor layer to isolate the plurality of electrodes from one another; and embedded layers being an impurity region of the second conductivity type which is higher in concentration than the semiconductor layer and being respectively provided substantially right below one of the plurality of electrode isolation diffusion layers between the semiconductor substrate and the semiconductor layer.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 28, 2018
    Assignee: ABLIC INC.
    Inventors: Takaaki Hioka, Mika Ebihara
  • Patent number: 9864020
    Abstract: A vertical Hall sensor, a Hall sensor module, and a method for manufacturing the same are provided. By applying a trench structure inside a substrate with respect to a ground terminal, a directional component parallel to surface of the substrate is maximized with respect to a current flow to detect the magnetic field with improved sensitivity.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 9, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 9786492
    Abstract: Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 10, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Toshiya Suzuki, Viljami J. Pore
  • Patent number: 9786491
    Abstract: Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 10, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Toshiya Suzuki, Viljami J. Pore
  • Patent number: 9041130
    Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya Kobayashi, Kenji Noma, Hisato Oyamatsu
  • Patent number: 8987850
    Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sechung Oh, Jangeun Lee, Woojin Kim, Heeju Shin
  • Patent number: 8987847
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8987848
    Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8969101
    Abstract: A method and structure for a three-axis magnetic field sensing device. An IC layer having first bond pads and second bond pads can be formed overlying a substrate/SOI member with a first, second, and third magnetic sensing element coupled the IC layer. One or more conductive cables can be formed to couple the first and second bond pads of the IC layer. A portion of the substrate member and IC layer can be removed to separate the first and second magnetic sensing elements on a first substrate member from the third sensing element on a second substrate member, and the third sensing element can be coupled to the side-wall of the first substrate member.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 3, 2015
    Assignee: mCube Inc.
    Inventors: Hong Wan, Anthony F. Flannery
  • Patent number: 8941196
    Abstract: Orthogonal spin-torque bit cells whose spin torques from a perpendicular polarizer and an in-plane magnetized reference layer are constructively or destructively combined. An orthogonal spin-torque bit cell includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque; an in-plane magnetized free layer and a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque combine and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction. The first spin-torque and second spin-torque can combine constructively to lower a switching current, increase a switching speed, and/or torque decrease an operating energy of the orthogonal spin-torque bit cell.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 27, 2015
    Assignee: New York University
    Inventors: Daniel Bedau, Huanlong Liu, Andrew David Kent
  • Patent number: 8907376
    Abstract: A stretchable electronic circuit that includes a stretchable base substrate having a plurality of stretchable conductors formed onto a surface thereof, with both the stretchable base substrate and conductors being bendable together about two orthogonal axes. The stretchable circuit also includes a stretchable sensor layer attached to the base substrate with a cavity formed therein which has a contact point exposing one of the plurality of stretchable conductors. The stretchable electronic circuit further includes a surface mount device (SMD) package with a conductor contact protrusion installed into the cavity, and wherein a substantially constant electrical connection is established between the conductor contact protrusion and the stretchable conductor at the contact point by tensile forces interacting between the stretchable base substrate and the stretchable sensor layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 9, 2014
    Assignee: University of Utah Research Foundation
    Inventors: Stephen Mascaro, Debra Mascaro, Jumana Abu-Khalaf, Jungwoo Park
  • Patent number: 8895323
    Abstract: A method for forming MRAM (magnetoresistive random access memory) devices is provided. A bottom electrode assembly is formed. A magnetic junction assembly is formed, comprising, depositing a magnetic junction assembly layer over the bottom electrode assembly, forming a patterned mask over the magnetic junction assembly layer, etching the magnetic junction assembly layer to form the magnetic junction assembly with gaps, gap filling the magnetic junction assembly, and planarizing the magnetic junction assembly. A top electrode assembly is formed.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 25, 2014
    Assignee: Lam Research Corporation
    Inventor: Joydeep Guha
  • Patent number: 8866238
    Abstract: Hybrid integrated components including an MEMS element and an ASIC element are described, whose capacitor system allows both signal detection with comparatively high sensitivity and sensitive activation of the micromechanical structure of the MEMS element. The hybrid integrated component includes an MEMS element having a micromechanical structure which extends over the entire thickness of the MEMS substrate. At least one structural element of this micromechanical structure is deflectable and is operationally linked to at least one capacitor system, which includes at least one movable electrode and at least one stationary electrode. Furthermore, the component includes an ASIC element having at least one electrode of the capacitor system. The MEMS element is mounted on the ASIC element, so that there is a gap between the micromechanical structure and the surface of the ASIC element.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 21, 2014
    Assignee: Robert Bosch GmbH
    Inventor: Johannes Classen
  • Patent number: 8860159
    Abstract: A spintronic electronic apparatus having a multilayer structure. The apparatus includes a substrate, having disposed in succession upon the substrate; a bottom interface layer; a pinned layer; a tunneling barrier; a free layer; and a top interface layer, wherein the apparatus operates as a non-resonant magnetic tunnel junction in a large amplitude, out-of-plane magnetization precession regime having weakly current dependent, large diode volt-watt sensitivity when external microwave signals that exceed a predetermined threshold current and have a frequency that is lower than a predetermined level excite the magnetization precession.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 14, 2014
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Thomas J. Meitzler, Elena N. Bankowski, Michael Nranian, Ilya N. Krivorotov, Andrei N. Slavin, Vasyl S. Tyberkevych
  • Patent number: 8836057
    Abstract: Magnetoresistive elements, and memory devices including the same, include a pinned layer having a fixed magnetization direction, a free layer corresponding to the pinned layer, and a protruding element protruding from the free layer and having a changeable magnetization direction. The free layer has a changeable magnetization direction. The protruding element is shaped in the form of a tube. The protruding element includes a first protruding portion and a second protruding portion protruding from ends of the free layer facing in different directions.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-chul Lee, Ung-hwan Pi, Kwang-seok Kim, Kee-won Kim, Young-man Jang
  • Patent number: 8823007
    Abstract: An integrated MEMS System. CMOS and MEMS devices can be provided in order to form an integrated CMOS-MEMS system. The system can include a silicon substrate layer, a CMOS layer, MEMS and CMOS devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, one which any number of CMOS MEMS devices can be configured. The integrated MEMS devices can include, but not exclusively, an combination of the following types of sensors: magnetic, pressure, humidity, temperature, chemical, biological, or inertial. Furthermore, the overlying WLP layer can be configured to hermetically seal any number of these integrated devices. The present technique provides an easy to use process that relies upon conventional process technology without substantial modifications to conventional equipment and process and reduces off-chip connections, which make the mass production of smaller and thinner units possible.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: September 2, 2014
    Assignee: mCube Inc.
    Inventor: Xiao “Charles” Yang
  • Patent number: 8823119
    Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-joon Kim, Hyung-joon Kwon
  • Patent number: 8815682
    Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Jefferson W. Hall, Mohammed Tanvir Quddus
  • Patent number: 8809978
    Abstract: A memory element includes a layered structure: a memory layer having a changeable magnetization direction, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, including a first ferromagnetic layer having a magnetization direction that is inclined from a direction perpendicular to a film face, a bonding layer laminated on the first ferromagnetic layer, and a second ferromagnetic layer laminated on the bonding layer and bonded to the first ferromagnetic layer via the bonding layer, having a magnetization direction that is inclined from the direction perpendicular to the film face, a magnetization-fixed layer having a fixed magnetization direction, an intermediate layer that is provided between the memory layer and the magnetization-fixed layer, and is contacted with the first ferromagnetic layer, and a cap layer that is contacted with the second ferromagnetic layer.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: August 19, 2014
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8796795
    Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Ebrahim Abedifard
  • Patent number: 8742520
    Abstract: A method and structure for a three-axis magnetic field sensing device is provided. The device includes a substrate, an IC layer, and preferably three magnetic field sensors coupled to the IC layer. A nickel-iron magnetic field concentrator is also provided.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 3, 2014
    Assignee: mCube Inc.
    Inventors: Hong Wan, Xiao (Charles) Yang
  • Patent number: 8710628
    Abstract: An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 29, 2014
    Assignee: Spansion LLC
    Inventor: Juri H. Krieger
  • Patent number: 8710604
    Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Tadashi Kai
  • Patent number: 8692342
    Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sechung Oh, Jangeun Lee, Woojin Kim, Heeju Shin
  • Patent number: 8629518
    Abstract: A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 ? to 400 ?. The MTJ cell structure can have a top conducting layer over the sacrifice layer.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jen Wang, Ya-Chen Kao, Chun-Jung Lin
  • Patent number: 8604573
    Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Yasuyuki Sonoda
  • Patent number: 8592930
    Abstract: A magnetic memory element includes: a first magnetization free layer; a non-magnetic layer; a reference layer; a first magnetization fixed layer group; and a first blocking layer. The first magnetization free layer is composed of ferromagnetic material with perpendicular magnetic anisotropy and includes a first magnetization fixed region, a second magnetization fixed region and a magnetization free region. The non-magnetic layer is provided near the first magnetization free layer. The reference layer is composed of ferromagnetic material and provided on the non-magnetic layer. The first magnetization fixed layer group is provided near the first magnetization fixed region. The first blocking layer is provided being sandwiched between the first magnetization fixed layer group and the first magnetization fixed region or in the first magnetization fixed layer group.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: November 26, 2013
    Assignee: NEC Corporation
    Inventors: Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Norikazu Ohshima, Nobuyuki Ishiwata
  • Patent number: 8580583
    Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: November 12, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Xiaochun Zhu, Xia Li, Seung H. Kang
  • Patent number: 8558333
    Abstract: A method for manipulating domain pinning and reversal in a ferromagnetic material comprises applying an external magnetic field to a uniaxial ferromagnetic material comprising a plurality of magnetic domains, where each domain has an easy axis oriented along a predetermined direction. The external magnetic field is applied transverse to the predetermined direction and at a predetermined temperature. The strength of the magnetic field is varied at the predetermined temperature, thereby isothermally regulating pinning of the domains. A magnetic storage device for controlling domain dynamics includes a magnetic hard disk comprising a uniaxial ferromagnetic material, a magnetic recording head including a first magnet, and a second magnet. The ferromagnetic material includes a plurality of magnetic domains each having an easy axis oriented along a predetermined direction.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: October 15, 2013
    Assignees: The University of Chicago, UCL Business PLC
    Inventors: Daniel M. Silevitch, Thomas F. Rosenbaum, Gabriel Aeppli
  • Patent number: 8513751
    Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-a tan(?)) degrees.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Asao
  • Patent number: 8508006
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: August 13, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8487391
    Abstract: There is provided a magnonic-crystal spin wave device capable of controlling a frequency of a spin wave. The magnonic-crystal spin wave device according to the invention includes a spin wave waveguide made of magnetic material, and the spin wave waveguide guides the spin wave so as to propagate in one direction, and includes a magnonic crystal part which has a cross-section orthogonal to the direction, and at least one of a shape, area size, and center line of the cross-section periodically changes in the direction. In accordance with the invention, it is possible to easily control the frequency of the spin wave using the spin wave waveguide made of single magnetic material.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 16, 2013
    Assignee: Seoul National University Industry Foundation
    Inventors: Sang-koog Kim, Ki-suk Lee, Dong-soo Han
  • Patent number: 8486723
    Abstract: A method and structure for a three-axis magnetic field sensing device is provided. The device includes a substrate, an IC layer, and preferably three magnetic field sensors coupled to the IC layer. A nickel-iron magnetic field concentrator is also provided.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: July 16, 2013
    Assignee: MCube Inc.
    Inventors: Hong Wan, Xiao “Charles” Yang
  • Patent number: 8455966
    Abstract: Provided are transistor devices such as logic gates that are capable of associating a computational state and or performing logic operations with detectable electronic spin state and or magnetic state. Methods of operating transistor devices employing magnetic states are provided. Devices comprise input and output structures and magnetic films capable of being converted between magnetic states.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: C Michael Garner, Dmitri E. Nikonov
  • Publication number: 20130099339
    Abstract: A spintronic electronic apparatus having a multilayer structure. The apparatus includes a substrate, having disposed in succession upon the substrate; a bottom interface layer; a pinned layer; a tunneling barrier; a free layer; and a top interface layer, wherein the apparatus operates as a non-resonant magnetic tunnel junction in a large amplitude, out-of-plane magnetization precession regime having weakly current dependent, large diode volt-watt sensitivity when external microwave signals that exceed a predetermined threshold current and have a frequency that is lower than a predetermined level excite the magnetization precession.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Applicant: The United States of America as Represented by the Secretary of the Army
    Inventors: Thomas J. Meitzler, Elena N. Bankowski, Michael Nranian, Ilya N. Krivorotov, Andrei N. Slavin, Vasyl S. Tyberkevych
  • Patent number: 8421138
    Abstract: A magnetic pinned layer is formed over a substrate. An insulating film is formed over the magnetic pinned layer. A recess is formed in and through the insulating film. A tunneling insulating film is formed over a bottom of the recess. A first magnetic free layer is formed over the bottom of the recess via the tunneling insulating film. A second magnetic free layer is formed over the insulating film and made of a same material as the first magnetic free layer. A non-magnetic film is formed on sidewalls of the recess, extending from the first magnetic free layer to the second magnetic free layer and made of oxide of the material of the first magnetic free layer. An upper electrode is disposed over the first magnetic free layer, non-magnetic film and second magnetic free layer, and electrically connected to the first magnetic free layer and second magnetic free layer.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: April 16, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihisa Iba
  • Patent number: 8217478
    Abstract: A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: July 10, 2012
    Assignee: Seagate Technology LLC
    Inventors: Xiaohua Lou, Yuankai Zheng, Wenzhong Zhu, Wei Tian, Zheng Gao
  • Patent number: 8114684
    Abstract: A complementary metal oxide semiconductor (CMOS) sensor system in one embodiment includes a doped substrate, a doped central island extending downwardly within the doped substrate from an upper surface of the doped substrate, and a first doped outer island extending downwardly within the doped substrate from the upper surface of the doped substrate, the first outer island electrically isolated from the central island within an upper portion of the substrate, and electrically coupled to the central island within a lower portion of the substrate.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: February 14, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Thomas Rocznik, Christoph Lang, Sam Kavusi
  • Patent number: 8089110
    Abstract: An embodiment of the present memory cell includes a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and second electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: January 3, 2012
    Assignee: Spansion LLC
    Inventor: Juri H. Krieger
  • Patent number: 8080485
    Abstract: A method of forming a semiconductor structure comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). The second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8035177
    Abstract: A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 11, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xiaohua Lou, Yuankai Zheng, Wenzhong Zhu, Wei Tian, Zheng Gao
  • Patent number: 7932573
    Abstract: A magnetic memory element having a layer structure containing a fixing layer (pinned layer: PL) having a magnetization direction fixed unidirectionally, a nonmagnetic dielectric layer (TN1) in contact with the fixing layer (PL), and a memory layer (free layer: FL) having a first surface in contact with the nonmagnetic dielectric layer (TN1) and a second surface on the opposite to the first surface, the magnetization direction of the memory layer (FL) having a reversible magnetization direction in response to the current through the layer structure. The entire surface of the first surface of the memory layer (FL) is covered with the nonmagnetic dielectric layer (TN1) and in the joint surface of the nonmagnetic dielectric layer (TN1) and the fixing layer (PL), the first surface of the nonmagnetic dielectric layer (TN1) is exposed in a manner of surrounding the joint surface.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: April 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Takada, Takashi Takenaga, Takeharu Kuroiwa, Taisuke Furukawa
  • Patent number: 7812410
    Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: October 12, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Michael Collonge, Maud Vinet, Olivier Thomas
  • Patent number: 7804151
    Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brennan J. Brown, James R. Elliott, Alvin J. Joseph, Edward J. Nowak
  • Patent number: 7795696
    Abstract: A magnetoresistive memory element has a read module with a first pinned layer that has a magnetoresistance that is readable by a read current received from an external circuit. The element has a write module that receives a write current from the external circuit. A coupling module adjacent both the write module and the read module has a free layer that functions as a shared storage layer for both the read module and the write module. The shared storage layer receives spin torque from both the read module and the write module and has a magnetization that is rotatable by the write current.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: September 14, 2010
    Assignee: Seagate Technology LLC
    Inventors: Oleg N. Mryasov, Thomas F. Ambrose, Werner Scholz
  • Publication number: 20100164483
    Abstract: A Hall element is provided which has a high sensitivity and contributes to an improvement in S/N ratio per current by using a low-concentration n-well within a suitable range. The Hall element includes a p-type semiconductor substrate layer 21 of p-type silicon, and an n-type impurity region 22 located in a surface of the p-type semiconductor substrate layer 21, the n-type impurity region 22 functioning as a magnetic sensing part 26. A p-type impurity region 23 is located in a surface of the n-type impurity region 22, and n-type regions 24 are located laterally of the p-type impurity region 23. A p-type substrate region 21a having a resistivity equal to that of the p-type semiconductor substrate layer 21 is located to extend around the n-type impurity region 22. An impurity concentration N in the n-type impurity region 22 functioning as the magnetic sensing part 26 is preferably from 1×1016 to 3×1016 (atoms/cm3), and a distribution depth D of the impurity concentration is preferably from 3.0 ?m to 5.0 ?m.
    Type: Application
    Filed: March 30, 2007
    Publication date: July 1, 2010
    Inventors: Takayuki Namai, Katsumi Kakuta
  • Patent number: 7745909
    Abstract: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7745893
    Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: June 29, 2010
    Assignee: Northern Lights Semiconductor Corp.
    Inventors: James Chyi Lai, Tom Allen Agan
  • Patent number: RE44878
    Abstract: A ferromagnetic thin-film based digital memory cell with a memory film of an anisotropic ferromagnetic material and with a source layer positioned on one side thereof so that a majority of conduction electrons passing therefrom have a selected spin orientation to be capable of reorienting the magnetization of the film. A disruption layer is positioned on the other side of the memory film so that conduction electrons spins passing therefrom are substantially random in orientation. The magnitude of currents needed to operate the cell can be reduced using coincident thermal pulses to raise the cell temperature.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 6, 2014
    Assignee: NVE Corporation
    Inventors: James M. Daughton, Arthur V. Pohm, Mark C. Tondra