Magnetic Field Patents (Class 257/421)
  • Patent number: 10811597
    Abstract: A magnetoresistive device with a magnetically fixed region having at least two ferromagnetic regions coupled together by an antiferromagnetic coupling region. At least one of the two ferromagnetic regions includes multiple alternating metal layers and magnetic layers and one or more interfacial layers. Wherein, each metal layer includes at least one of platinum, palladium, nickel, or gold, and the interfacial layers include at least one of an oxide, iron, or an alloy including cobalt and iron.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Jijun Sun
  • Patent number: 10811593
    Abstract: Embodiments of the invention can be directed to controlling and/or engineering the size and/or volume of polar nanoregions (PNRs) of ferroelectric polycrystalline material systems. Some embodiments can achieved this via composition modifications to cause changes in the PNRs and/or local structure. Some embodiments can be used to control and/or engineer dielectric, piezoelectric, and/or electromechanical properties of polycrystalline materials. Controlling and/or engineering the PNRs may facilitate improvements to the dielectric, piezoelectric, and/or electromechanical properties of materials. Controlling and/or engineering the PNRs may further facilitate generating a piezoelectric material that may be useful for many different piezoelectric applications.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 20, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Fei Li, Dabin Lin, Shujun Zhang, Thomas R. Shrout, Long-Qing Chen
  • Patent number: 10811595
    Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Oleg Golonzka, Tahir Ghani, Ruth A. Brain, Yih Wang
  • Patent number: 10804319
    Abstract: A top pinned magnetic tunnel junction (MTJ) stack for use in spin-transfer torque magnetoresistive random access memory (STT MRAM) is provided. The top pinned MTJ stack contains a synthetic anti-ferromagnetic magnetic free layer stack that is formed on an insulating aluminum nitride (AlN) seed layer having hexagonal symmetry. For such a top pinned MTJ stack, the symmetry requirements for the tunnel barrier layer do not conflict anymore with the symmetry requirements for strong anti-ferromagnetic exchange. Further, and compared to using only a metallic seed, the insulating AlN seed layer limits spin pumping from the magnetic free layer into the metallic seed layer and therefore lowers the switching current, while only making a small contribution to the resistance of a STT MRAM.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthias G. Gottwald
  • Patent number: 10804460
    Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Daniel B. Bergstrom, Justin S. Brockman, Oleg Golonzka, Tahir Ghani
  • Patent number: 10797230
    Abstract: Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 10796833
    Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, Lawrence A. Clevenger, James Stathis
  • Patent number: 10797225
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2/capping layer configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL1 and PL2, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RACAP is formed on PL2 to provide higher PL2 stability. The condition RA1<RA2 and RACAP<RA2 is achieved when TB1 and the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB2, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan, Sahil Patel, Ru-Ying Tong
  • Patent number: 10797233
    Abstract: The various implementations described herein include methods, devices, and systems for fabricating magnetic memory devices. In one aspect, a method of fabricating a magnetic memory device includes: (1) providing a dielectric substrate with a metallic core protruding from the dielectric substrate, where: (a) a first portion of the metallic core is surrounded by the dielectric substrate and a second portion of the metallic core protrudes away from a surface of the dielectric substrate; and (b) the second portion includes: (i) a surface offset from the surface of the dielectric substrate and (ii) sidewalls extending away from the surface of the dielectric substrate to the offset surface; (2) depositing a first ferromagnetic layer on exposed surfaces of the metallic core and the dielectric substrate; (3) depositing a spacer layer on exposed surfaces of the first ferromagnetic layer; and (4) depositing a second ferromagnetic layer on exposed surfaces of the spacer layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 6, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Marcin Gajek, Michail Tzoufras, Davide Guarisco, Eric Michael Ryan
  • Patent number: 10790635
    Abstract: An apparatus for novel technique of high-speed magnetic recording based on manipulating pinning layer in magnetic tunnel junction-based memory by using terahertz magnon laser is provided. The apparatus comprises a terahertz writing head configured to generate a tunable terahertz writing signal and a memory cell including a spacer that comprises a thickness configured based on Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction. The memory cell comprises two separate memory states: a first binary state and a second binary state; wherein the first binary memory state corresponds to a ferromagnetic sign of the Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction corresponding to a first thickness value of the spacer; and wherein the second binary memory state corresponds to an antiferromagnetic sign of the Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction corresponding to a second thickness value of the spacer. The thickness of the spacer is manipulated by the tunable terahertz writing signal.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 29, 2020
    Assignee: Magtera, Inc.
    Inventor: Boris G. Tankhilevich
  • Patent number: 10783945
    Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC (111) direction.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 22, 2020
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
  • Patent number: 10777737
    Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Shik Kim, Jeong-Heon Park, Gwan-Hyeob Koh
  • Patent number: 10770511
    Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10763428
    Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Po-Kang Wang
  • Patent number: 10763304
    Abstract: The present disclosure provides a semiconductor structure, including a memory region and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a first stop layer being disposed over a magnetic tunneling junction (MTJ) over the first Nth metal line, and a first (N+1)th metal via being disposed over the MTJ and surrounded by the first stop layer, the first (N+1)th metal via having a first height. The logic region includes a second Nth metal line, a second stop layer being disposed over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line and having a second height. N is an integer greater than or equal to 1 and the first height is greater than the second height. A method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chern-Yow Hsu, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10763427
    Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 1, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Ruchil Kumar Jain, Yongshun Sun, Shyue Seng Tan
  • Patent number: 10763426
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Patent number: 10756258
    Abstract: A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 10741477
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 10734443
    Abstract: A material stack includes a first magnetoresistance element with a first direction of response to an external magnetic field and a second magnetoresistance element with second direction of response to the external magnetic field, opposite to the first direction of response. The first magnetoresistance element can be disposed under or over the second magnetoresistance element. An insulating layer separates the first and second magnetoresistance elements.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Rémy Lassalle-Balier, Paolo Campiglio
  • Patent number: 10734013
    Abstract: Spin transfer torque (STT) devices with multilayer seed layers that can be used in magnetic recording and memory are provided. One such STT device includes a substrate, and a stack of layers formed on the substrate, where the stack includes a first seed layer directly on the substrate and including Cr, a second seed layer on the first seed layer and including Ta, a ferromagnetic free layer on the second seed layer; a ferromagnetic polarizing layer, and a nonmagnetic spacer layer between the free layer and the polarizing layer. One such method includes fabricating the STT device.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zheng Gao, Masahiko Hashimoto, Susumu Okamura, James Mac Freitag
  • Patent number: 10734572
    Abstract: A device including a capping layer over a portion of a top electrode, and method of production thereof. Embodiments include an MRAM cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell includes a MTJ pillar between a top electrode and a bottom electrode; and a capping layer over a portion of the top electrode.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yi Jiang, Curtis Chun-I Hsieh, Wanbing Yi, Juan Boon Tan
  • Patent number: 10725100
    Abstract: Methods and apparatus for magnetic field sensor having a sensing element, an analog circuit path coupled to the sensing element for generating an output voltage in response to a magnetic field applied to the sensing element, and a coil in proximity to the sensing element, the coil having a first terminal that is accessible external to the magnetic field sensor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 28, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shaun D. Milano, Michael C. Doogue, William P. Taylor
  • Patent number: 10727397
    Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
  • Patent number: 10727272
    Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region. The memory region includes a first Nth metal line of an Nth metal layer, a magnetic tunneling junction (MTJ) over first Nth metal line, a carbon-based layer between the first Nth metal line and the MTJ, and a first (N+M)th metal via of an (N+M)th metal layer. A method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo, Hung Cho Wang
  • Patent number: 10720178
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula AGa2Ox (0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 21, 2020
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Katsuyuki Nakada, Tatsuo Shibata
  • Patent number: 10720567
    Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10720568
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10720572
    Abstract: A memory device includes a memory stack formed on a substrate to program skyrmions within at least one layer of the stack. The skyrmions represent logic states of the memory device. The memory stack further includes a top and bottom electrode to receive electrical current from an external source and to provide the electrical current to the memory stack. A free layer stores a logic state of the skyrmions in response to the electrical current. A Dzyaloshinskii-Moriya (DM) Interaction (DMI) layer in contact with the free layer induces skyrmions in the free layer. A tunnel barrier is interactive with the DMI layer to facilitate detection of the logic state of the skyrmions in response to a read current. At least one fixed magnetic (FM) layer is positioned within the memory stack to facilitate programming of the skyrmions within the free layer in response to the electrical current.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: July 21, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Michael M. Fitelson, Thomas F. Ambrose, Nicholas D. Rizzo
  • Patent number: 10707356
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Megumi Yakabe, Yasushi Nakasaki, Tadaomi Daibou, Tadashi Kai, Junichi Ito, Masahiro Koike, Shogo Itai, Takamitsu Ishihara
  • Patent number: 10707269
    Abstract: According to one embodiment, a semiconductor storage device includes: a first memory cell and a second memory cell, each including a switching element and a resistance change element coupled to the switching element, and the first memory cell and the second memory cell being adjacent to each other; a non-active member having a switching function between the switching element of the first memory cell and the switching element of the second memory cell; and an insulator which covers at least one of an upper surface or a lower surface of the non-active member, a side surface of the non-active member, a side surface of the switching element of the first memory cell, and a side surface of the switching element of the second memory cell.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshihiko Nagase, Daisuke Watanabe, Koji Ueda, Tadashi Kai, Kazumasa Sunouchi
  • Patent number: 10700123
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Patent number: 10700125
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Patent number: 10700266
    Abstract: An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: June 30, 2020
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jin Pyo Hong, Ja Bin Lee
  • Patent number: 10692521
    Abstract: A storage element is provided. The storage element includes a memory layer; a fixed magnetization layer; an intermediate layer including a non-magnetic material; wherein the intermediate layer is provided between the memory layer and the fixed magnetization layer; wherein the fixed magnetization layer includes at least a first magnetic layer, a second magnetic layer, and a non-magnetic layer, and wherein the first magnetic layer includes a CoFeB composition. A memory apparatus and a magnetic head are also provided.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 23, 2020
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Hiroyuki Uchida
  • Patent number: 10692926
    Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 23, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Jijun Sun, Sanjeev Aggarwal, Han-Jong Chia, Jon M. Slaughter, Renu Whig
  • Patent number: 10692927
    Abstract: A double magnetic tunnel junction (MTJ) stack for use in spin-transfer torque magnetoresistive random access memory (STT MRAM) is provided. The double MTJ stack includes a bottom tunnel barrier layer having hexagonal symmetry and composed of AlN, a magnetic free layer stack containing a synthetic anti-ferromagnetic coupling layer, and a top tunnel barrier layer having cubic symmetry. For such a double MTJ stack, the symmetry requirements for the tunnel barrier layers do not conflict anymore with the symmetry requirements for strong anti-ferromagnetic exchange. Thus, such a double MTJ stack can be used to provide performance enhancement such as faster switching times and lower write errors to a STT MRAM.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthias G. Gottwald
  • Patent number: 10685671
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula AGa2Ox (0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 16, 2020
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Katsuyuki Nakada, Tatsuo Shibata
  • Patent number: 10686125
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Patent number: 10679782
    Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Anurag Chaudhry, Ian A. Young
  • Patent number: 10672976
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 2, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10672604
    Abstract: Improved resistive random access memory (RRAM) devices are provided that use a 2-D electrode as the SET electrode to take up a variable amount of oxygen from an oxide material, thereby providing a non-volatile resistive memory cell.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: June 2, 2020
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Seunghyun Lee, Joon Sohn, Hon-Sum Philip Wong
  • Patent number: 10665776
    Abstract: Provided is a magnetoresistance effect element in which a tunnel barrier layer stably has a cation disordered spinel structure. This magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer disposed between the first ferromagnetic layer and the second ferromagnetic layer. In addition, the tunnel barrier layer is an oxide of MgxAl1-x (0?x<1) and an amount of oxygen in the tunnel barrier layer is lower than an amount of oxygen in a fully oxidized state in which the oxide has an ordered spinel structure.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 26, 2020
    Assignees: TDK CORPORATION, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Shinto Ichikawa, Katsuyuki Nakada, Seiji Mitani, Hiroaki Sukegawa, Kazuhiro Hono, Tadakatsu Ohkubo
  • Patent number: 10665676
    Abstract: Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 26, 2020
    Assignee: Intersil Americas LLC
    Inventors: Dev Alok Girdhar, Jeffrey Michael Johnston
  • Patent number: 10658577
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Iwata
  • Patent number: 10651370
    Abstract: A magnetic data recording element for magnetic random access memory data recording. The magnetic data recording element includes a magnetic tunnel junction element that includes a magnetic reference layer, a magnetic free layer and a non-magnetic barrier layer located between the non-magnetic reference layer and the magnetic free layer. The magnetic free layer includes a layer of Hf that causes the magnetic free layer to have an increased perpendicular magnetic anisotropy. This increased perpendicular magnetic anisotropy improves data retention and increases thermal stability, by preventing the magnetization of the magnetic free layer from inadvertently losing its magnetic orientation.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 12, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Mustafa Pinarbasi, Bartlomiej Adam Kardasz, Jorge Vasquez, Thomas D. Boone
  • Patent number: 10650873
    Abstract: A memory array that comprises three dimensionally stacked two-dimensional memory arrays. The memory array includes a first layer and a second layer oriented orthogonal to the first layer. The memory array further includes a magnetic tunnel junction adjacent to each of the first layer and the second layer. The magnetic tunnel junction further includes a first magnetic layer adjacent to the second layer. Additionally, the magnetic tunnel junction includes a second magnetic layer adjacent to the first layer. The magnetic tunnel junction also includes a tunnel layer adjacent to the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Carnegie Mellon University
    Inventors: Jian-Gang Zhu, Chia-Ling Chien, Qinli Ma
  • Patent number: 10643643
    Abstract: Embodiments of the present disclosure generally relate to a spin torque oscillator device (STO) including a high damping field generation layer or a damping enhancing capping layer for use in microwave assisted magnetic recording (MAMR) write heads. In one embodiment, a STO device for a MAMR write head includes a spin polarization layer, a spacer layer over the spin polarization layer, and a field generation layer over the spacer layer. The field generation layer has a damping in a range from about 0.5% to about 20%.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zheng Gao, James Mac Freitag, Susumu Okamura
  • Patent number: 10643680
    Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 5, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Pinarbasi, Bartek Kardasz
  • Patent number: 10634634
    Abstract: Disclosed is a microsensor package. Particularly, disclosed is a microsensor package, in which a sensing chip is packaged by using PCBs stacked on top of one another, whereby the thickness of the package slim can be kept slim, and at the same time, it can be manufactured at a low cost and can be easily manufactured.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 28, 2020
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun