Magnetic Field Patents (Class 257/421)
  • Patent number: 11189782
    Abstract: A multilayered bottom electrode for a magnetic tunnel junction (MTJ) containing device is provided that includes, from bottom to top, a base segment having a first diameter and composed of a remaining portion of a first bottom electrode metal-containing layer, a middle segment having a second diameter and composed of a remaining portion of a second bottom electrode metal-containing layer, and an upper segment having a third diameter and composed of a remaining portion of a third bottom electrode metal-containing layer, wherein the first diameter is greater than the second diameter, and the third diameter is equal to, or less than, the second diameter. The wider base segment of each multilayered bottom electrode prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Thitima Suwannasiri, Nathan P. Marchack, Pouya Hashemi
  • Patent number: 11183630
    Abstract: A magnetoresistance effect element is provided in which a MR ratio is not likely to decrease even at a high bias voltage. A magnetoresistance effect element according to an aspect of the present invention includes: a first ferromagnetic metal layer; a second ferromagnetic metal layer; a tunnel barrier layer that is provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer, in which the tunnel barrier layer is formed of a non-magnetic oxide having a cubic crystal structure represented by a compositional formula A1-xA?xO, where A represents a divalent cation, and A? represents a trivalent cation, and the number of A ions is more than the number of A? ions in a primitive lattice of the crystal structure.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: November 23, 2021
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11177430
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 16, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11171284
    Abstract: A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Chih-Wei Lu, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 11170832
    Abstract: A magnetic memory device includes a first conductive line extending in a first direction on a substrate, a first magnetic pattern on the first conductive line, the first magnetic pattern including a first portion and a second portion that have different thicknesses, and a second conductive line on the first magnetic pattern and extending in a second direction intersecting the first direction.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Woong Kim, Juhyun Kim, Se Chung Oh, Ung Hwan Pi
  • Patent number: 11165013
    Abstract: The disclosed technology generally relates to magnetic devices and more particularly to magnetic tunnel junction (MTJ) devices in which switching can be mediated by spin-orbit torque, and further relates to a method of fabricating such devices. In an aspect, a magnetic tunnel junction (MTJ) device includes a spin-orbit torque (SOT) mediating layer, a hard-mask layer used to define a shape of the SOT layer, a magnetic tunnel junction arranged between the SOT layer and the hard-mask layer. The MTJ includes at least a free layer and a reference layer separated by a non-magnetic barrier layer. The device further includes at least two electrical accesses arranged to contact the SOT layer to pass a write current therethrough. To provide field-free switching of the free layer, the device further includes a ferromagnetic element as at least one of a ferromagnetic sublayer of the hard-mask and a material in the electrical accesses.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 2, 2021
    Assignee: IMEC vzw
    Inventors: Kevin Garello, Gouri Sankar Kar
  • Patent number: 11165016
    Abstract: According to one embodiment, a method of manufacturing a memory device includes forming a first layer stack and a second layer stack at an interval on a foundation, and forming a first insulator that includes a first portion on a side surface of the first layer stack, a second portion on a side surface of the second layer stack, and a third portion on the foundation between the first and second layer stacks. Part of the first portion of the first insulator and part of the second portion are thinned with an ion beam while leaving the third portion of the first insulator. A second insulator is formed between the first and second portions of the first insulator.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: November 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuyuki Sonoda
  • Patent number: 11162894
    Abstract: An apparatus for generation of coherent terahertz radiation is provided. In one example, the apparatus includes one or more multilayer tunable microcolumns. In turn, a multilayer tunable microcolumn can include a substrate, a bottom electrode, a bottom layer of a ferromagnetic material further comprising a magnon gain medium (MGM) coupled to the bottom electrode, a tunnel junction coupled to the ferromagnetic material, a spin injector coupled to the tunnel junction, a pinning layer coupled to the spin injector, a reference layer coupled to the pinning layer and a top electrode. In one example, a containment cavity encloses at least one of the multilayer tunable microcolumns. In one example, a storage cavity encloses the containment cavity.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 2, 2021
    Assignee: Magtera, Inc.
    Inventor: Boris G. Tankhilevich
  • Patent number: 11152047
    Abstract: A magnetic memory device contains a synthetic antiferromagnetic (SAF) structure that includes an antiferromagnetically coupled stack and a reference layer. The antiferromagnetically coupled stack contains plural multilayer stacks. Each multilayer stack contains at least one ferromagnetic material layer, a non-magnetic layer and a non-magnetic SAF spacer layer having a different composition than the non-magnetic layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Wonjoon Jung, Michael Nicolas Albert Tran
  • Patent number: 11145813
    Abstract: A conductive microstud is formed in a recess of an insulator layer formed on the substrate. A bottom pedestal is formed on a top surface of the microstud. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A top pedestal is formed on a top surface of the bottom pedestal. The top surface of at least one of the bottom pedestal and top pedestal is planarized. A conductive layer is formed on a top surface of the top pedestal. Next, a conical structure is formed. The conical structure is comprised of at least the conductive layer and a top portion of the top pedestal.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert, Daniel C Edelstein
  • Patent number: 11145806
    Abstract: A device includes a plurality of bottom electrode features, a plurality of Magnetic Tunnel Junction (MTJ) stacks formed on top surfaces of the bottom electrode features, top electrode features formed on top of the MTJ stacks, and an etch stop layer extending along side surfaces of the bottom electrode feature and partially along side surfaces of the MTJ stacks.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Harry-Hak-Lay Chuang, Ru-Liang Lee
  • Patent number: 11133374
    Abstract: A method includes depositing a magnetic layer over a dielectric layer, and etching a first portion of the magnetic layer, in which a second portion of the magnetic layer that is directly under the first portion of the magnetic layer remains over the dielectric layer after etching the first portion of the magnetic layer. The second portion of the magnetic layer is etched.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Shuo Su, Chun-Tsung Kuo, Jiech-Fun Lu
  • Patent number: 11127895
    Abstract: According to one embodiment, a magnetic memory device includes a first insulating region, a first counter insulating region, a first conductive member, and a first magnetic element. The first conductive member is provided between the first insulating region and the first counter insulating region. The first conductive member extends in a first direction crossing a second direction. The second direction is from the first insulating region toward the first counter insulating region. The first magnetic element is provided between the first insulating region and the first counter insulating region. A third direction from the first conductive member toward the first magnetic element crosses a plane including the first and second directions. A portion of a first insulating side surface of the first insulating region opposes the first conductive member. A portion of a first counter insulating side surface of the first counter insulating region opposes the first conductive member.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 21, 2021
    Assignee: KABUSHIKl KAISHA TOSHIBA
    Inventors: Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Altansargai Buyandalai, Mariko Shimizu, Hiroaki Yoda
  • Patent number: 11127789
    Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Na Cho, Bok-Yeon Won, Oik Kwon
  • Patent number: 11121173
    Abstract: Techniques for preserving the underlying dielectric layer during MRAM device formation are provided. In one aspect, a method of forming an MRAM device includes: depositing a first dielectric cap layer onto a substrate over logic and memory areas of the substrate; depositing a sacrificial metal layer onto the first dielectric cap layer; patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer in at least the logic area; depositing a second dielectric cap layer onto the first dielectric cap layer; forming an MRAM stack on the second dielectric cap layer; patterning the MRAM stack using ion beam etching into at least one memory cell, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area; and removing the patterned sacrificial metal layer. An MRAM device is also provided.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Michael Rizzolo
  • Patent number: 11121306
    Abstract: Provided are a magnetic tunnel junction device and a method of fabricating the same. The magnetic tunnel junction device includes a heavy metal layer, a free magnetic layer disposed on the heavy metal layer, and a tunnel insulating layer disposed on the free magnetic layer. The heavy metal layer includes platinum (Pt), the free magnetic layer includes cobalt (Co), a magnetization state of the free magnetic layer has an easy-cone state, the free magnetic layer has a positive first-order perpendicular magnetic anisotropy constant and a negative second-order perpendicular magnetic anisotropy constant, and the tunnel insulating layer includes magnesium oxide (MgO).
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 14, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Sang Ho Lim, Hyung-Keun Gweon, Seong Rae Lee
  • Patent number: 11121310
    Abstract: A structure used in the formation of a spintronics element, the spintronics element to include a plurality of laminated layers, includes a substrate, a plurality of laminated layers formed on the substrate, an uppermost layer of the plurality of laminated layers being a non-magnetic layer containing oxygen, and a protection layer directly formed on the uppermost layer, the protection layer preventing alteration of characteristics of the uppermost layer while exposed in an atmosphere including H2O, a partial pressure of H2O in the atmosphere being equal to or larger than 10?4 Pa, no other layer being directly formed on the protection layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 14, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Soshi Sato, Masaaki Niwa, Hiroaki Honjo, Shoji Ikeda, Hideo Ohno, Tetsuo Endo
  • Patent number: 11114611
    Abstract: A method to make magnetic random access memory with small footprint using O-ion implantation to form electrically isolated memory pillar and electric (bottom and top) leads, which are made from some oxygen gettering materials, Mg, Zr, Y, Th, Ti, Al, Ba. The doped O-ions react with metal atoms to form fully oxidized metal oxide after high temperature anneal. The method only needs two photolithography patterning and oxygen implantations and no etch and dielectric refill are needed, thus significantly reduce process cost. The method can produce extremely small MRAM cell size with perfectly vertical pillar edges (FIG. 1).
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: September 7, 2021
    Inventor: Yimin Guo
  • Patent number: 11114376
    Abstract: A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
  • Patent number: 11105867
    Abstract: The object of the present invention is to attain an unconventionally high tunnel magnetoresistance (TMR) ratio by using a barrier layer made of an MgAl2O4 type insulator material with a spinel structure. The problem can be solved by a magnetic tunnel junction in which a barrier layer is made of a cubic nonmagnetic material having a spinel structure, and both of two ferromagnetic layers that are adjacently on and below the barrier layer are made of a Co2FeAl Heusler alloy. Preferably, the nonmagnetic material is made of oxide of an Mg1?xAlx (0<x?1) alloy, and exhibits tunnel magnetoresistance of 250% or more and 34000% or less at a room temperature.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: August 31, 2021
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Hiroaki Sukegawa, Thomas Scheike, Seiji Mitani, Tadakatsu Ohkubo, Kazuhiro Hono, Kouichiro Inomata
  • Patent number: 11107615
    Abstract: A magnetization rotational element includes a ferromagnetic metal layer, and a spin-orbit torque wiring extending in a first direction intersecting a lamination direction of the ferromagnetic metal layer and having the ferromagnetic metal layer positioned on one surface thereof, in which a direction of spin injected from the spin-orbit torque wiring into the ferromagnetic metal layer intersects a magnetization direction of the ferromagnetic metal layer, and a damping constant of the ferromagnetic metal layer is larger than 0.01.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK CORPORATION
    Inventors: Tohru Oikawa, Tomoyuki Sasaki, Yohei Shiokawa, Tatsuo Shibata
  • Patent number: 11107980
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Patent number: 11094878
    Abstract: A spin-transfer torque magneto-resistive random access memory (STT-MRAM) device is provided. The STT-MRAM device includes a substrate, a dielectric layer and a magnetic tunnel junction (MTJ) stack. The substrate includes a conductor and a landing pad. The MTJ stack includes a reference layer element, a free layer assembly and a barrier layer element. The reference layer element is lined with redeposited metal and is disposed on the landing pad within the dielectric layer. The free layer assembly includes a free layer element, a hard mask layer element disposed on the free layer element, redeposited metal lining sidewalls of the free and hard mask layer elements and dielectric material lining the redeposited metal. The barrier layer element is interposed between and has a same width as the reference layer element and the free layer assembly.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Bruce B. Doris, Eugene J. O'Sullivan
  • Patent number: 11087810
    Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/?m2, switching voltage <0.15 V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hideaki Fukuzawa, Vignesh Sundar, Yu-Jen Wang, Ru-Ying Tong
  • Patent number: 11088204
    Abstract: A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Willy Rachmady
  • Patent number: 11088199
    Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Wu-Chang Tsai, Tien-Wei Chiang
  • Patent number: 11081643
    Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel C. Edelstein
  • Patent number: 11075335
    Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11069853
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 20, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Hsin-Wei Tseng, Chando Park, Jaesoo Ahn, Lin Xue, Mahendra Pakala
  • Patent number: 11063212
    Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming MTJ layers over a dielectric layer; performing a first etching operation on the MTJ layers to form MTJ stacks, in which the first etching operation is performed such that a metal-containing doped region is formed in the dielectric layer and between the MTJ stacks; and performing a second etching operation to break through the metal-containing doped region.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chern-Yow Hsu
  • Patent number: 11062752
    Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Tofizur Rahman, James Pellegren, Angeline Smith, Christopher Wiegand, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Ian Young
  • Patent number: 11056640
    Abstract: Magnetoelectric or magnetoresistive memory cells include at least one of a high dielectric constant dielectric capping layer and/or a nonmagnetic metal dust layer located between the free layer and the dielectric capping layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 6, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Matthew Carey, Alan Kalitsov, Bruce Terris
  • Patent number: 11056643
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. In the method there is provided an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a metal hardmask layer on a surface of said MTJ cap layer, the etch stop layer being subject to lithographic patterning and etching to form a patterned hardmask pillar structure. An encapsulating is performed to encapsulate, using an insulating material film, a top surface and sidewall surfaces of said patterned hardmask layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned hardmask without impacting MTJ stack performance.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris
  • Patent number: 11054490
    Abstract: A magnetic field detection device includes a base, a first yoke, and a magneto-resistive effect element. The first yoke is provided on the base, and includes first and second principal surfaces each extending along a first plane, and a first end surface coupling the first and second principal surfaces. The magneto-resistive effect element is provided on the base, and includes a magnetization free layer disposed at a position overlapped with the first yoke in a first direction along the first plane. The first end surface includes an inverted tapered surface inclined relative to the first plane and extending closer to a center point of the magnetization free layer as being away from the base in a second direction orthogonal to the first plane. A distance from the center point to a first edge is shorter than a distance from the center point to a second edge.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 6, 2021
    Assignee: TDK CORPORATION
    Inventors: Yoshiaki Tanaka, Tetsuya Hiraki, Kazuya Watanabe, Suguru Watanabe
  • Patent number: 11050017
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 29, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu, Hung-Chan Lin
  • Patent number: 11043380
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 22, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 11043630
    Abstract: A magnetoresistive device may include an intermediate region positioned between a magnetically fixed region and a magnetically free region, and spin Hall channel region extending around a sidewall of at least the magnetically free region. An insulator region may extend around a portion of the sidewall such that the insulator region contacts a first portion of the sidewall and the spin Hall channel region contacts a second portion of the sidewall.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 22, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Sarin A. Deshpande
  • Patent number: 11043632
    Abstract: A first pattern is formed on an MTJ stack as a first array of first parallel bands. A first ion beam etching is performed on the MTJ stack using the first pattern wherein a tilt between an ion beam source and the substrate is maintained such that a horizontal component of the ion beam is parallel to the first parallel bands and the substrate is not rotated. Thereafter, a second pattern is formed on the MTJ stack as a second array of parallel bands wherein the second parallel bands are perpendicular to the first parallel bands. A second ion beam etching is performed using the second pattern wherein a tilt between an ion beam source and the substrate is maintained such that a horizontal component of the ion beam is parallel to the second parallel bands and wherein the substrate is not rotated to complete formation of the MTJ structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: June 22, 2021
    Assignee: Headway Technologies, Inc.
    Inventors: Vignesh Sundar, Guenole Jan, Dongna Shen, Yi Yang, Yu-Jen Wang
  • Patent number: 11037611
    Abstract: A magnetic property measuring system includes coil structures configured to apply a magnetic field to a sample, a light source configured to irradiate incident light to the sample, and a detector configured to detect polarization of light reflected from the sample. The magnetic field is perpendicular to a surface of the sample. Each coil structure includes a pole piece and a coil surrounding an outer circumferential surface of the pole piece. A wavelength of the incident light is equal to or less than about 580 nm.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunsun Noh, Juhyun Kim, Ung Hwan Pl
  • Patent number: 11029338
    Abstract: A current sensor includes a die and a shunt resistor having a first temperature coefficient and having a first node and a second node fabricated onto the die, wherein the shunt resistor is for passing the current that is to be sensed. A first compensation resistor is fabricated onto the die and is coupled to the first node of the shunt resistor, wherein the first compensation resistor is proximate the shunt resistor and has a temperature coefficient that is similar to the temperature coefficient of the shunt resistor. A second compensation resistor is fabricated onto the die and is coupled to the second node of the shunt resistor, wherein the second compensation resistor is proximate the shunt resistor and has a temperature coefficient that is the close to the temperature coefficient of the shunt resistor.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 8, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Cetin Kaya
  • Patent number: 11031546
    Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 8, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Kenneth H. Smith, Moazzem Hossain, Sanjeev Aggarwal
  • Patent number: 11029372
    Abstract: A Hall element including a contact is provided. A Hall element is provided, including: a substrate; a magnetosensitive portion formed on the substrate; an insulating film formed on the magnetosensitive portion; and a conductive portion which is formed on the insulating film, extends from a peripheral region of the magnetosensitive portion toward a central region of the magnetosensitive portion, penetrates the insulating film, and is electrically connected to the magnetosensitive portion, wherein when observing a cross section passing through a center of the magnetosensitive portion in plan view and a portion at which the conductive portion is in contact with the magnetosensitive portion, at least a part of the conductive portion extends below the insulating film in the cross section.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 8, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tsuyoshi Akagi, Tetsuya Takahashi
  • Patent number: 11024797
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 11024801
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 1, 2021
    Inventors: Jung-Tang Wu, Jui-Hung Ho, Chin-Szu Lee, Meng-Yu Wu, Szu-Hua Wu
  • Patent number: 11011579
    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Samuele Sciarrillo
  • Patent number: 11005033
    Abstract: A component semiconductor structure having a semiconductor layer, which has a front side and a back side, at least one integrated circuit being formed on the front side and a first oxide layer being formed on the back side, a monolithically formed semiconductor body having a top surface and a back surface being provided, and a second oxide layer being formed on the back surface, and the two oxide layers being integrally connected to each other, and a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to the top surface, and at least three first highly doped semiconductor contact regions being formed on the top surface and at least three second highly doped semiconductor contact regions being formed on the lower surface.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 11, 2021
    Assignee: TDK-Micronas GmbH
    Inventors: Martin Cornils, Maria-Cristina Vecchi
  • Patent number: 11005034
    Abstract: Magnetoelectric or magnetoresistive memory cells include at least one of a high dielectric constant dielectric capping layer and/or a nonmagnetic metal dust layer located between the free layer and the dielectric capping layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 11, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Matthew Carey, Alan Kalitsov, Bruce Terris
  • Patent number: 11005035
    Abstract: A magnetoresistive effect element includes a first ferromagnetic layer and a tunnel barrier layer. The tunnel barrier layer has a main body region and a first interface region. The main body region has an oxide material of a first spinel structure represented by a general formula LM2O4. The first interface region has at least one element X selected from a group consisting of elements having a valence of 2 and elements having a valence of 3 excluding Al and has an oxide material of a second spinel structure represented by a general formula DG2O4(D represents one or more kinds of elements including Mg or the element X, and G represents one or more kinds of elements including Al or the element X). A content of the element X contained in the first interface region is larger than that of the element X contained in the main body region.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 11, 2021
    Assignee: TDK CORPORATION
    Inventors: Tsuyoshi Suzuki, Katsuyuki Nakada, Shinto Ichikawa
  • Patent number: 10998906
    Abstract: A logic function device according to an embodiment of the present invention includes one or more function reconfiguring units having magnetization in one direction set by spin torque caused due to an function reconfiguring current, and an output terminal formed at an end thereof; and one or more input units formed on the function reconfiguring unit and having magnetization in the one direction set by spin torque caused due to an input current, wherein an output voltage of the output terminal is determined on the basis of whether a magnetization direction of the function reconfiguring unit and a magnetization direction of the input unit are parallel or anti-parallel.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 4, 2021
    Inventors: Kyoung Whan Kim, Dong Soo Han, Byoung Chul Min, Seok Min Hong, Hyun Cheol Koo, Hyung Jun Kim, Tae Eon Park, Ouk Jae Lee
  • Patent number: 10998377
    Abstract: The present disclosure provides a semiconductor structure, including a memory region, a first metal line in the memory region, a magnetic tunneling junction (MTJ) cell over the first metal line, a carbon-based layer between the first metal line and the MTJ cell, a second metal line over the MTJ cell, a logic region adjacent to the memory region, wherein the logic region is free from a coverage of the carbon-based layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo, Hung Cho Wang