Magnetic Field Patents (Class 257/421)
  • Patent number: 11508904
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: November 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11506733
    Abstract: A magnetic sensor comprises a magnetoresistive effect element including a first side surface and a second side surface facing in opposite directions along a first axis and a first end surface and a second end surface facing in opposite directions along a second axis substantially orthogonal to the first axis. The sensor has a sensitivity axis extending in a direction of the first axis, a first yoke unit provided adjacent to the first side surface of the magnetoresistive effect element, and a first bias magnetic field generation unit provided adjacent to the first end surface of the magnetoresistive effect element. The first bias magnetic field generation unit is provided to be capable of applying a bias magnetic field on the magnetoresistive effect element and the first yoke unit.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 22, 2022
    Assignee: TDK Corporation
    Inventors: Kenichi Takano, Tsuyoshi Umehara, Yuta Saito, Hiraku Hirabayashi
  • Patent number: 11502242
    Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Chih-Chao Yang, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 11502241
    Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: MingYuan Song, Shy-Jay Lin, William J. Gallagher, Hiroki Noguchi
  • Patent number: 11495735
    Abstract: A spin-current magnetization rotational element includes: a ferromagnetic metal layer; and a spin-orbit torque wiring that extends in a first direction intersecting a stacking direction of the ferromagnetic metal layer and is bonded to the ferromagnetic metal layer. A direction of a spin injected into the ferromagnetic metal layer from the spin-orbit torque wiring intersects a magnetization direction of the ferromagnetic metal layer. The ferromagnetic metal layer has shape anisotropy and has a demagnetizing field distribution caused by the shape anisotropy. The demagnetizing field distribution generates an easy magnetization rotational direction in which the magnetization of the ferromagnetic metal layer is most easily reversed. The easy magnetization rotational direction intersects the first direction in a plan view seen from the stacking direction.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: November 8, 2022
    Assignee: TDK CORPORATION
    Inventors: Tatsuo Shibata, Tomoyuki Sasaki, Tohru Oikawa
  • Patent number: 11495741
    Abstract: A SOT device includes a bismuth antimony dopant element (BiSbE) alloy layer over a substrate. The BiSbE alloy layer is used as a topological insulator. The BiSbE alloy layer includes bismuth, antimony, AND a dopant element. The dopant element is a non-metallic dopant element, a metallic dopant element, and combinations thereof. Examples of metallic dopant elements include Ni, Co, Fe, CoFe, NiFe, NiCo, NiCu, CoCu, NiAg, CuAg, Cu, Al, Zn, Ag, Ga, In, or combinations thereof. Examples of non-metallic dopant elements include Si, P, Ge, or combinations thereof. The BiSbE alloy layer can include a plurality of BiSb lamellae layers and one or more dopant element lamellae layers. The BiSbE alloy layer has a (012) orientation.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Brian R. York, Cherngye Hwang, Alan Spool, Michael Gribelyuk, Quang Le
  • Patent number: 11495738
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistanceƗarea (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Patent number: 11489111
    Abstract: A memory device includes two phase change memory (PCM) cells and a bridge. The first PCM cell includes an electrical input and a phase change material. The second PCM cell includes an electrical input that is independent from the electrical input of the first PCM cell and another phase change material. The bridge is electrically connected to the two PCM cells.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Junli Wang, Su Chen Fan
  • Patent number: 11482570
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 25, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Thomas Andre, Sarin A. Deshpande
  • Patent number: 11476412
    Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Noriyuki Sato, Kevin O'Brien, Benjamin Buford, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • Patent number: 11476303
    Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 18, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • Patent number: 11469371
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Yuan Song, Shy-Jay Lin
  • Patent number: 11462253
    Abstract: Provided is a magnetoresistance effect element in which the magnetization direction of the recording layer is perpendicular to the film surface and which has a high thermal stability factor ?, and a magnetic memory. A recording layer having a configuration of first magnetic layer/first non-magnetic coupling layer/first magnetic insertion layer/second non-magnetic coupling layer/second magnetic layer is sandwiched between the first and second non-magnetic layers and stacked so that a magnetic coupling force is generated between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 4, 2022
    Assignee: TOHOKU UNIVERSITY
    Inventors: Koichi Nishioka, Tetsuo Endoh, Shoji Ikeda, Hiroaki Honjo, Hideo Sato, Hideo Ohno
  • Patent number: 11462584
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonsung Han, Seung Pil Ko
  • Patent number: 11462583
    Abstract: A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Chih-Chao Yang, Daniel Charles Edelstein, John Arnold, Theodorus E. Standaert
  • Patent number: 11450466
    Abstract: The invention comprises a novel composite seed structure (CSS) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)]n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 20, 2022
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 11437432
    Abstract: An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kilho Lee, Gwanhyeob Koh, Woojin Kim
  • Patent number: 11437431
    Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Chiang Min
  • Patent number: 11430943
    Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Patent number: 11424405
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Patent number: 11417835
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance x area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Jian Zhu, Huanlong Liu
  • Patent number: 11417834
    Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 16, 2022
    Assignee: Purdue Research Foundation
    Inventors: Shehrin Sayed, Vinh Quang Diep, Kerem Y Camsari, Supriyo Datta
  • Patent number: 11411173
    Abstract: Material stacks for perpendicular spin transfer torque memory (pSTTM) devices, pSTTM devices and computing platforms employing such material stacks, and methods for forming them are discussed. The material stacks include a cladding layer of predominantly tungsten on a protective layer, which is in turn on an oxide capping layer over a magnetic junction stack. The cladding layer reduces oxygen dissociation from the oxide capping layer for improved thermal stability and retention.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Angeline Smith, Justin Brockman, Tofizur Rahman, Daniel Ouellette, Andrew Smith, Juan Alzate Vinasco, James ODonnell, Christopher Wiegand, Oleg Golonzka
  • Patent number: 11404098
    Abstract: A memory device includes a first ferromagnetic layer, an insulating layer above the first ferromagnetic layer, a second ferromagnetic layer above the insulating layer, a capping layer on an upper surface of the second ferromagnetic layer, and an electrode on an upper surface of the capping layer. The second ferromagnetic layer includes iron atoms. The capping layer includes one or more elements identical to one or more elements in the second ferromagnetic layer. The electrode includes one or more elements identical to one or more of the elements in the capping layer and includes a material having a Vickers hardness higher than a Vickers hardness of an iron atom.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 2, 2022
    Assignees: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga Isoda, Eiji Kitagawa, Young Min Eeh, Tadaaki Oikawa, Kazuya Sawada, Jin Won Jung
  • Patent number: 11404630
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Md Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Justin S. Brockman, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11404369
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Patent number: 11404631
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 2, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
  • Patent number: 11401161
    Abstract: A distributed sensor system is disclosed that provides spatial and temporal data in an operating environment. The distributed sensor nodes can be coupled together to form a distributed sensor system. For example, a distributed sensor system comprises a collection of Sensor Nodes (SN) that are physically coupled and are able to collect data about the environment in a distributed manner. For example, a first sensor node and a second sensor node is formed respectively in a first region and a second region of the semiconductor substrate. A flexible interconnect is formed overlying the semiconductor substrate and couples the first sensor node to the second sensor node. A portion of the semiconductor substrate is removed by etching beneath the flexible interconnect such that the distributed sensor system has multiple degrees of freedom that support following surface contours or sudden changes of direction.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 2, 2022
    Assignee: Versana Micro Inc.
    Inventor: Bishnu Prasanna Gogoi
  • Patent number: 11391794
    Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit-torque wiring; and a laminated body laminated on the spin-orbit-torque wiring, wherein the laminated body includes a first ferromagnetic layer, an oxide containing layer, and a second ferromagnetic layer in order from the spin-orbit-torque wiring, wherein the oxide containing layer contains an oxide of a non-magnetic element, and wherein the first ferromagnetic layer and the second ferromagnetic layer are ferromagnetically coupled to each other.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 19, 2022
    Assignee: TDK CORPORATION
    Inventor: Yohei Shiokawa
  • Patent number: 11387141
    Abstract: A method for semiconductor device fabrication includes forming storage elements on conductive structures. An interlevel dielectric (ILD) layer is formed over the storage elements. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11387405
    Abstract: A memory device includes a plurality of layers forming a stack. The plurality of layers include a spin polarization layer having a magnetic anisotropy approximately perpendicular to a plane of the spin polarization layer, an antiferromagnetic layer having an antiferromagnetic material, a ferromagnetic layer that is exchange coupled to the antiferromagnetic layer, where the antiferromagnetic layer is between the ferromagnetic layer and the spin polarization layer, and a storage layer having a magnetization direction that indicates a memory state of the storage layer. The memory state is switched by an amount of current through the stack. The spin polarization layer, the ferromagnetic layer, and the antiferromagnetic layer are configured to reduce the amount of current through the stack for switching the magnetization direction of the storage layer relative to an amount of current through a memory device without the spin polarization layer, the ferromagnetic layer, and the antiferromagnetic layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 12, 2022
    Assignee: Carnegie Mellon University
    Inventor: Jian-Gang Zhu
  • Patent number: 11387407
    Abstract: A spin-orbit-torque magnetization rotational element and a spin-orbit-torque magnetoresistance effect element capable of easily rotating or reversing magnetization of a ferromagnetic layer. The spin-orbit-torque magnetization rotational element includes spin-orbit-torque wiring and a first ferromagnetic layer laminated on the spin-orbit-torque wiring in a first direction, wherein the spin-orbit-torque wiring includes a first region extending in a second direction, a second region extending in a third direction different from the second direction, and an intersection region where the first region and the second region intersect, and wherein the first ferromagnetic layer and the intersection region at least partially overlap in a plan view from the first direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 12, 2022
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Yohei Shiokawa, Minoru Sanuki
  • Patent number: 11386951
    Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Brian Doyle, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Patent number: 11380838
    Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Justin Brockman, Conor Puls, Stephen Wu, Christopher Wiegand, Tofizur Rahman, Daniel Ouellette, Angeline Smith, Andrew Smith, Pedro Quintero, Juan Alzate-Vinasco, Oleg Golonzka
  • Patent number: 11374167
    Abstract: An embedded magnetoresistive random-access memory (MRAM) device including a portion of a metal wiring layer above a semiconductor device and a bottom electrode over the portion of the metal wiring layer. The embedded MRAM where the bottom electrode connects to a first portion of a bottom surface of a magnetoresistive random access memory pillar and a sidewall spacer is on the magnetoresistive random access memory pillar. The embedded MRAM device includes a ring of inner metal is on the portion of the metal wiring layer surrounding a portion of the bottom electrode.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Alexander Reznicek, Bruce B. Doris
  • Patent number: 11372061
    Abstract: A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 28, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yongshun Sun, Eng Huat Toh, Ping Zheng
  • Patent number: 11374163
    Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-Ching Lin, Sasikanth Manipatruni, Dmitri Nikonov, Ian Young
  • Patent number: 11374164
    Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Chia-Ching Lin, Kaan Oguz, Christopher Wiegand, Angeline Smith, Noriyuki Sato, Kevin O'Brien, Benjamin Buford, Ian Young, Md Tofizur Rahman
  • Patent number: 11367749
    Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Tofizur Rahman, Gary Allen, Atm G. Sarwar, Ian Young, Hui Jae Yoo, Christopher Wiegand, Benjamin Buford
  • Patent number: 11362270
    Abstract: A magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer. The tunnel barrier layer is a stacked body including one or more first oxide layers having a spinel structure and one or more second oxide layers having a spinel structure with a composition which is different from a composition of the first oxide layer.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 14, 2022
    Assignee: TDK CORPORATION
    Inventors: Shinto Ichikawa, Katsuyuki Nakada, Tomoyuki Sasaki
  • Patent number: 11361805
    Abstract: A memory device includes a first electrode, a second electrode that is spaced from the first electrode, a fixed vertical magnetization structure configured to generate a fixed vertical magnetic field and located between the first electrode and the second electrode, at least one layer stack located between the fixed magnetization structure and the second electrode and containing respective spacer dielectric layer and a respective additional reference layer including a respective ferromagnetic material having perpendicular magnetic anisotropy, and a magnetic tunnel junction located between the at least one layer stack and the second electrode, the magnetic tunnel junction containing a reference layer, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, and the reference layer being more proximal to the at least one layer stack than the free layer is to the at least one layer stack.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: June 14, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Goran Mihajlovic, Wonjoon Jung, Bhagwati Prasad
  • Patent number: 11362263
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Tanay Gosavi, Justin Brockman, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • Patent number: 11355700
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 11355701
    Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 11348971
    Abstract: The present invention is directed to a perpendicular magnetic structure comprising a first seed layer including tantalum, a second seed layer deposited on top of the first seed layer and including iridium, a third seed layer deposited on top of the second seed layer, and a fourth seed layer deposited on top of the third seed layer and including chromium. The third seed layer includes one of NiFe, NiFeB, NiFeCr, CoFeB, CoFeTa, CoFeW, CoFeMo, CoFeTaB, CoFeWB, or CoFeMoB. The perpendicular magnetic structure further includes a magnetic fixed layer structure formed on top of the fourth seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane of the magnetic fixed layer structure. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The magnetic material includes cobalt. The transition metal includes one of nickel, platinum, palladium, or iridium.
    Type: Grant
    Filed: February 13, 2021
    Date of Patent: May 31, 2022
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 11348868
    Abstract: A channel structure for signal transmission is provided. The channel structure includes a first common pad, disposed on a first layer; a second common pad, disposed on a second layer; a via, for electrically connecting the first common pad and the second common pad; a first device path pad, disposed on the second layer and located in a first direction of the second common pad; and a second device path pad disposed on the second layer and located in a second direction of the second common pad. The channel structure includes a first electrical element electrically coupled between the second common pad and the first device path pad, or includes a second electrical element electrically coupled between the second common pad and the second device path pad.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Wistron Corporation
    Inventors: Kun-Hung Tsai, Yu-Jhan Lin
  • Patent number: 11348886
    Abstract: An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
  • Patent number: 11342497
    Abstract: Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: May 24, 2022
    Assignee: Everspin Technologies, Inc.
    Inventor: Han-Jong Chia
  • Patent number: 11335850
    Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 17, 2022
    Assignee: International Business Machines Corporation
    Inventors: Karthik Yogendra, Robert Robison, Eric Raymond Evarts
  • Patent number: 11335728
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 17, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Thomas Andre, Sarin A. Deshpande