Magnetic Field Patents (Class 257/421)
  • Patent number: 10446740
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula of AIn2Ox (0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 15, 2019
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Katsuyuki Nakada, Tatsuo Shibata
  • Patent number: 10446607
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDARIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
  • Patent number: 10439616
    Abstract: The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin waves. In one aspect, a majority gate device comprises cells that are configurable as spin wave generators or spin wave detectors. The majority gate device comprises an odd number of spin wave generators, and at least one spin wave detector. The majority gate device additionally comprises a waveguide adapted for guiding spin waves generated by the spin wave generators. The spin wave generators and the at least one spin wave detector are positioned in an inline configuration along the waveguide such that, in operation, interference of the spin waves generated by the spin wave generators can be detected by the at least one spin wave detector. The interference of the spin waves corresponds to a majority operation of the spin waves generated by the spin wave generators.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 8, 2019
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Odysseas Zografos, Bart Soree, Florin Ciubotaru, Hanns Christoph Adelmann
  • Patent number: 10439133
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a hybrid free layer. The hybrid free layer is switchable between stable magnetic states using a current passed through the magnetic junction. The nonmagnetic spacer layer is between the free layer and the reference layer. The hybrid free layer includes a soft magnetic layer, a hard magnetic layer and an oxide coupling layer between the hard magnetic layer and the soft magnetic layer. The soft magnetic layer has a soft layer magnetic thermal stability coefficient of not more than thirty. The hard magnetic layer has a hard layer magnetic thermal stability coefficient of at least twice the soft layer magnetic thermal stability coefficient.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dmytro Apalkov, Xueti Tang, Vladimir Nikitin, Shuxia Wang, Gen Feng
  • Patent number: 10438997
    Abstract: The present invention is directed to a magnetic structure including a first seed layer, which is made of a first transition metal, formed on top of a second seed layer comprising cobalt, iron, and boron; and a magnetic fixed layer structure formed on top of the first seed layer and having a first invariable magnetization direction substantially perpendicular to a layer plane thereof. The magnetic fixed layer structure includes layers of a first magnetic material interleaved with layers of a second transition metal. The first transition metal may be chromium or iridium. The second transition metal may be nickel, platinum, palladium, or iridium. The second seed layer which comprises cobalt, iron, and boron, may have a noncrystalline structure. Moreover, the second seed layer may be non-magnetic or superparamagnetic. The magnetic structure may further includes a third seed layer, which may comprise tantalum, formed adjacent to the second seed layer opposite the first seed layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 8, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10431733
    Abstract: A perpendicular magnetic tunnel junction device (pMTJ) is provided that has a structure of a first heavy metal layer, a first thin dusting layer on the first heavy metal layer, a first CoFeB layer on the thin dusting layer, a MgO barrier layer on the first CoFeB layer, a second CoFeB layer on the MgO barrier layer, a second thin dusting layer on the CoFeB layer; and a second heavy metal layer on the thin dusting layer. The insertion of the thin dusting layer improves thermal stability of the pMTJ structure.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 1, 2019
    Assignee: THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Weigang Wang, Hamid Almasi
  • Patent number: 10431736
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata
  • Patent number: 10432144
    Abstract: A high-frequency phase-locked oscillation circuit having an extremely narrow peak width and a stable frequency so that a high-frequency wave that is oscillated by the MR element solves a problem of a large peak width of oscillation spectrum. The high-frequency phase-locked oscillation circuit includes a magnetoresistive element that oscillates a high-frequency wave with an oscillating frequency; a reference signal source that outputs a reference signal with a reference frequency; a phase-locked loop circuit having a phase comparator, a loop filter, and a frequency divider; an adder that adds a phase error signal output from the loop filter and a bias voltage for oscillating the high-frequency wave from the magnetoresistive element, and that inputs an added bias voltage to the magnetoresistive element; and a filter provided between the frequency divider and the magnetoresistive element.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 1, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Shingo Tamaru, Hitoshi Kubota, Akio Fukushima, Shinji Yuasa
  • Patent number: 10424723
    Abstract: A Magnetic Tunnel Junction (MTJ) device including pillar contacts coupling the free magnetic layer of cell pillars to a top contact. The pillar contacts are electrically isolated from one or more other portions of the cell pillar by one or more self-aligned sidewall insulators. The MTJ device further including one of a static magnetic compensation layer or an exchange spring layer in the cell pillar.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 24, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Thomas Boone, Pradeep Manandhar, Manfred Schabes, Bartlomiej Kardasz, Mustafa Pinarbasi
  • Patent number: 10418547
    Abstract: A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10410703
    Abstract: A magnetoresistance effect element includes a recording layer containing a ferromagnetic body, and including a first fixed and second magnetization regions having magnetization components fixed substantially in a direction antiparallel to the in-plane direction to each other, and a free magnetization region disposed between the first and second fixed magnetization regions and having a magnetization component invertible in the in-plane direction, a domain wall disposed between the first fixed magnetization region and the free magnetization region, and being movable within the free magnetization region, and a magnetic nanowire having a width of 40 nm or less. The thickness of the recording layer is 40 nm or less and at least half but no more than twofold the width of the magnetic nanowire. The element further includes a barrier layer disposed on the recording layer, and a reference layer disposed on the barrier layer and containing a ferromagnetic body.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 10, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shunsuke Fukami, Toru Iwabuchi, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10411069
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: September 10, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Patent number: 10395809
    Abstract: Embodiments of the inventive concepts provide a flat perpendicular magnetic layer having a low saturation magnetization and a perpendicular magnetization-type tunnel magnetoresistive element using the same. The perpendicular magnetic layer is a nitrogen-poor (Mn1?xGax)Ny layer (0<x?0.5 and 0<y<0.1) formed by providing nitrogen (N) into a MnGa alloy while adjusting a nitrogen amount. The perpendicular magnetic layer can be formed flat.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 27, 2019
    Assignees: Samsung Electronics Co., Ltd., National Institute for Materials Science
    Inventors: Shigeki Takahashi, Yoshiaki Sonobe, Hiroaki Sukegawa, Hwachol Lee, Kazuhiro Hono, Seiji Mitani, Jun Liu
  • Patent number: 10388865
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
  • Patent number: 10388862
    Abstract: A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10388856
    Abstract: Provided is a magnetoresistance effect element that that generates a high MR ratio at a lower RA than a TMR element using a material of a conventional tunnel barrier layer or MgAl2O4. The magnetoresistance effect element includes a laminate in which an underlayer, a first ferromagnetic metal layer, a tunnel harrier layer, and a second ferromagnetic metal layer are laminated in that order, wherein the underlayer is made of TiN, NbN, TaN, ZrN or mixed crystals thereof, and the tunnel barrier layer is made of a compound that has a spinel structure and expressed by composition formula (1) below: (1) AxIn2Oy, where A is the non-magnetic divalent cation and represents cations of one or more elements selected from the group consisting of magnesium and zinc, x represents a number satisfying 0<x?2, and y represents a number satisfying 0<y?4.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 20, 2019
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10388343
    Abstract: A magnetoresistive element includes: a first magnetic layer having a magnetization direction that is variable; a second magnetic layer having a magnetization direction that is invariable; a first non-magnetic layer provided between the first magnetic layer and the second magnetic layer; a third magnetic layer that fixes the magnetization direction of the second magnetic layer and that antiferromagnetically couples with the second magnetic layer; and a second non-magnetic layer provided between the second magnetic layer and the third magnetic layer. The second non-magnetic layer includes ruthenium (Ru) and a metal element.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadaaki Oikawa, Young Min Eeh, Kazuya Sawada, Kenichi Yoshino, Toshihiko Nagase, Daisuke Watanabe
  • Patent number: 10388853
    Abstract: A magnetic memory element for Magnetic Random Access Memory. The magnetic memory element has improved reference layer magnetic pinning and reduced dipole fringing field effect on the magnetic free layer. The magnetic memory element includes a magnetic reference layer having a pinned magnetization, a magnetic free layer having a switchable magnetization and a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. The magnetic reference layer is exchange coupled with a synthetic anti-ferromagnetic structure that includes a first multi-layer structure, a second multi-layer structure and a non-magnetic anti-parallel exchange coupling layer located between the first and second multi-layer structures. Each of the first and second multi-layer structures includes a plurality of bi-layers of Pt and Co, with the Pt being deposited first and located below the Co.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 20, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Bartlomiej Adam Kardasz, Jorge Vasquez, Georg Wolf, Mustafa Pinarbasi
  • Patent number: 10388347
    Abstract: Some embodiments are directed to a non-collinear magnetoresistive device, including a free layer; a fixed layer; and a non-magnetic layer disposed between the free layer and the fixed layer, wherein the fixed layer has an easy magnetization direction in an in-plane direction or in a perpendicular direction, the free layer satisfies at room temperature expressions (1) and (2) below: ERT?1.66×10?19 J??(1) V?5×104 nm3??(2) where ERT=(Ku1,eff+Ku2+Ku1,eff2/4Ku2)×V, Ku1,eff: an effective first-order anisotropy constant, Ku2: a second-order anisotropy constant, and V: a volume, and wherein the free layer is in a cone magnetization state.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 20, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Rie Matsumoto, Hiroko Arai, Shinji Yuasa, Hiroshi Imamura
  • Patent number: 10374149
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Patent number: 10374145
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10361362
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer made of a material comprising cobalt and formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an iridium layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the iridium layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 23, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Huadong Gan, Yiming Huai, Yuchen Zhou, Zihui Wang
  • Patent number: 10361361
    Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 23, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guohan Hu, Younghyun Kim, Daniel C. Worledge
  • Patent number: 10361032
    Abstract: A ceramic capacitor that has low ESL and is suitable to be built into a substrate includes a first external electrode including a first portion extending from a portion located on a first principal surface to a portion of a first end surface, a second portion extending from a portion located on a second principal surface to a portion of the first end surface, a third portion extending from a portion located on a first side surface to a portion of the first end surface, and a fourth portion extending from a portion located on a second side surface to a portion of the first end surface. The first external electrode includes an outermost layer that is a Cu plated layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasuyuki Shimada
  • Patent number: 10354707
    Abstract: A seed layer stack with a smooth top surface having a peak to peak film thickness variation of about 0.5 nm is formed by sputter depositing a second seed layer on a first seed layer that is Mg, MgN, or an alloy thereof where the second seed layer has a bond energy substantially greater than that of the first seed layer. The second seed layer may be Ta or NiCr. In some embodiments, an uppermost seed layer that is one or both of Ru and Cu is deposited on the second seed layer. Higher coercivity (Hc) and perpendicular magnetic anisotropy (Hk) is observed in an overlying ferromagnetic layer than when a prior art seed layer stack is employed. The first seed layer has a thickness from 2 to 20 Angstroms and has a resputtering rate about 2 to 40 times that of the second seed layer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 16, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Ruhang Ding, Min Li, Wenyu Chen
  • Patent number: 10354708
    Abstract: A storage device according to one embodiment of the present technology includes a magnetization fixed layer, an intermediate layer, and a storage layer. The magnetization fixed layer is configured to have magnetization in an orientation perpendicular to a film surface and a constant magnetization direction. The intermediate layer includes a non-magnetic body and is disposed on the magnetization fixed layer. The storage layer includes an outer circumferential portion and a center portion, is disposed to face the magnetization fixed layer with the intermediate layer sandwiched therebetween, and is configured to have a variable magnetization direction, the outer circumferential portion having magnetization in an orientation perpendicular to a film surface, the center portion being formed by being surrounded by the outer circumferential portion and having magnetization inclined from the orientation perpendicular to the film surface.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 16, 2019
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 10354739
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10354682
    Abstract: A data reader may have a magnetoresistive stack with a magnetically free layer decoupled from a first shield by a cap. The cap can have one or more sub-layers respectively configured with a thickness of 4 nm or less as measured parallel to a longitudinal axis of the magnetoresistive stack on an air bearing surface.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 16, 2019
    Assignee: Seagate Technology LLC
    Inventors: Liwen Tan, ZhiGuo Ge, Shaun E. McKinlay, Jae-Young Yi, Stacey C. Wakeham
  • Patent number: 10355045
    Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10355197
    Abstract: An integrated circuit includes a magnetic field sensor and an injection molded magnetic material enclosing at least a portion of the magnetic field sensor.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • Patent number: 10355044
    Abstract: A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. The depletion of the magnetic material enables crystallization of the depleted magnetic material through crystal structure propagation from a neighboring crystalline material, without interference from the now-enriched getter seed region. This promotes high tunnel magnetoresistance and high magnetic anisotropy strength. Also during formation, another diffusive species is transferred from a precursor oxide material to the getter seed region, due to a chemical affinity elicited by another getter species. The depletion of the oxide material enables lower electrical resistance and low damping in the cell structure. Methods of fabrication and semiconductor devices are also disclosed.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sumeet C. Pandey
  • Patent number: 10347691
    Abstract: The present invention is directed to a magnetic structure, which includes a magnetic fixed layer structure formed on top of a seed layer structure. The seed layer structure includes one or more layers of a first transition metal, which may be platinum, palladium, nickel, or iridium, interleaved with one or more layers of a second transition metal, which may be tantalum, titanium, vanadium, molybdenum, chromium, tungsten, zirconium, hafnium, or niobium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first magnetic material interleaved with layers of the first transition metal. The first magnetic material may be made of cobalt.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 9, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Bing K. Yen, Huadong Gan
  • Patent number: 10347828
    Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 9, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Patent number: 10347821
    Abstract: A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Lu, Junjing Bao, Xia Li, Seung Hyuk Kang
  • Patent number: 10347827
    Abstract: A method of making a spin-torque transfer magnetic random access memory device (STT MRAM) device includes forming a tunnel barrier layer on a reference layer; forming a free layer on the tunnel barrier layer, the free layer comprising a cobalt iron boron (CoFeB) alloy layer and an iron (Fe) layer; and performing a sputtering process to form a metal oxide layer on the Fe layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Guohan Hu
  • Patent number: 10347689
    Abstract: A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. The depletion of the magnetic material enables crystallization of the depleted magnetic material through crystal structure propagation from a neighboring crystalline material, without interference from the now-enriched getter seed region. This promotes high tunnel magnetoresistance and high magnetic anisotropy strength. Also during formation, another diffusive species is transferred from a precursor oxide material to the getter seed region, due to a chemical affinity elicited by another getter species. The depletion of the oxide material enables lower electrical resistance and low damping in the cell structure. Methods of fabrication and semiconductor devices are also disclosed.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sumeet C. Pandey
  • Patent number: 10347310
    Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data includes a fixed layer, a barrier layer, and a composite free layer. A barrier layer is disposed between a fixed layer and a composite free layer. A composite free layer includes an in-plane anisotropy free layer, a perpendicular magnetic anisotropy (PMA) inducing layer, and a ferromagnetic amorphous layer. A PMA-inducing layer may be disposed such that an in-plane anisotropy free layer is between a barrier layer and the PMA-inducing layer. A ferromagnetic amorphous layer may be disposed between an in-plane anisotropy free layer and a PMA-inducing layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Young-Suk Choi
  • Patent number: 10340442
    Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a magnetic material containing at least one element selected from a first group consisting of Mn, Fe, Co, and Ni; at least one element selected from a second group consisting of Ru, Rh, Pd, Ag, Os, Ir, Pt, and Au; and at least one element selected from a third group consisting of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 2, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoki Hase, Takao Ochiai, Tadaomi Daibou, Yushi Kato, Shumpei Omine, Junichi Ito
  • Patent number: 10340446
    Abstract: A semiconductor structure includes a seed layer and a multilayer stack of one or more multilayers disposed over the seed layer, each of the one or more multilayers including a magnetic layer and an additional layer disposed over a top surface of the magnetic layer. The additional layer includes a non-magnetic material and a dusting material. The multilayer stack provides a reference layer of a perpendicular magnetic tunnel junction stack. The magnetic layer may be formed of cobalt, the non-magnetic material may be at least one of iridium and rhodium, and the dusting material may be at least one of platinum, ruthenium, palladium, gold and nickel.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventor: Matthias Georg Gottwald
  • Patent number: 10340443
    Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Elijah V. Karpov, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Niloy Mukherjee, Prashant Majhi
  • Patent number: 10333058
    Abstract: The disclosed technology provides various implementations of a device based on a spin Hall effect (SHE) and spin transfer torque (STT) effect.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 25, 2019
    Assignee: Cornell University
    Inventors: Sriharsha V. Aradhya, Robert A. Buhrman, Daniel C. Ralph, Graham E. Rowlands
  • Patent number: 10333061
    Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventors: Ga-Young Ha, Ki-Seon Park, Jong-Han Shin
  • Patent number: 10325639
    Abstract: An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field is applied after a final anneal step is performed during memory device fabrication such that all magnetizations in the free layer, and AP1 and AP2 pinned layers are temporarily aligned “in-plane”. After the applied field is removed, interfacial perpendicular magnetic anisotropy (PMA) at a tunnel barrier/AP1 interface induces a single AP1 magnetic domain with a magnetization in a first vertical direction. Interfacial PMA at a FL/tunnel barrier interface affords a single FL domain with magnetization in the first direction or opposite thereto. AP2 magnetization is opposite to the first direction as a result of antiferromagnetic coupling with the AP1 layer. Alternatively, a perpendicular-to-plane magnetic field may be applied for initialization.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Jen Lee, Guenole Jan, Huanlong Liu, Jian Zhu
  • Patent number: 10319902
    Abstract: Some embodiments are directed to a magnetoresistive device, including a free layer having an easy magnetization direction in a perpendicular direction or in an in-plane direction; a fixed layer having the easy magnetization direction which is in the perpendicular direction when the easy magnetization direction of the free layer is in the perpendicular direction or in the in-plane direction when the easy magnetization direction of the free layer is in the in-plane direction; and a non-magnetic layer disposed between the free layer and the fixed layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 11, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Rie Matsumoto, Hiroko Arai, Shinji Yuasa, Hiroshi Imamura
  • Patent number: 10305025
    Abstract: A magnetic memory device including a first magnetic layer selectively exhibiting a first state in which the first magnetic layer has a first magnetization direction perpendicular to a main surface thereof and a second state in which the first magnetic layer has a second magnetization direction opposite to the first magnetization direction; a second magnetic layer having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the first magnetization direction, and having a top surface including a recess portion or a bottom surface including a recess portion; a third magnetic layer provided between the first magnetic layer and the second magnetic layer, and having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the second magnetization direction; and a nonmagnetic layer provided between the first magnetic layer and the third magnetic layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jyunichi Ozeki, Hiroyuki Ohtori, Kuniaki Sugiura, Yutaka Hashimoto, Katsuya Nishiyama
  • Patent number: 10304508
    Abstract: A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 28, 2019
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Satoshi Sugahara, Yota Takamura, Shigeki Nakagawa
  • Patent number: 10305027
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 28, 2019
    Assignees: Kabushiki Kaisha Toshiba, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yushi Kato, Tadaomi Daibou, Yuuzo Kamiguchi, Naoharu Shimomura, Junichi Ito, Hiroaki Sukegawa, Mohamed Belmoubarik, Po-Han Cheng, Seiji Mitani, Tadakatsu Ohkubo, Kazuhiro Hono
  • Patent number: 10302711
    Abstract: An article may include a substantially perpendicularly magnetized free layer having a first magnetic orientation in the absence of an applied magnetic field. The article may also include a spin Hall channel layer configured to conduct a spin current configured to subject the perpendicularly magnetized free layer to a magnetic switching torque and a substantially in-plane magnetized bias layer configured to bias the substantially perpendicularly magnetized free layer to a second magnetic orientation. The second magnetic orientation is different than the first magnetic orientation and is out of a plane of the substantially perpendicularly magnetized free layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 28, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: Jian-Ping Wang, Angeline Klemm Smith, Mahdi Jamali, Zhengyang Zhao
  • Patent number: 10297747
    Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 21, 2019
    Assignee: Everpsin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Moazzem Hossain
  • Patent number: 10297746
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel