Abstract: A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

Abstract: A memory device includes a first metal structure, a magnetic tunnel junction (MTJ) structure, a second metal structure, a first spacer, and a second spacer. The MTJ structure is over the first metal structure. The second metal structure is over the MTJ structure. The first spacer is over a first sidewall of the second metal structure. The second spacer is over a second sidewall of the second metal structure. The second spacer has a top surface higher than a top surface of the first spacer.

Abstract: The present disclosure provides a spin-orbit torque structure having a high spin Hall angle and low resistance by including a topological material. In addition, the present disclosure provides a spin-orbit torque structure having a low power consumption density by including a topological material. Also, a magnetic memory device including the spin-orbit torque structure is provided.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Abstract: The present disclosure generally relates to magnetoresistive (MR) devices. The MR device comprises a synthetic antiferromagnetic (SAF) layer that increases exchange coupling field, and in turn, less magnetic noise of such devices. The MR device comprises a first ferromagnetic (FM1) layer and a second ferromagnetic (FM2) layer, in between which is an SAF spacer of RuAl alloy having a B2 crystalline structure which may grow epitaxial on BCC (110) or FCC (111) textures, meaning that the (110) or (111) plane is parallel to the surface of MR device substrate. Further, amorphous layers may be inserted into the device structure to reset the growth texture of the device to a (001), (110), or (111) texture in order to promote the growth of tunneling barrier layers or antiferromagnetic (AF) pinning layers.

Abstract: A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.

Abstract: A magnetic memory device includes a conductive line that extends in a first direction, and a magnetic track line that extends in the first direction on a top surface of the conductive line. The conductive line may include a first region having a first width in a second direction, and a second region having a second width in the second direction. The first direction and the second direction are parallel to the top surface of the conductive line and are perpendicular to each other. The second width may be greater than the first width. The magnetic track line includes first domains arranged in the first direction on the first region of the conductive line, and second domains arranged in the first direction on the second region of the conductive line. A size of each of the second domains may be less than a size of each of the first domains.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to temperature sensors with programmable magnetic tunnel junction structures and methods of manufacture. A structure includes a resistor material connected in series with a programmable magnetic tunnel junction structure in a Wheatstone bridge configuration.

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.

Abstract: The present invention is directed to a perpendicular magnetic structure including a seed layer structure that includes a first seed layer comprising a metal element and oxygen; a second seed layer formed on top of the first seed layer and comprising cobalt, iron, and boron; and a third seed layer formed on top of the second seed layer and comprising chromium. The metal element is one of titanium, tantalum, or magnesium. The perpendicular magnetic structure further includes a magnetic fixed layer structure formed on top of the seed layer structure and having an invariable magnetization direction substantially perpendicular to a layer plane of the magnetic fixed layer structure. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The magnetic material includes cobalt. The transition metal is one of nickel, platinum, palladium, or iridium.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.

Abstract: A magnetic memory device may include a magnetic track, which is extended in a first direction, and a first electrode, which is provided at a biasing point of the magnetic track and is configured to apply a voltage to the magnetic track. The magnetic track includes a first region between a first end of the magnetic track and the biasing point and a second region between the biasing point and a second end of the magnetic track. The first electrode may be configured to cause a difference between a current density in the first region and a current density in the second region.

Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

Abstract: A top pinned SAF-containing magnetic tunnel junction structure is provided that contains a coupling spacer composed of a paramagnetic hexagonal metal phase material that has a stoichiometric ratio of Me3X or Me2X, wherein Me is a magnetic metal having a magnetic moment and X is a metal that alloys with Me in a hexagonal phase and dilutes the magnetic moment of Me. In embodiments in which a Me3X coupling spacer is present, Me is cobalt, and X is vanadium, niobium, tantalum, molybdenum or tungsten. In embodiments in which a Me2X coupling spacer is present, Me is iron and X is tantalum or tungsten. The coupling spacer is formed by providing a material stack including at least a precursor paramagnetic hexagonal metal phase material forming multilayered structure that includes alternating layers of magnetic metal, Me, and metal, X, and then thermally soaking the material stack.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

Abstract: A coil device capable of minimizing defects and increasing a thickness of a conductor pattern is provided. The coil device includes: a base substrate; a seed pattern formed on the base substrate and including a seed region and a lead-in wiring region; a first conductive pattern formed on the seed region; a second conductive pattern formed on at least a portion of the first conductive pattern; and a protective layer formed to contact at least one or more of the base substrate, the seed pattern, the first conductive pattern, and the second conductive pattern, in which the seed pattern of the lead-in wiring region extends to a cut line.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the resistive layer is greater than the transverse width of the bottom electrode metal layer and/or the top electrode metal layer, and the resistive layer has a variable resistance; an oxygen barrier layer located between the bottom electrode metal layer and the top electrode metal layer, where the oxygen barrier layer is located above the resistive layer; and an oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the oxygen grasping layer is less than the transverse width of the resistive layer.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetisation direction, a second magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, a third magnetic layer provided on a lower side of the first magnetic layer, the second magnetic layer and the nonmagnetic layer, having a fixed magnetization direction antiparallel to the magnetization direction of the second magnetic layer, and formed of an alloy of cobalt (Co) and platinum (Pt), and a buffer layer provided on a lower side of the third magnetic layer and including a first layer portion containing rhenium (Re).

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

Abstract: A piezoelectric element includes a substrate and a laminate which is provided on the substrate and which includes a first electrode, a seed layer, a piezoelectric layer, and a second electrode in this order, and the seed layer includes a composite oxide containing as a constituent element, lead, iron, and titanium.

Abstract: Provided are a magnetic tunneling junction device having more stable perpendicular magnetic anisotropy (PMA) and/or increased operating speed, and/or a memory device including the magnetic tunneling junction device. The magnetic tunneling junction device includes a free layer having a first surface and a second surface opposite the first surface; a pinned layer facing the first surface of the free layer; a first oxide layer between the pinned layer and the free layer; and a second oxide layer on the second surface of the free layer. The free layer includes a magnetic material X doped with a non-magnetic metal/ The second oxide layer includes ZOx which is an oxide of a metal Z. An oxygen affinity of the metal Z is greater than an oxygen affinity of the non-magnetic metal X.

Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.

Abstract: A cryogenic magnetic device includes a free layer having a free magnetisation and a magnetic anisotropy favouring the orientation of the free magnetisation according to a first orientation or a second orientation, the magnetic anisotropy being defined by an energy barrier separating the first orientation and the second orientation, the amplitude of the energy barrier being less than 6300 kB, the free layer having a Gilbert damping factor comprised between 0.02 and 0.4; a tunnel barrier extending in contact with the free layer; and a system configured to apply a voltage pulse through the tunnel barrier so as to reduce the amplitude of the energy barrier and switch the free magnetisation.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Abstract: A storage device includes: a memory unit and a first pillar. The first pillar includes: a first region having a third portion between a first and a second portion respectively having a first and a second maximum diameter, and having a first minimum diameter, the first and second portions defining a first distance; a second region having a sixth portion between a fourth and a fifth portion respectively having a third and a fourth maximum diameter, and having a second minimum diameter, the fourth and fifth portions defining a second distance; and a third region between the first and second regions, having a ninth portion between a seventh and an eighth portion respectively having a fifth and a sixth maximum diameter, and having a third minimum diameter, the seventh and eighth portions defining a third distance shorter than each of the first and second distances.

Abstract: The present disclosure provides a magnetic random-access memory cell, a memory and a device. The magnetic random-access memory cell comprises: a spin-orbit coupling layer and a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the spin-orbit coupling layer, the first magnetic tunnel junction and the second magnetic tunnel junction having at least two symmetrical axes with different lengths; an angle between an easy magnetization symmetrical axis direction of a free layer of the first magnetic tunnel junction and a length direction of the spin-orbit coupling layer is a preset first angle, and an angle between an easy magnetization symmetrical axis direction of a free layer of the second magnetic tunnel junction and the length direction of the spin-orbit coupling layer is a preset second angle; neither of the first angle and the second angle is zero degree, 90 degrees or 180 degrees.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including first and second magnetic layers each having a fixed magnetization direction, a third magnetic layer provided between the first and second magnetic layers, and having a variable magnetization direction, a first nonmagnetic layer between the first and third magnetic layers, and a second nonmagnetic layer between the second and third magnetic layers, and a switching element connected in series to the magnetoresistance effect element, changing from an electrically nonconductive state to an electrically conductive state when a voltage applied between two terminals is higher than or equal to a threshold voltage.

Abstract: A memory structure, i.e., magnetoresistive random access memory (MRAM) structure, is provided that includes a seeding area including at least a tunnel barrier seed layer located beneath a chemical templating layer that is wider than the magnetic tunnel junction (MTJ) structure that is located on the chemical templating layer. Redeposited metallic material is located on at least a sidewall of the tunnel barrier seed layer of the seeding area so as to shunt that area of the structure. The memory structure has reduced resistance with minimal tunnel magnetoresistance (TMR) loss penalty.

Abstract: A memristor may include an exchange-coupled composite (ECC) portion to provide three or more nonvolatile magneto-resistive states. The ECC portion may include a continuous layer and a granular layer magnetically exchange coupled to the continuous layer. A plurality of memristors may be used in a system to, for example, define a neural network.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device.

Abstract: A magnetic structure, a magnetic device incorporating the magnetic structure and a method for providing the magnetic structure are described. The magnetic structure includes a magnetic layer, a templating structure and a resistive insertion layer. The magnetic layer includes a Heusler compound and has a perpendicular magnetic anisotropy energy exceeding an out-of-plane demagnetization energy. The templating structure has a crystal structure configured to template at least one of the Heusler compound and the resistive insertion layer. The magnetic layer is on the templating structure. The resistive insertion layer is configured to reduce magnetic damping for the Heusler compound and allow for templating of the Heusler compound.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

Abstract: The present disclosure provides a semiconductor structure including a first electrode via, a first electrode on the first electrode via, a magnetic tunneling junction (MTJ) over the first electrode, a second electrode over the MTJ, a first dielectric layer on the first electrode via, a second dielectric layer on the first dielectric layer. The first dielectric layer is a planar layer. A sidewall of the MTJ is in contact with the second dielectric layer, and a bottom surface of the second dielectric layer is higher than a bottom surface of the first electrode.

Abstract: Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.