Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.

Abstract: There is provided a hall sensor. The hall sensor includes a hall element disposed on a semiconductor substrate. The hall element includes: a sensing region, a first electrode, a second electrode, a third electrode and a fourth electrode, and a doped region disposed on the sensing region, and the sensing region has at least one angulated corner or rounded corner.

Abstract: The vertical Hall element includes: a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate; a plurality of high-concentration second conductivity type electrodes formed in a straight line on a surface of the semiconductor layer having substantially the same shape, and spaced at a first interval; a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes to isolate the plurality of electrodes from one another having substantially the same shape, and spaced at a second interval; and a first added layer and a second added layer each formed along the straight line outside of the outermost electrodes, and each having substantially the same structure as that of each electrode isolation layer.

Abstract: In accordance with embodiments of the present disclosure, a memory system may include one or more memory modules and a memory controller communicatively coupled to one or more memory modules. The memory controller may be configured to determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The memory controller may also be configured to initiate one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature.

Abstract: A sensor arrangement according to an embodiment includes a board with a plurality of conductive lines of a first type, and a plurality of conductive lines of a second type different from the conductive lines of the first type, and a recess. The sensor arrangement further includes a plurality of sensor devices mechanically accommodated on a main surface of the board and arranged around the recess, each sensor device being electrically coupled to the conductive lines of the first type and at least to one of the conductive lines of the second type, wherein each conductive line of the second type electrically couples a sensor device with at least one other item different from the sensor devices of the plurality of sensor devices. A projection of the conductive lines of the first and second types perpendicular to the main surface is crossing-free. Each conductive line of the first type electrically couples at least all of the plurality of sensor devices.

Abstract: A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.

Abstract: Embodiments of the present invention provide a Hall effect device that includes a Hall effect region of a first semiconductive type, at least three contacts and a lateral conductive structure. The Hall effect region is formed in or on top of a substrate, wherein the substrate includes an isolation arrangement to isolate the Hall effect region in a lateral direction and in a depth direction from the substrate or other electronic devices in the substrate. The at least three contacts are arranged at a top of the Hall effect region to supply the Hall effect device with electric energy and to provide a Hall effect signal indicative of the magnetic field, wherein the Hall effect signal is generated in a portion of the Hall effect region defined by the at least three contacts. The lateral conductive structure is located between the Hall effect region and the isolation arrangement.

Abstract: A sensor wire count reduction system having various features is disclosed. Signals from multiple sensors may be combined together to reduce the number of wires implemented to convey the signals to a remote location. Multiple binary sensor outputs may be represented on a single wire as a multi-level signal, and may be decoded at a remote location.

Abstract: A magnetic field sensor includes a circular vertical Hall (CVH) sensing element and at least one planar Hall element. The CVH sensing element has contacts arranged over a common implant region in a substrate. In some embodiments, the at least one planar Hall element is formed as a circular planar Hall (CPH) sensing element also having contacts disposed over the common implant region. A CPH sensing element and a method of fabricating the CPH sensing element are separately described.

Abstract: A method and system for providing increased accuracy in a CMOS sensor system in one embodiment includes a plurality of sensor elements having a first terminal and a second terminal on a complementary metal oxide semiconductor substrate, a first plurality of switches configured to selectively connect the first terminal to a power source and to selectively connect the first terminal to a readout circuit, and a second plurality of switches configured to selectively connect the second terminal to the power source and to selectively connect the second terminal to the readout circuit.

Abstract: Vertical Hall device with highly conductive node for electrically connecting first and second Hall effect regions. A vertical Hall device comprises a first Hall effect region and a different second Hall effect region, both in a common semiconductor body. The first and second Hall effect regions have a main face and an opposite face, respectively. A highly conductive opposite face node is in ohmic contact to the opposite face of the first Hall effect region and the opposite face of the second Hall effect region in the semiconductor body. The vertical Hall device also comprises a first pair of contacts in or at the main face of the first Hall effect region and a second pair of contacts in or at the main face of the second Hall effect region. A convex circumscribing contour of the second pair of contacts is disjoint from a convex circumscribing contour of the first pair of contacts. Alternative embodiments comprise a pair of contacts and an opposite face node contact.

Abstract: The invention provides a Hall sensor element having a substrate, which has a main surface, having an electrically conductive active region, which extends from the main surface into the substrate, and having a first electrically conductive, buried layer in the substrate, which contacts the active region at a first lower contact surface. From another standpoint, the invention provides a method for measuring a magnetic field with the aid of such a Hall sensor element, in which an electrical measuring current is conducted through the active region between a first upper contact electrode at the main surface and the first lower contact surface. A Hall voltage is picked up in the active region along a path running inclined with respect to a connecting line between the first lower contact surface and the first upper contact electrode.

Abstract: Method of manufacturing sinterable electrical components for jointly sintering with active components, the components in planar shape being provided with at least one planar lower face meant for sintering, and an electrical contact area on the face opposite to the sintering face being available in the form of a metallic contact face, whose upper side is contactable by means of a commonly known method of the group: wire bonding or soldering or sintering or pressure contacting, the component being a temperature sensor, whose lower face is provided with a sinterable metallization on a ceramic body, said ceramic body having two electrical contact faces for continued electrical connection.

Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A magnetic field sensor having a support with a top side and a bottom side, whereby a Hall plate is provided on the top side of the support and the Hall plate comprises a carbon-containing layer.

Abstract: A method and structure for a three-axis magnetic field sensing device. An IC layer having first bond pads and second bond pads can be formed overlying a substrate/SOI member with a first, second, and third magnetic sensing element coupled the IC layer. One or more conductive cables can be formed to couple the first and second bond pads of the IC layer. A portion of the substrate member and IC layer can be removed to separate the first and second magnetic sensing elements on a first substrate member from the third sensing element on a second substrate member, and the third sensing element can be coupled to the side-wall of the first substrate member.

Abstract: A pressure sensor has a sensor body at least partly formed with an electrically insulating material, particularly a ceramic material, defining a cavity facing on which is a diaphragm provided with an electric detector element, configured for detecting a bending of the diaphragm. The sensor body supports a circuit arrangement, including, a plurality of circuit components, among which is an integrated circuit, for treating a signal generated by the detection element. The circuit arrangement includes tracks made of electrically conductive material directly deposited on a surface of the sensor body made of electrically insulating material. The integrated circuit is made up of a die made of semiconductor material directly bonded onto the surface of the sensor body and the die is connected to respective tracks by means of wire bonding, i.e. by means of thin connecting wires made of electrically conductive material.

Abstract: A method and structure for a three-axis magnetic field sensing device is provided. The device includes a substrate, an IC layer, and preferably three magnetic field sensors coupled to the IC layer. A nickel-iron magnetic field concentrator is also provided.

Abstract: A thermally stable Magnetic Tunnel Junction (MTJ) cell, and a memory device including the same, include a pinned layer having a pinned magnetization direction, a separation layer on the pinned layer, and a free layer on the separation layer and having a variable magnetization direction. The pinned layer and the free layer include a magnetic material having Perpendicular Magnetic Anisotropy (PMA). The free layer may include a central part and a marginal part on a periphery of the central part. The free layer is shaped in the form of a protrusion in which the central part is thicker than the marginal part.

Abstract: According to one embodiment, a magnetic memory element includes a stacked body including first and second stacked units stacked with each other. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer provided therebetween. The second stacked unit includes third and fourth ferromagnetic layers and a second nonmagnetic layer provided therebetween. Magnetization of the second and third ferromagnetic layers are variable. Magnetizations of the first and fourth ferromagnetic layers are fixed in a direction perpendicular to the layer surfaces. A cross-sectional area of the third ferromagnetic layer is smaller than a cross-sectional area of the first stacked unit when cut along a plane perpendicular to the stacking direction.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: A memory element includes a layered structure and a negative thermal expansion material layer. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a magnetic layer having a positive magnetostriction constant. The magnetization direction is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

Abstract: A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 ? to 400 ?. The MTJ cell structure can have a top conducting layer over the sacrifice layer.

Abstract: A semiconductor device includes a Hall element, which is switched between a first and second mode. In the first mode, connection A between a first and second resistor and connection C between a third and fourth resistor are set to Vcc or GND. Connection D between the first and fourth resistor and connection B between the second and third resistor are set as output terminals. In the second mode, D and B are set to Vcc or GND and A and C are set as output terminals. When a first line placed along the second resistor and connected to A is set at Vcc in the first mode, a second line placed along the fourth resistor and connected to D is set at Vcc in the second mode. When the first line is set at GND in first mode, the second line is set at GND in the second mode.

Abstract: A magnetic tunnel junction (MTJ) storage element may comprise a pinned layer stack and a first functional layer. The pinned layer stack is formed of a plurality of layers comprising a bottom pinned layer, a coupling layer, and a top pinned layer. The first functional layer is disposed in the bottom pinned layer or the top pinned layer.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A method and structure for a three-axis magnetic field sensing device is provided. The device includes a substrate, an IC layer, and preferably three magnetic field sensors coupled to the IC layer. A nickel-iron magnetic field concentrator is also provided.

Abstract: A solid-state imaging device includes a pixel array area in which an unit pixel including a photoelectric conversion element converting optical signals to signal charges and a transfer gate transferring the signal charges which have been photoelectrically converted in the photoelectric conversion element is two-dimensionally arranged in a matrix form, a supply voltage control means for supplying plural first control voltages sequentially to a control electrode of the transfer gate, and a driving means for performing driving of reading out signal charges transferred by the transfer gate when the plural first control voltages are sequentially applied twice and more.

Abstract: A vertical Hall sensor which is integrated in a semiconductor chip has at least 6 electric contacts which are arranged along a straight line on the surface of the semiconductor chip. The electric contacts are wired according to a predetermined rule, namely such that when the contacts are numbered through continuously and repeatedly with the numerals 1, 2, 3 and 4 starting from one of the two outermost contacts, the contacts to which the same numeral is assigned are electrically connected with each other.

Abstract: A semiconductor device includes a Hall element, which is switched between a first and second mode. In the first mode, connection A between a first and second resistor and connection C between a third and fourth resistor are set to Vcc or GND. Connection D between the first and fourth resistor and connection B between the second and third resistor are set as output terminals. In the second mode, D and B are set to Vcc or GND and A and C are set as output terminals. When a first line placed along the second resistor and connected to A is set at Vcc in the first mode, a second line placed along the fourth resistor and connected to D is set at Vcc in the second mode. When the first line is set at GND in first mode, the second line is set at GND in the second mode.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.

Abstract: A symmetrical vertical Hall element comprises a well of a first conductivity type that is embedded in a substrate of a second conductivity type and which is contacted by four contacts serving as current and voltage contacts. From the electrical point of view, such a Hall element with four contacts can be regarded as a resistance bridge formed by four resistors R1 to R4 of the Hall element. From the electrical point of view, the Hall element is then regarded as ideal when the four resistors R1 to R4 have the same value. The invention suggests a series of measures in order to electrically balance the resistance bridge. A first measure exists in providing at least one additional resistor. A second measure exists in locally increasing or reducing the electrical conductivity of the well. A third measure exists in providing two Hall elements that are electrically connected in parallel in such a way that their Hall voltages are equidirectional and their offset voltages are largely compensated.

Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.

Abstract: A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.

Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.

Abstract: A Hall sensor on a semiconductor substrate includes a Hall plate in the semiconductor substrate, where the Hall plate includes a first zone having a first conduction type. The semiconductor substrate also include a second zone having a second conduction type. A space-charge zone in the semiconductor substrate separates the first zone and the second zone, first contacts supply a control current to the first zone, and second contacts supply a compensation current to the second zone.

Abstract: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal layer. The multi-layered metal layer is formed by at least one metal layer, where the direction of the anisotropy axis of the antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged orthogonally. The provided memory has the advantage of lowering the switching field of the ferromagnetic layer, and further lowering the writing current.

Abstract: A vertical Hall effect apparatus, including methods thereof. A substrate layer can be provided upon which an epitaxial layer is formed. The epitaxial layer is surrounded vertically by one or more isolation layers. Additionally, an oxide layer can be formed above the epitaxial layer. A plurality of Hall effect elements can be formed within the epitaxial layer(s) and below the oxide layer, wherein the Hall effect elements sense the components of an arbitrary magnetic field in the plane of the wafer and perpendicular to the current flow in the hall element. A plurality of field plates can be formed above the oxide layer to control the inherited offset due to geometry control and processing of the vertical Hall effect apparatus, while preventing the formation of an output voltage of the vertical Hall effect apparatus at zero magnetic fields thereof.

Abstract: A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the groove and the groove is filled with copper and then planarized. The electrically conductive material is provided an upper surface that is recessed relative to the upper surface of the layer of insulating material. A cap, which can be conductive (e.g., Ta) or resistive (e.g., TiAIN), is disposed over the electrically conductive material and within the groove. A surface of the cap that faces away from the electrically conductive material, is formed with an elevation substantially equal to that of the edge of the liner, or the cap can extend over the liner edge. At least one layer of magneto-resistive material is disposed over a portion of the cap. Advantageously, the cap can protect the copper line from harmful etch processes required for etching a MRAM stack, while keeping the structure planar after CMP.

Abstract: In a method for fabricating a Bi thin film having a great MR (magnetoresistance) at room temperature and a method for fabricating a spintronics device using the same, the Bi thin film is fabricated by an electrodepostiting method and a sputtering method and has very great MR characteristics at room temperature, and it can be applied to various spintronics devices.

Abstract: A self aligned Hall sensor system and method are disclosed. A substrate can be provided. A Hall element and a plurality of contacts can then be formed upon the substrate wherein contacts are located in reference to one another. A field plate formed from polysilicon can then be formed upon the Hall element, wherein the field plate functions as a self-aligning mask for the plurality of contacts such that when the field plate is biased, a number of mobile carriers present at a surface of the field plate are minimized throughout the surface and up to and including the plurality of contacts, thereby minimizing asymmetry and offsets associated with the Hall element.

Abstract: A power generator. The power generator includes a first substrate, a second substrate, a magnetic film, a first metal layer, a second metal layer and an electricity storage device. The second substrate is disposed on the first substrate. A vibration chamber is formed between the first substrate and second substrate. The magnetic film is disposed between the first substrate and second substrate and located in the vibration chamber. The magnetic film has a predetermined magnetic field. The first metal layer is disposed under the first substrate and is aligned with the vibration chamber. The second metal layer is disposed on the second substrate and is aligned with the vibration chamber. The electricity storage device is electrically connected to the first metal layer and second metal layer.

Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

Abstract: A magnetic sensor device formed using SOI CMOS techniques includes a substrate, a silicon oxide layer and in some cases a plurality of gated regions. A first terminal is located between two innermost gated regions and supplies a supply voltage. A second and a third terminal, each of which is located between two adjacent gated regions other than the two innermost gated regions, output positive and negative Hall voltages. By appropriately controlling a bias voltage to the gated regions, small changes in a magnetic field induces larger currents in channel regions under the gated regions, which, in turn, results in detectable Hall voltages.

Abstract: This invention relates to an apparatus and methods for reducing the impedance mismatch problem encountered by differential signaling in conductive core substrates, while maintaining adherence to the common mode noise assumption. Specifically, the conductive paths that traverse through the conductive core are separated by a nonconductive material which minimize impedance and interruption of the signal coupling.

Abstract: A device for detecting a magnetic field, e.g., a magnetic field meter and an ammeter are described, the device having a first lateral magnetotransistor and a second lateral magnetotransistor, and in which the first and the second lateral magnetotransistors are complementary.

Abstract: A semiconductor magnetic sensor includes a semiconductor substrate, a source, a drain, a gate, and a carrier condensing means. The source and the drain are located in a surface of the substrate. One of the source and the drain includes adjoining two regions. The gate is located between the source and the drain for drawing minority carriers of the substrate to induce a channel, through which the carriers flow between the source and the drain to form a channel carrier current. The carriers flow into the two regions to form two regional carrier currents. The magnitude of a magnetic field where the sensor is placed is measured using the difference in quantity between the two regional carrier currents. The carrier condensing means locally increases carrier density in the channel carrier current in the proximity of an axis that passes between the two regions in order to increase the difference.

Abstract: A metrological Hall effect sensor with sensitivity to temperature less than 250 ppm/° C. and with high Hall effect coefficient for temperatures greater than 200° C. formed in a multilayer structure comprising a thin active layer deposited on a substrate, wherein the substrate is made of monocrystalline silicon carbide (SiC), and wherein the thin active layer is made of a weakly type n-doped silicon carbide (SiC) semiconductor in the exhaustion regime.