Abstract: A photodetector device includes an avalanche photodiode array substrate formed from compound semiconductor. A plurality of avalanche photodiodes arranged to operate in a Geiger mode are two-dimensionally arranged on the avalanche photodiode array substrate. A circuit substrate includes a plurality of output units which are connected to each other in parallel to form at least one channel. Each of the output units includes a passive quenching element and a capacitative element. The passive quenching element is connected in series to at least one of the plurality of avalanche photodiodes. The capacitative element is connected in series to at least one of the avalanche photodiodes and is connected in parallel to the passive quenching element.

Abstract: A semiconductor device and a semiconductor die are disclosed. The semiconductor device includes: a SPAD wafer containing SPAD dies formed thereon with respective SPAD arrays; a TDC wafer containing TDC dies formed thereon with respective TDC arrays; and a logic wafer containing logic dies formed thereon with respective peripheral logic circuits. The SPAD wafer, TDC wafer and logic wafer are bonded in the sequence set forth. The TDC arrays and peripheral logic circuits are arranged on the TDC and logic wafers, respectively, and the SPAD arrays are bonded to the TDC arrays. The three wafers are bonded and integrated together to form the semiconductor device using a multi-wafer stacking technique. The increased integration of the semiconductor device means an increased fill factor of SPAD arrays for same size, resulting in improved photon detection efficiency of the semiconductor device and improved detection performance of single-photon detectors fabricated from the semiconductor device.

Abstract: A semiconductor body comprises a buried layer of a first type of conductivity, a first region of the first type of conductivity, a shallow region of a second type of conductivity at a first surface of the semiconductor body, a sinker of the first type of conductivity located at the first surface of the semiconductor body, and a separating region of the first type of conductivity encircling at least one of the sinker and the buried layer. The first region is between the buried layer and the shallow region.

Abstract: A photodetector having a small form factor and having high detection efficiency with respect to both visible light and infrared rays may include a first electrode, a collector layer on the first electrode, a tunnel barrier layer on the collector layer, a graphene layer on the tunnel barrier layer, an emitter layer on the graphene layer, and a second electrode on the emitter layer. The photodetector may be included in an image sensor. An image sensor may include a substrate, an insulating layer on the substrate, and a plurality of photodetectors on the insulating layer. The photodetectors may be aligned with each other in a direction extending parallel or perpendicular to a top surface of the insulating layer. The photodetector may be included in a LiDAR system.

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

Abstract: This Application discloses methods for fabricating and packaging avalanche photodiodes (APDs), particularly useful for high sensitivity Geiger-mode APDs formed using an array of micro-cells. The photodetector is formed on a semiconductor wafer of indium phosphide (InP) having epitaxial layers, including indium gallium arsenide (InGaAs) as the photodetecting layer, with n-doped InP to one side, and layers of InP incorporating p-doped regions on the opposite side. The p-doped regions may be used to define the array of micro-cells. The photodetector is packaged by etching a well into the epitaxial structure on the semiconductor wafer, allowing an electrode to be patterned that contacts the n-doped InP layer and another that contacts the p-doped InP regions. Flip-chip bonding techniques can then attach the semiconductor wafer to a stronger support substrate, which may additionally be configured with electronic circuitry positioned to electrically contact the electrodes on the semiconductor wafer surface.

Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. The light scattering structures may include a low-index material formed in trenches in the semiconductor substrate. The light scattering structures may have different sizes and/or a layout with a non-uniform number of structures per unit area. SPAD devices may also include isolation structures in a ring around the SPADs to prevent crosstalk. The isolation structures may include metal-filled deep trench isolation structures. The metal filler may include tungsten.

Abstract: According to one embodiment, a light detector includes a plurality of elements. Each of the elements includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor region is located on the first semiconductor region and has a higher first-conductivity-type impurity concentration than the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The elements are arranged at a first period in a second direction crossing a first direction. The first direction is from the first semiconductor region toward the second semiconductor region. A quenching part is electrically connected with the third semiconductor region. Multiple lenses are located respectively on the elements. One of the lenses is positioned on one of the elements. A refracting layer is located between the elements and the lenses. The refracting layer has a first thickness.

Abstract: The present invention relates to a slot waveguide formed by a vertical material stack comprising a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si1-xGex pseudosubstrate layer with 0<x?1 and with a third refractive index. The center layer is grown on the Si1-xGex pseudosubstrate layer. The second refractive index is lower than the first refractive index and lower than the third refractive index. The slot waveguide can be included in a phase-shifter including two vertically arranged electrodes configured for providing a vertical electrical field (Ev) extending between the top layer and the bottom layer of the slot waveguide and for providing a complementary-metal-oxide-semiconductor compatible driver voltage. The phase-shifter can be configured for providing a linear electro-optical effect inside the center layer of the slot waveguide.

Abstract: A photodetector device includes a semiconductor material layer and at least one photodiode in the semiconductor material layer. The at least one photodiode is configured to be biased beyond a breakdown voltage thereof to generate respective electrical signals responsive to detection of incident photons. The respective electrical signals are independent of an optical power of the incident photons. A textured region is coupled to the semiconductor material layer and includes optical structures positioned to interact with the incident photons in the detection thereof by the at least one photodiode. Two or more photodiodes may define a pixel of the photodetector device, and the optical structures may be configured to direct the incident photons to any of the two or more photodiodes of the pixel.

Abstract: To reduce the influence of generation of after-pulses when a pixel including a SPAD is used. In a SPAD pixel, a PN junction part of a P+ type semiconductor layer and an N+ type semiconductor layer is formed, a P type semiconductor layer having a concentration higher than the concentration of a silicon substrate is formed in a region deeper than the PN junction part and close to a light absorption layer. With no quenching operation generating no after-pulse, electrons generated in the light absorption layer are guided to the PN junction part and subjected to avalanche amplification. When the quenching operation is performed after avalanche amplification, the electrons are guided to the N+ type semiconductor layer by a potential barrier to prevent avalanche amplification. The present disclosure is applicable to an image sensor including a SPAD.

Abstract: A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.

Abstract: A photodetector device includes an avalanche photodiode array substrate formed from compound semiconductor. A plurality of avalanche photodiodes arranged to operate in a Geiger mode are two-dimensionally arranged on the avalanche photodiode array substrate. A circuit substrate includes a plurality of output units which are connected to each other in parallel to form at least one channel. Each of the output units includes a passive quenching element and a capacitative element. The passive quenching element is connected in series to at least one of the plurality of avalanche photodiodes. The capacitative element is connected in series to at least one of the avalanche photodiodes and is connected in parallel to the passive quenching element.

Abstract: The present disclosure relates to a sensor chip and an electronic apparatus each of which enables carriers generated through photoelectric conversion to be efficiently used. At least one or more avalanche multiplication regions multiplying carriers generated through photoelectric conversion are provided in each of a plurality of pixel regions in a semiconductor substrate, and light incident on the semiconductor substrate is condensed by an on-chip lens. Then, a plurality of on-chip lenses is arranged in one pixel region. The present technology, for example, can be applied to a back-illuminated type CMOS image sensor.

Abstract: The present relates to a multi-junction photon detector comprising a semiconductor substrate, a plurality of n+ pixels on the top surface and a p+ uniform doping implant on the backside and at least one n-doped layer on the backside, deeper in the substrate bulk than the p+ implant, such that the detector presents a first PN junction corresponding to a drift and signal induction region and comprising the pixels on the substrate, and a second PN junction corresponding to a gain region and comprising the n-doped layer disposed on the backside of the detector active area deeper in the substrate bulk. These two junctions are operated in inverse polarization. The area between them contains a PN junction in direct polarization and it is fully depleted from the free charges.

Abstract: The present technology relates to a light detecting element and a method of manufacturing the same that make it possible to reduce pixel size. The light detecting element includes a plurality of pixels arranged in the form of a matrix. Each of the pixels includes a first semiconductor layer of a first conductivity type formed in an outer peripheral portion in the vicinity of a pixel boundary, and a second semiconductor layer of a second conductivity type opposite from the first conductivity type formed on the inside of the first semiconductor layer as viewed in plan. A high field region formed by the first semiconductor layer and the second semiconductor layer when a reverse bias voltage is applied is configured to be formed in a depth direction of a substrate. The present technology is, for example, applicable to a photon counter or the like.

Abstract: A solid-state imaging element including a photoelectric conversion layer of a first electrical conductivity type including a plurality of pixel regions, an electrode electrically coupled to the photoelectric conversion layer and provided for each of the pixel regions, a semiconductor layer provided between the electrode and the photoelectric conversion layer and having a bandgap larger than a bandgap of the photoelectric conversion layer, a diffusion part disposed in a vicinity of an edge of the pixel region and including an impurity of a second electrical conductivity type that is diffused from the semiconductor layer across the photoelectric conversion layer, and a non-diffusion part provided inside the diffusion part and not including the impurity of the second electrical conductivity type in the photoelectric conversion layer.

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. The light scattering structures may include a low-index material formed in trenches in the semiconductor substrate. The light scattering structures may have different sizes and/or a layout with a non-uniform number of structures per unit area. SPAD devices may also include isolation structures in a ring around the SPADs to prevent crosstalk. The isolation structures may include metal-filled deep trench isolation structures. The metal filler may include tungsten.

Abstract: A semiconductor light receiving element includes a first semiconductor layer, a waveguide type photodiode structure, an optical waveguide structure, and a fourth semiconductor layer. The waveguide type photodiode structure is provided on the first semiconductor layer. The waveguide type photodiode structure includes an optical absorption layer, a second semiconductor layer, a multiplication layer, and a third semiconductor layer. The optical waveguide structure is provided on the first semiconductor layer. The optical waveguide structure includes an optical waveguiding core layer and a cladding layer. An end face of the waveguide type photodiode structure faces to an end face of the optical waveguide structure. The fourth semiconductor layer is located between the end face of the waveguide type photodiode structure and the end face of the optical waveguide structure. The fourth semiconductor layer contacts the multiplication layer at the end face of the waveguide type photodiode structure.

Abstract: A photoelectric conversion device includes a photoelectric conversion region, a readout circuit, and a counting circuit. The photoelectric conversion region is configured to generate a signal charge. The readout circuit is configured to, when reading out a signal that is based on the signal charge generated at the photoelectric conversion region, selectively perform first readout for reading out the signal using avalanche multiplication that is based on the signal charge and second readout for reading out the signal without causing avalanche multiplication to occur with respect to at least a part of the signal charge. The counting circuit is configured to count a number of occurrences of avalanche current which is caused to occur by avalanche multiplication in the first readout.

Abstract: A photoelectric conversion apparatus includes an effective pixel circuit, a reference pixel circuit, a signal output unit, and a comparison unit. The effective pixel circuit includes a photoelectric conversion unit, and is configured to be controlled by using a control line and to output a digital signal based on electric charges generated by the photoelectric conversion unit. The reference pixel circuit includes a holding unit for holding the digital signal. The reference pixel circuit is configured to be controlled by using the control line together with the effective pixel circuit. The signal output unit is configured to output a signal to the holding unit so that a first digital signal with a predetermined value is held by the holding unit. The comparison unit is configured to compare the first signal with the digital signal output from the holding unit controlled to hold the first digital signal.

Abstract: A light receiving element array includes one or more unit element blocks. Each of the unit element blocks includes different light receiving elements with different element structures.

Abstract: A lateral interband Type II engineered (LITE) detector is provided. LITE detectors use engineered heterostructures to spatially separate electrons and holes into separate layers. The device may have two configurations, a positive intrinsic (PIN) configuration and a BJT (Bipolar junction transistor) configuration. The PIN configuration may have a wide bandgap (WBG) layer that transports the holes above a narrow bandgap (NBG) absorber layer that absorbs the target radiation and transports the electrons. The BJT configuration may have a WBG layer operating as a BJT above an NBG layer. In both configurations, the LITE design uses a Type II staggered offset between the NBG layers and the WBG layers that provides a built-in field for the holes to drift from an absorber region to a transporter region.

Abstract: According to an embodiment, a single photon detector configured to reduce a dark current comprises a buffer layer, a light absorption layer, a grading layer, an electric field control layer, and a window layer sequentially formed on a substrate. An active area may be formed in the window layer. A barrier junction may be formed through the window layer up to at least a portion of the light absorption layer, around the active area.

Abstract: A photodetecting device includes a semiconductor substrate, a plurality of avalanche photodiodes each having a light receiving region, the avalanche photodiodes being arranged in a matrix at the semiconductor substrate, and a plurality of through-electrodes electrically connected to corresponding light receiving regions. The plurality of through-electrodes are arranged for each area surrounded by four mutually adjacent avalanche photodiodes of the plurality of avalanche photodiodes. Each of the light receiving regions has, when viewed from a direction perpendicular to a first principal surface of the semiconductor substrate, a polygonal shape including a pair of first sides opposing each other in a row direction and extending in a column direction and four second side opposing four through-electrodes surrounding the light receiving region and extending in directions intersecting with the row direction and the column direction. The length of the first side is shorter than the length of the second side.

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

Abstract: A multiplication layer on a semiconductor substrate of n-type contains Al atoms. An electric field control layer on the multiplication layer is of p-type, and includes a high-concentration area, and a low-concentration area lower in impurity concentration than the high-concentration area which is formed outside the high-concentration area. An optical absorption layer on the electric field control layer is lower in impurity concentration than the high-concentration area. A window layer of n-type formed on the optical absorption layer is larger in band gap than the optical absorption layer. A light-receiving area of p-type is formed apart from an outer edge of the window layer, and at least partly faces the high-concentration area through the window layer and the optical absorption layer. The guard ring area of p-type which the window layer separates from the light-receiving area penetrates through the window layer to extend into the optical absorption layer.

Abstract: An avalanche photodiode including an absorption region, a collection region and a multiplication region between the absorption region and the collection region that performs a carrier multiplication by impact ionisation of a single type of carrier. The multiplication region includes a plurality of multilayer structures where each multilayer structure includes, from the absorption region to the collection region, an acceleration layer having a first energy band gap then a multiplication layer having a second energy band gap. The first energy band gap is greater than the second energy band gap.

Abstract: Devices, systems, and methods are provided for reducing electrical and optical crosstalk in photodiodes. A photodiode may include a first layer with passive material, the passive material having no electric field. The photodiode may include a second layer with an absorbing material, the second layer above the first layer. The photodiode may include a diffused region with a buried p-n junction. The photodiode may include an active region with the buried p-n junction and having an electric field greater than zero. The photodiode may include a plateau structure based on etching through the second layer to the first layer, the etching performed at a distance of fifteen microns or less from the buried p-n junction.

Abstract: A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.

Abstract: In an example, a photosensitive imaging surface is provided by an extended photodiode structure.

Abstract: Photoelectric conversion device includes semiconductor chip including first semiconductor region, second semiconductor region arranged on the first semiconductor region, and third semiconductor region arranged on the second semiconductor region. Chip end face of the semiconductor chip is formed by the first semiconductor region, the second semiconductor region and the third semiconductor region. The first semiconductor region is of first conductivity type and the second semiconductor region is of second conductivity type. The third semiconductor region includes photoelectric conversion region, readout circuit region, and peripheral region. The peripheral region includes isolation region and outer periphery region arranged between the chip end face and the isolation region. The isolation region is of the second conductivity type and the outer periphery region is of the first conductivity type.

Abstract: Disclosed herein is an apparatus suitable for radiation detection. The apparatus may comprise a radiation absorption layer and a first electrode on the radiation absorption layer. The radiation absorption layer may be configured to generate charge carriers therein from a radiation particle absorbed by the radiation absorption layer. The first electrode may be configured to generate an electric field in the radiation absorption layer. The first electrode may have a geometry shaping the electric field so that the electric field in an amplification region of the radiation absorption layer has a field strength sufficient to cause an avalanche of the charge carriers in the amplification region.

Abstract: A semiconductor device includes: a semiconductor substrate having a diode formation region; an upper diffusion region of a first conductivity type provided on a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a lower diffusion region of a second conductivity type provided at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region having a higher impurity concentration as compared to the semiconductor substrate. The lower diffusion region provides a PN joint surface with the upper diffusion region at a position deeper than the main surface, and has a maximum point indicating a maximum concentration in an impurity concentration profile of the lower diffusion region in the diode formation region.

Abstract: Systems and methods for a focused field avalanche photodiode (APD) may include an absorbing layer, an anode, a cathode, an N-doped layer, a P-doped layer, and a multiplication region between the N-doped layer and the P-doped layer. Oxide interfaces are located at top and bottom surfaces of the anode, cathode, N-doped layer, P-doped layer, and multiplication region. The APD may absorb an optical signal in the absorbing layer to generate carriers, and direct them to a center of the cathode using doping profiles in the N-doped layer and the P-doped layer that vary in a direction perpendicular to the top and bottom surfaces. The doping profiles in the N-doped layer and the P-doped layer may have a peak concentration midway between the oxide interfaces, or the N-doped layer may have a peak concentration midway between the oxide interfaces while the P-doped layer may have a minimum concentration there.

Abstract: To solve at least one of various problems in an image sensor in a 2PD scheme. A solid-state image pickup element includes a plurality of pixels each including a photoelectric conversion element formed on a silicon substrate, in which some pixels in the plurality of pixels each have the photoelectric conversion element partitioned by a first-type separating region extending in a plate shape in a direction along a thickness direction of the silicon substrate, and other pixels in the plurality of pixels each have the photoelectric conversion element partitioned by a second-type separating region formed with a material different from a material of the first-type separating region, the second-type separating region extending in a plate shape in the direction along the thickness direction of the silicon substrate.

Abstract: An imaging device including a first imaging cell having a variable sensitivity; and a first sensitivity control line electrically connected to the first imaging cell, where the first imaging cell comprises a photoelectron conversion area that generates a signal charge by incidence of light, and a signal detection circuit that detects the signal charge. The photoelectron conversion area includes a first electrode, a translucent second electrode connected to the first sensitivity control line, and a photoelectric conversion layer disposed between the first electrode and the second electrode, and during an exposure period from a reset of the first imaging cell until a readout of the signal charge accumulated in the first imaging cell by exposure, the first sensitivity control line supplies to the first imaging cell a first sensitivity control signal having a waveform expressed by a first function.

Abstract: A photodetecting device includes a semiconductor substrate including a first principal surface and a second principal surface that oppose each other and a plurality of through-electrodes penetrating through the semiconductor substrate in a thickness direction. The semiconductor substrate includes a plurality of avalanche photodiodes arranged to operate in Geiger mode. The plurality of through-electrodes are electrically connected to the corresponding avalanche photodiodes. The semiconductor substrate includes a first area in which the plurality of avalanche photodiodes are distributed in at least a first direction and a second area in which the plurality of through-electrodes are distributed two-dimensionally. The first area and the second area are distributed in a second direction orthogonal to a first direction when viewed from a direction orthogonal to the first principal surface.

Abstract: Methods and devices for an avalanche photo-transistor. In one aspect, an avalanche photo-transistor includes a detection region configured to absorb light incident on a first surface of the detection region and generate one or more charge carriers in response, a first terminal in electrical contact with the detection region and configured to bias the detection region, an interim doping region, a second terminal in electrical contact with the interim doping region and configured to bias the interim doping region, a multiplication region configured to receive the one or more charge carriers flowing from the interim doping region and generate one or more additional charge carriers in response, a third terminal in electrical contact with the multiplication region and configured to bias the multiplication region, wherein the interim doping region is located in between the detection region and the multiplication region.

Abstract: A solid-state image sensor comprises: a plurality of pixels each provided with a sensor unit that generates a pulse signal at a frequency corresponding to a frequency of reception of photons; a first counter that counts a number of pulses generated by the sensor unit; and an output unit that outputs a signal corresponding to a count value counted by the first counter in a case where change in the number of pulses detected per unit time is greater than a threshold.

Abstract: Provided is a photo-detection device including: a plurality of avalanche diodes; a quench element configured to suppress avalanche multiplication in the plurality of avalanche diodes; and a pixel signal processing unit configured to process a signal obtained by summing signals output from respective ones of the plurality of avalanche diodes. The quench element the number of which is one is connected to the plurality of avalanche diode in series.

Abstract: A method and apparatus for fabricating sensor chip assemblies. A photodetector wafer and an optics wafer are bonded to each other. Photodetectors are formed on the photodetector wafer. A circuit wafer is bonded to the photodetector wafer that is bonded to the optics wafer after forming the photodetectors on the photodetector wafer.

Abstract: In an embodiment, an image sensor includes a semiconductor substrate, an epitaxial layer disposed over the semiconductor substrate, a first heavily doped region disposed in the epitaxial layer, and a shallow trench isolation region disposed in the epitaxial layer and surrounding the first heavily doped region. The semiconductor substrate and the epitaxial layer are of a first doping type and the semiconductor substrate is coupled to a reference potential node. The first heavily doped region is of a second doping type opposite to the first doping type. The epitaxial layer, the first heavily doped region, and the shallow trench isolation region are part of a p-n junction photodiode configured to operate in the near ultraviolet region.

Abstract: Compact Single Photon Avalanche Diode (SPAD) array structures are described. An on board common trigger circuit is used for two or more SPAD structures. The common trigger includes a compact counter and flash memory constructed adjacent two or more SPAD structures. Triggering of a SPAD latches the value of the counter and the value is stored in the memory along with the ID of the triggering SPAD. The counter continues counting, and if another SPAD subsequently triggers, the counter is again latched and the value is stored in the memory along with the ID of the subsequently triggering SPAD. The memory can be read and the triggering circuit reset. Methods for designing compact SPAD structures, a compact active quenching circuit and a compact 16 bit counter are described.

Abstract: A SPAD-type photodiode including: a semiconductor substrate of a first conductive type having a front side and a back side; and a first semiconductor region of the second conductivity type extending in the substrate from the front side thereof and towards the back side thereof, the lateral surfaces of the first region being in contact with the substrate and the junction between the lateral surfaces of the first region and the substrate defining an avalanche area of the photodiode.

Abstract: A photodetector according to an embodiment includes: a first semiconductor layer; a porous semiconductor layer disposed on the first semiconductor layer; and at least one photo-sensing element including a second semiconductor layer of a first conductivity type disposed in a region of the porous semiconductor layer and a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer.

Abstract: A photodetection device including a diode array and a method for production thereof. In the device, each diode of the array includes an absorption region having a first bandgap energy and a collection region having a first doping type, and adjacent diodes in a network are separated by a trench including sides and a bottom. The bottom and sides of the trench form a stabilization layer having a second doping type, opposite the first doping type, and a bandgap energy greater than the first bandgap energy of the absorption regions.

Abstract: A structure of the avalanche photodiode type includes a first P doped semiconducting zone, a second multiplication semiconducting zone adapted to supply a multiplication that is preponderant for electrons, a fourth P doped semiconducting “collection” zone. One of the first and second semiconducting zones forms the absorption zone. The structure also includes a third semiconducting zone formed between the second semiconducting zone and the fourth semiconducting zone. The third semiconducting zone has an electric field in operation capable of supplying an acceleration of electrons between the second semiconducting zone and the fourth semiconducting zone without multiplication of carriers by impact ionisation.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.