Electromagnetic Or Particle Radiation Patents (Class 257/428)
  • Patent number: 12165952
    Abstract: A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shiang Liao, Chieh-Yen Chen, Chuei-Tang Wang
  • Patent number: 12154870
    Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Wei Hsieh, Kuo-Chang Kang
  • Patent number: 12117476
    Abstract: An apparatus for detecting a condition or authenticity of one or more electronic devices includes an enclosure having an antenna integrated therewithin, a fixture mounted within a hollow interior of the enclosure, the fixture being configured to receive the one or more electronic devices and connect one or more signals to each of the one or more electronic devices and a sensor and controller assembly connected to the antenna and configured to process a signature of an emission of a radiofrequency (RF) energy from of one or more electronic devices having the one or more signals connected thereto.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: October 15, 2024
    Assignee: Nokomis, Inc.
    Inventors: Walter J. Keller, III, Andrew Richard Portune, Todd Eric Chornenky, William Anthony Davis
  • Patent number: 12107107
    Abstract: A dark-current-inhibiting image sensor includes a semiconductor substrate, a thin and a thin junction. The semiconductor substrate includes a front surface, a back surface opposite the front surface, a photodiode, and a concave surface between the front surface and the back surface. The concave surface extends from the back surface toward the front surface, and defines a trench that surrounds the photodiode in a cross-sectional plane parallel to the back surface. The thin junction extends from the concave surface into the semiconductor substrate, and is a region of the semiconductor substrate. The semiconductor substrate includes a first substrate region, located between the thin junction and the photodiode, that has a first conductive type. The photodiode and the thin junction have a second conductive type opposite the first conductive type.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 1, 2024
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yifei Du, Zhiqiang Lin, Hui Zang, Seong Yeol Mun
  • Patent number: 12047691
    Abstract: An image sensor includes a pixel array including a plurality of pixels provided in a plurality of rows and a plurality of columns, and a signal processor configured to process first image data generated by the pixel array to generate a plurality of pieces of first full color image data, wherein the signal processor is further configured to split the first image data into a plurality of pieces of phase data, remosaic-process each of the plurality of pieces of phase data to generate a plurality of pieces of color phase data, merge the plurality of pieces of color phase data corresponding to a same color, respectively, to generate a plurality of pieces of preliminary color data, and compensate for the plurality of pieces of preliminary color data to generate the plurality of pieces of first full color image data.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: July 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanyoung Jang, Hee Kang, Seongwook Song
  • Patent number: 12021092
    Abstract: A flat panel detector substrate includes a base substrate, a photoelectric conversion layer, a bias signal line, and a conductive structure. The photoelectric conversion layer is located on the base substrate. The photoelectric conversion layer has a first surface proximate to the base substrate and a second surface away from the base substrate. The bias signal line is located between the photoelectric conversion layer and the base substrate. The conductive structure is located on the base substrate. One end of the conductive structure is coupled to the second surface of the photoelectric conversion layer, another end of the conductive structure is coupled to the bias signal line, and a portion therebetween is located beside the photoelectric conversion layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 25, 2024
    Assignees: BEIJING BOE SENSOR TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianxing Shang, Xuecheng Hou, Guan Zhang, Huinan Xia, Xiaobin Shang
  • Patent number: 11996373
    Abstract: A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 28, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, An-Ping Chien
  • Patent number: 11961809
    Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Patent number: 11935809
    Abstract: A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: March 19, 2024
    Assignee: NXP USA, INC.
    Inventors: Zhiwei Gong, Scott M. Hayes, Michael B. Vincent, Betty Hill-Shan Yeung, Rushik P. Tank, Kabir Mirpuri
  • Patent number: 11929333
    Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
  • Patent number: 11908815
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11863081
    Abstract: A single/Multi-phase PMIC built on silicon substrate with coil layers processed on top of the PMIC layers' is provided. The integrated coil is in a spiral form, with a gap at the center of the coil, making additional metal routing not required. The integrated coil has connection pads located in the center gap of the spiral form, limiting the overall inductor resistance to the device only. The on-die inductor may have a magnetic core wrapping the windings. The spiral form may be implemented in a circular design, or a racetrack (elongated spiral) design. The coil layers may be implemented as multiple coil layers or as a single coil layer, connected in parallel (with the same I/O pads), reducing the resistance and maintaining the inductance.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 2, 2024
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Santosh Kulkarni, Jens Masuch
  • Patent number: 11835391
    Abstract: A radiation detection device includes a plurality of field effect transistors (FETs) arranged to form a resonant cavity. The cavity includes a first end and a second end. The plurality of FETs provide an electromagnetic field defining an standing wave oscillating at a resonant frequency defined by a characteristic of the cavity. A radiation input passing through the cavity induces a perturbation of the electromagnetic field.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: December 5, 2023
    Assignee: TIMBRE TECHNOLOGIES, INC.
    Inventors: Saeed Assadi, James Pogge
  • Patent number: 11824020
    Abstract: An electronic device that has an antenna device that includes a conductive pattern layer comprising a first antenna element, the conductive pattern layer formed in an insulating substrate and adjacent to a first surface of the insulating substrate, and a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The electronic device further has a semiconductor package that includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer, a first electronic component electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first electronic component.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: November 21, 2023
    Assignee: MEDIATEK INC.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Tzu-Hung Lin
  • Patent number: 11791534
    Abstract: This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer; placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Tawian Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Patent number: 11721652
    Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11682629
    Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11675115
    Abstract: An optical device is provided. The optical device includes a substrate, a plurality of color filters and a plurality of spacers. The substrate has a central region and a peripheral region. The plurality of color filters include red color filters, green color filters and blue color filters and are formed on the substrate. The plurality of spacers are formed between the color filters. The refractive index of the spacers reduces gradually from that of the spacer located at the central region to that of the spacer located at the peripheral region of the substrate.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 13, 2023
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Kuo Feng, Chin-Chuan Hsieh
  • Patent number: 11658105
    Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 11569183
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Patent number: 11545426
    Abstract: The present disclosure provides a semiconductor device package including a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yi Chun Chou
  • Patent number: 11521919
    Abstract: The invention relates to a foil-based package with at least one foil substrate having an electrically conductive layer arranged thereon which is patterned to provide a first electrically conducting portion and a second electrically conducting portion, which is coplanar to the first electrically conducting portion, and a third electrically conducting portion, which is coplanar to the first electrically conducting portion, the first electrically conducting portion being arranged between the second and third electrically conducting portions. In accordance with the invention, the first electrically conducting portion is implemented to be a signal-guiding waveguide for high-frequency signals and the second electrically conducting portion, which is coplanar to the first electrically conducting portion, and the third electrically conducting portion, which is coplanar to the first electrically conducting portion, form an equipotential surface.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 6, 2022
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Robert Faul
  • Patent number: 11488915
    Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes a rewiring layer, wherein the rewiring layer comprises a first dielectric layer and a first metal wiring layer in the first dielectric layer; metal connecting column, formed on the first metal wiring layer of the rewiring layer; a packaging layer, disposed on the rewiring layer, an antenna metal layer, formed on the packaging layer, an antenna circuit chip, bonded to the first metal layer of the rewiring layer, and electrically connected to the antenna metal layer through the metal connecting column; and a metal bump, formed on the first metal wiring layer of the rewiring layer, to achieve electrical lead-out of the rewiring layer.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: November 1, 2022
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 11430825
    Abstract: An image capturing assembly includes an encapsulation layer, embedded with functional components. The top surface and bottom surface of the encapsulation layer expose the functional components. A through hole is formed in the encapsulation layer; and the functional components have soldering pads facing away from a bottom of the encapsulation layer. A photosensitive unit including a photosensitive chip and an optical filter is mounted on the photosensitive chip. The photosensitive chip is embedded in the through hole; the optical filter is outside the through hole; the top surface and bottom surface of the encapsulation layer expose the photosensitive chip; and the photosensitive chip includes soldering pads facing away from the bottom of the encapsulation layer. A redistribution layer structure is on the top side of the encapsulation layer and electrically connects the soldering pads of the photosensitive chip with the soldering pads of the functional components.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 30, 2022
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Da Chen, Mengbin Liu
  • Patent number: 11415713
    Abstract: A product includes a transparent scintillator material, a beta emitter material having an end-point energy of greater than 225 kiloelectron volts (keV), and a photovoltaic portion configured to convert light emitted by the scintillator material to electricity.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 16, 2022
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Joshua Jarrell, Nerine Cherepy, John Winter Murphy, Rebecca J. Nikolic, Erik Lars Swanberg, Jr.
  • Patent number: 11340398
    Abstract: A waveguide structure includes a first surface having a first width, a second surface having a second width, the second surface being opposite to the first surface, and a sidewall surface connecting the first surface and the second surface. The first width is greater than the second width.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 24, 2022
    Assignee: ARTILUX, INC.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Han-Din Liu, Chia-Peng Lin, Chung-Chih Lin, Yun-Chung Na, Pin-Tso Lin, Tsung-Ting Wu, Yu-Hsuan Liu, Kuan-Chen Chu
  • Patent number: 11315976
    Abstract: A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 26, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Takahiro Kawamura
  • Patent number: 11296254
    Abstract: A diode array is provided. The diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array, wherein each of the light emitting diodes includes a stack of functional layers comprising a first type semiconductor layer, a second type semiconductor layer, and a light emitting layer located between the first type semiconductor layer and the second type semiconductor layer, wherein at least one of the light emitting diodes includes: a first current limiting region abutting a vertically extending boundary of the second semiconductor layer; wherein, with respect to a top down view, the first current limiting region is formed about an outer edge of the light emitting diode and an outer perimeter of the first current limiting region is equal to or less than 400 micrometers (?m).
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 5, 2022
    Assignee: VISIONLABS CORPORATION
    Inventors: Hung-Cheng Lin, Hung-Kuang Hsu, Hua-Chen Hsu
  • Patent number: 11264521
    Abstract: A photosensitive field-effect transistor which can be configured to provide an electrical response when illuminated by electromagnetic radiation incident on the transistor. The field-effect transistor has a channel (13) made from a two-dimensional material and comprises a photoactive layer (22) which can be configured to donate charge carriers to the transistor channel (13) when electromagnetic radiation is absorbed in the photoactive layer (22). The photosensitive field-effect transistor comprises a top electrode (21) which is in contact with the photoactive layer on one or more contact areas which together form a contact pattern. With a suitably patterned top electrode (21), a voltage applied to the electrode can function as an electrical shutter which can switch the photosensitive field-effect transistor between a light-sensitive state and a light-immune state.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 1, 2022
    Assignee: EMBERION OY
    Inventors: Martti Voutilainen, Sami Kallioinen, Juha Rakkola
  • Patent number: 11245192
    Abstract: A chip antenna includes: a first dielectric layer; a second dielectric layer upwardly spaced apart from the first dielectric layer; a patch antenna pattern disposed on the second dielectric layer; a feed via extending through the first dielectric layer; a feed pattern disposed between the first and second dielectric layers, electrically connected to the feed via, and spaced apart from the patch antenna pattern; and an adhesive layer adhered to the first and second dielectric layers. The adhesive layer includes a cavity surrounding the feed pattern between the first and second dielectric layers and; and a vent disposed between the cavity and an external side surface of the adhesive layer.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: February 8, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dae Ki Lim, Young Sik Hur, Kyu Bum Han, Ju Hyoung Park, Myeong Woo Han, Jeong Ki Ryoo
  • Patent number: 11239266
    Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a plurality of second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. An insulating film includes a first insulating film covering surfaces of the second semiconductor regions, and a second insulating film covering peripheries of pad electrodes. The pad electrodes include a first electrode region in contact with the second region, and a second electrode region continuous with the first electrode region. The second electrode region is disposed on at least a part of a region included in the first insulating film and corresponding to the first region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 1, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Patent number: 11231381
    Abstract: Nanoparticle(NP)-decorated carbon nanotube (CNT) ropes used as sensing elements for hydrogen gas (H2) chemiresistors are described herein. The NP-decorated CNT rope sensors were prepared by dielectrophoretic deposition of a single semiconducting CNT rope followed by the electrodeposition of metal nanoparticles to highly disperse said nanoparticles on the CNT surfaces. The rope sensors produced a relative resistance change 20-30 times larger than what was observed at single, pure Pd nanowires. Thus, the rope sensors improved upon all H2 sensing metrics (speed, dynamic range, and limit-of-detection) relative to single Pd nanowires.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 25, 2022
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Reginald M. Penner, Xiaowei Li
  • Patent number: 11209318
    Abstract: A radiation detection device includes a plurality of field effect transistors (FETs) arranged to form a resonant cavity. The cavity includes a first end and a second end. The plurality of FETs provide an electromagnetic field defining an standing wave oscillating at a resonant frequency defined by a characteristic of the cavity. A radiation input passing through the cavity induces a perturbation of the electromagnetic field.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: December 28, 2021
    Assignee: Timbre Technologies, Inc.
    Inventors: Saeed Assadi, James Pogge
  • Patent number: 11205627
    Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: December 21, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Wei Hsieh, Kuo-Chang Kang
  • Patent number: 11204283
    Abstract: A cavity blackbody radiation source is provide. A cavity blackbody radiation source comprises a blackbody radiation cavity and a carbon nanotube layer. The blackbody radiation cavity comprises an inner surface. The carbon nanotube layer is located on the inner surface. The carbon nanotube carbon nanotube layer comprises a plurality of carbon nanotubes and a plurality of microporous. A method of making the cavity blackbody radiation source is also provide.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 21, 2021
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Guang Wang, Shou-Shan Fan
  • Patent number: 11127880
    Abstract: An optoelectronic semiconductor device and a method for producing an optoelectronic semiconductor device are disclosed. In an embodiment an optoelectronic semiconductor device includes a semiconductor body having a first region of a first conductivity type, an active region configured to generate electromagnetic radiation and a second region of a second conductivity type in a stacking direction, an electrical contact metallization arranged on a side of the second region facing away from the active region and being opaque to the electromagnetic radiation, a radiation coupling-out region surrounding the electrical contact metallization at an edge side and an absorber layer structure arranged between the electrical contact metallization and the second region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 21, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Johannes Unger, Franz Eberhard, Fabian Kopp, Katharina Christoph
  • Patent number: 11125626
    Abstract: A cavity black body radiation source is provided. The cavity black body radiation source comprises a blackbody radiation cavity, a black lacquer, and a carbon nanotube layer. The blackbody radiation cavity comprises an inner surface. The black lacquer is located on the inner surface. The carbon nanotube layer is located on a surface of the black lacquer away from the blackbody radiation cavity. The carbon nanotube layer comprises a plurality of carbon nanotubes and a plurality of microporous. A method of making the cavity blackbody radiation source is also provided.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 21, 2021
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Guang Wang, Shou-Shan Fan
  • Patent number: 11114391
    Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes a rewiring layer, wherein the rewiring layer comprises a first dielectric layer and a first metal wiring layer in the first dielectric layer; metal connecting column, formed on the first metal wiring layer of the rewiring layer; a packaging layer, disposed on the rewiring layer, an antenna metal layer, formed on the packaging layer, an antenna circuit chip, bonded to the first metal layer of the rewiring layer, and electrically connected to the antenna metal layer through the metal connecting column; and a metal bump, formed on the first metal wiring layer of the rewiring layer, to achieve electrical lead-out of the rewiring layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 7, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 11114745
    Abstract: This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer, placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Wen-Shiang Liao
  • Patent number: 11082550
    Abstract: A capacitive proximity sensor for use in mobile devices such as smartphones and connected tables, in which it is used to switch off a display (70) when the device is brought to the ear, and to reduce selectively the RF power when the device is in close proximity to a body part of a user, in order to fulfil regulatory SAR limits. The capacitive sensor uses two electrodes (60, 30), the first of which may also serve as RF antenna, and the other is preferably on the back of the phone and is opposite the display.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: August 3, 2021
    Assignee: Semtech Corporation
    Inventors: Chaouki Rouaissia, Hehai Zheng
  • Patent number: 11004810
    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
    Type: Grant
    Filed: December 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
  • Patent number: 11004799
    Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10989749
    Abstract: An apparatus for detecting a condition or authenticity of one or more electronic devices includes an enclosure having an antenna integrated therewithin, a fixture mounted within a hollow interior of the enclosure, the fixture being configured to receive the one or more electronic devices and connect one or more signals to each of the one or more electronic devices and a sensor and controller assembly connected to the antenna and configured to process a signature of an emission of a radiofrequency (RF) energy from of one or more electronic devices having the one or more signals connected thereto.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 27, 2021
    Assignee: NOKOMIS, INC.
    Inventors: Walter John Keller, III, Andrew Richard Portune, Todd Eric Chornenky, William Anthony Davis
  • Patent number: 10983010
    Abstract: The present disclosure is an infrared sensor capable of being integrated into a IR focal plane array. It includes of a CMOS based readout circuit with preamplification, noise filtering, and row/column address control. Using either a microbolometer device structure with either a thermal sensing element of vanadium oxide or amorphous silicon, a nanocomposite is fabricated on top of either of these materials comprising aligned or unaligned carbon nanotube films with IR transmissive layer of silicon nitride followed by one to five monolayers of graphene. These layers are connected in series minimizing the noise sources and enhancing the NEDT of each film. The resulting IR sensor is capable of NEDT of less than 1 mK. The wavelength response is from 2 to 12 microns. The approach is low cost using a process that takes advantage of the economies of scale of wafer level CMOS.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 20, 2021
    Assignee: Magnolia Optical Technologies, Inc.
    Inventors: Ashok K. Sood, Elwood J. Egerton
  • Patent number: 10971825
    Abstract: An antenna module includes: an integrated circuit (IC) configured to generate a radio frequency (RF) signal; and a substrate including an antenna portion providing a first surface of the substrate, and a circuit pattern portion providing a second surface of the substrate. The antenna portion includes first antenna members configured to transmit the RF signal, cavities corresponding to the first antenna members, through vias respectively disposed in the cavities and respectively electrically connected to the first antenna members, and a plating member disposed in at least one cavity among the cavities. The circuit pattern portion includes a circuit pattern and an insulating layer forming, for each of the through vias, an electrical connection path to the IC.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 6, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ho Kyung Kang, ThomasA Kim
  • Patent number: 10964652
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit layer, a first package body, a first antenna and an electronic component. The circuit layer has a first surface and a second surface opposite to the first surface. The first package body is disposed on the first surface of the circuit layer. The first antenna penetrates the first package body and is electrically connected to the circuit layer. The electronic component is disposed on the second surface of the circuit layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh
  • Patent number: 10867939
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
  • Patent number: 10804171
    Abstract: Disclosed in the present invention are a sensor packaging structure and a manufacturing method thereof. The sensor packaging structure includes a protection board, a circuit structure and a filling structure. A front surface of the circuit structure is connected to a first surface of the protection board. A second surface of the protection board is used as a sensing function surface. The filling structure is located on the outer periphery of the circuit structure and connected to the first surface of the protection board. The sensor packaging structure of the present invention uses the protection board as a protection layer of the functional circuit, which can effectively protect the functional circuit of the sensor. Meanwhile, the protection board is first connected to the circuit structure in the manufacturing method to avoid tolerance accumulation, increasing the manufacturing accuracy of the protection layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 13, 2020
    Assignee: MICROARRAY MICROELECTRONICS CORP., LTD.
    Inventors: Yangyuan Li, Shaobo Ding
  • Patent number: 10797195
    Abstract: The invention relates to semiconductor devices for converting ionizing radiation into an electrical signal. The present ionizing radiation sensor has an n+-i-p+ structure, produced using the planar process. The sensor contains an i-region in the form of a high-resistivity substrate of high-purity float-zone silicon with p-type conductivity, having on its front face n+-regions (2, 3), an SiO2 layer (4), aluminium metallization (5), and a passivation layer. On the front face of the substrate (1) n-regions (2) are formed by ion implantation; a masking layer of SiO2 (layer 4) is grown; aluminium metallization (5) is deposited; and a passivation layer (6) is applied.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 6, 2020
    Inventors: Vladimir Aleksandrovich Elin, Mikhail Moiseevich Merkin
  • Patent number: 10797100
    Abstract: An imaging device includes a semiconductor substrate, pixels, a charge detector, charge storage portions, an output gate portion and a shift gate portion. The pixels and the charge detector are provided in the semiconductor substrate. The charge storage portions are provided on the charge detector side of the pixels, and linked to the pixels. The output gate portion is positioned between the charge detector and the charge storage portions, and includes charge transfer channels extending in a radial configuration in directions from the charge detector toward the pixels. The shift gate portion is positioned between one charge storage portion and one charge transfer channel. The shift gate portion includes a gate electrode provided on the semiconductor substrate. A planar configuration of the gate electrode has a side orthogonal to the extending direction of the one charge transfer channels, the side being most proximal to the one charge transfer channel.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 6, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Ryuta Inobe