Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Abstract: A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.

Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A single/Multi-phase PMIC built on silicon substrate with coil layers processed on top of the PMIC layers' is provided. The integrated coil is in a spiral form, with a gap at the center of the coil, making additional metal routing not required. The integrated coil has connection pads located in the center gap of the spiral form, limiting the overall inductor resistance to the device only. The on-die inductor may have a magnetic core wrapping the windings. The spiral form may be implemented in a circular design, or a racetrack (elongated spiral) design. The coil layers may be implemented as multiple coil layers or as a single coil layer, connected in parallel (with the same I/O pads), reducing the resistance and maintaining the inductance.

Abstract: A radiation detection device includes a plurality of field effect transistors (FETs) arranged to form a resonant cavity. The cavity includes a first end and a second end. The plurality of FETs provide an electromagnetic field defining an standing wave oscillating at a resonant frequency defined by a characteristic of the cavity. A radiation input passing through the cavity induces a perturbation of the electromagnetic field.

Abstract: An electronic device that has an antenna device that includes a conductive pattern layer comprising a first antenna element, the conductive pattern layer formed in an insulating substrate and adjacent to a first surface of the insulating substrate, and a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The electronic device further has a semiconductor package that includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer, a first electronic component electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first electronic component.

Abstract: This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer; placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die.

Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: An optical device is provided. The optical device includes a substrate, a plurality of color filters and a plurality of spacers. The substrate has a central region and a peripheral region. The plurality of color filters include red color filters, green color filters and blue color filters and are formed on the substrate. The plurality of spacers are formed between the color filters. The refractive index of the spacers reduces gradually from that of the spacer located at the central region to that of the spacer located at the peripheral region of the substrate.

Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: The present disclosure provides a semiconductor device package including a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction.

Abstract: The invention relates to a foil-based package with at least one foil substrate having an electrically conductive layer arranged thereon which is patterned to provide a first electrically conducting portion and a second electrically conducting portion, which is coplanar to the first electrically conducting portion, and a third electrically conducting portion, which is coplanar to the first electrically conducting portion, the first electrically conducting portion being arranged between the second and third electrically conducting portions. In accordance with the invention, the first electrically conducting portion is implemented to be a signal-guiding waveguide for high-frequency signals and the second electrically conducting portion, which is coplanar to the first electrically conducting portion, and the third electrically conducting portion, which is coplanar to the first electrically conducting portion, form an equipotential surface.

Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes a rewiring layer, wherein the rewiring layer comprises a first dielectric layer and a first metal wiring layer in the first dielectric layer; metal connecting column, formed on the first metal wiring layer of the rewiring layer; a packaging layer, disposed on the rewiring layer, an antenna metal layer, formed on the packaging layer, an antenna circuit chip, bonded to the first metal layer of the rewiring layer, and electrically connected to the antenna metal layer through the metal connecting column; and a metal bump, formed on the first metal wiring layer of the rewiring layer, to achieve electrical lead-out of the rewiring layer.

Abstract: An image capturing assembly includes an encapsulation layer, embedded with functional components. The top surface and bottom surface of the encapsulation layer expose the functional components. A through hole is formed in the encapsulation layer; and the functional components have soldering pads facing away from a bottom of the encapsulation layer. A photosensitive unit including a photosensitive chip and an optical filter is mounted on the photosensitive chip. The photosensitive chip is embedded in the through hole; the optical filter is outside the through hole; the top surface and bottom surface of the encapsulation layer expose the photosensitive chip; and the photosensitive chip includes soldering pads facing away from the bottom of the encapsulation layer. A redistribution layer structure is on the top side of the encapsulation layer and electrically connects the soldering pads of the photosensitive chip with the soldering pads of the functional components.

Abstract: A product includes a transparent scintillator material, a beta emitter material having an end-point energy of greater than 225 kiloelectron volts (keV), and a photovoltaic portion configured to convert light emitted by the scintillator material to electricity.

Abstract: A waveguide structure includes a first surface having a first width, a second surface having a second width, the second surface being opposite to the first surface, and a sidewall surface connecting the first surface and the second surface. The first width is greater than the second width.

Abstract: A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.

Abstract: A diode array is provided. The diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array, wherein each of the light emitting diodes includes a stack of functional layers comprising a first type semiconductor layer, a second type semiconductor layer, and a light emitting layer located between the first type semiconductor layer and the second type semiconductor layer, wherein at least one of the light emitting diodes includes: a first current limiting region abutting a vertically extending boundary of the second semiconductor layer; wherein, with respect to a top down view, the first current limiting region is formed about an outer edge of the light emitting diode and an outer perimeter of the first current limiting region is equal to or less than 400 micrometers (?m).

Abstract: A photosensitive field-effect transistor which can be configured to provide an electrical response when illuminated by electromagnetic radiation incident on the transistor. The field-effect transistor has a channel (13) made from a two-dimensional material and comprises a photoactive layer (22) which can be configured to donate charge carriers to the transistor channel (13) when electromagnetic radiation is absorbed in the photoactive layer (22). The photosensitive field-effect transistor comprises a top electrode (21) which is in contact with the photoactive layer on one or more contact areas which together form a contact pattern. With a suitably patterned top electrode (21), a voltage applied to the electrode can function as an electrical shutter which can switch the photosensitive field-effect transistor between a light-sensitive state and a light-immune state.

Abstract: A chip antenna includes: a first dielectric layer; a second dielectric layer upwardly spaced apart from the first dielectric layer; a patch antenna pattern disposed on the second dielectric layer; a feed via extending through the first dielectric layer; a feed pattern disposed between the first and second dielectric layers, electrically connected to the feed via, and spaced apart from the patch antenna pattern; and an adhesive layer adhered to the first and second dielectric layers. The adhesive layer includes a cavity surrounding the feed pattern between the first and second dielectric layers and; and a vent disposed between the cavity and an external side surface of the adhesive layer.

Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a plurality of second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. An insulating film includes a first insulating film covering surfaces of the second semiconductor regions, and a second insulating film covering peripheries of pad electrodes. The pad electrodes include a first electrode region in contact with the second region, and a second electrode region continuous with the first electrode region. The second electrode region is disposed on at least a part of a region included in the first insulating film and corresponding to the first region. The first main surface is a light incident surface of the semiconductor substrate.

Abstract: Nanoparticle(NP)-decorated carbon nanotube (CNT) ropes used as sensing elements for hydrogen gas (H2) chemiresistors are described herein. The NP-decorated CNT rope sensors were prepared by dielectrophoretic deposition of a single semiconducting CNT rope followed by the electrodeposition of metal nanoparticles to highly disperse said nanoparticles on the CNT surfaces. The rope sensors produced a relative resistance change 20-30 times larger than what was observed at single, pure Pd nanowires. Thus, the rope sensors improved upon all H2 sensing metrics (speed, dynamic range, and limit-of-detection) relative to single Pd nanowires.

Abstract: A radiation detection device includes a plurality of field effect transistors (FETs) arranged to form a resonant cavity. The cavity includes a first end and a second end. The plurality of FETs provide an electromagnetic field defining an standing wave oscillating at a resonant frequency defined by a characteristic of the cavity. A radiation input passing through the cavity induces a perturbation of the electromagnetic field.

Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.

Abstract: A cavity blackbody radiation source is provide. A cavity blackbody radiation source comprises a blackbody radiation cavity and a carbon nanotube layer. The blackbody radiation cavity comprises an inner surface. The carbon nanotube layer is located on the inner surface. The carbon nanotube carbon nanotube layer comprises a plurality of carbon nanotubes and a plurality of microporous. A method of making the cavity blackbody radiation source is also provide.

Abstract: A cavity black body radiation source is provided. The cavity black body radiation source comprises a blackbody radiation cavity, a black lacquer, and a carbon nanotube layer. The blackbody radiation cavity comprises an inner surface. The black lacquer is located on the inner surface. The carbon nanotube layer is located on a surface of the black lacquer away from the blackbody radiation cavity. The carbon nanotube layer comprises a plurality of carbon nanotubes and a plurality of microporous. A method of making the cavity blackbody radiation source is also provided.

Abstract: An optoelectronic semiconductor device and a method for producing an optoelectronic semiconductor device are disclosed. In an embodiment an optoelectronic semiconductor device includes a semiconductor body having a first region of a first conductivity type, an active region configured to generate electromagnetic radiation and a second region of a second conductivity type in a stacking direction, an electrical contact metallization arranged on a side of the second region facing away from the active region and being opaque to the electromagnetic radiation, a radiation coupling-out region surrounding the electrical contact metallization at an edge side and an absorber layer structure arranged between the electrical contact metallization and the second region.

Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes a rewiring layer, wherein the rewiring layer comprises a first dielectric layer and a first metal wiring layer in the first dielectric layer; metal connecting column, formed on the first metal wiring layer of the rewiring layer; a packaging layer, disposed on the rewiring layer, an antenna metal layer, formed on the packaging layer, an antenna circuit chip, bonded to the first metal layer of the rewiring layer, and electrically connected to the antenna metal layer through the metal connecting column; and a metal bump, formed on the first metal wiring layer of the rewiring layer, to achieve electrical lead-out of the rewiring layer.

Abstract: This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer, placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die.

Abstract: A capacitive proximity sensor for use in mobile devices such as smartphones and connected tables, in which it is used to switch off a display (70) when the device is brought to the ear, and to reduce selectively the RF power when the device is in close proximity to a body part of a user, in order to fulfil regulatory SAR limits. The capacitive sensor uses two electrodes (60, 30), the first of which may also serve as RF antenna, and the other is preferably on the back of the phone and is opposite the display.

Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: An apparatus for detecting a condition or authenticity of one or more electronic devices includes an enclosure having an antenna integrated therewithin, a fixture mounted within a hollow interior of the enclosure, the fixture being configured to receive the one or more electronic devices and connect one or more signals to each of the one or more electronic devices and a sensor and controller assembly connected to the antenna and configured to process a signature of an emission of a radiofrequency (RF) energy from of one or more electronic devices having the one or more signals connected thereto.

Abstract: The present disclosure is an infrared sensor capable of being integrated into a IR focal plane array. It includes of a CMOS based readout circuit with preamplification, noise filtering, and row/column address control. Using either a microbolometer device structure with either a thermal sensing element of vanadium oxide or amorphous silicon, a nanocomposite is fabricated on top of either of these materials comprising aligned or unaligned carbon nanotube films with IR transmissive layer of silicon nitride followed by one to five monolayers of graphene. These layers are connected in series minimizing the noise sources and enhancing the NEDT of each film. The resulting IR sensor is capable of NEDT of less than 1 mK. The wavelength response is from 2 to 12 microns. The approach is low cost using a process that takes advantage of the economies of scale of wafer level CMOS.

Abstract: An antenna module includes: an integrated circuit (IC) configured to generate a radio frequency (RF) signal; and a substrate including an antenna portion providing a first surface of the substrate, and a circuit pattern portion providing a second surface of the substrate. The antenna portion includes first antenna members configured to transmit the RF signal, cavities corresponding to the first antenna members, through vias respectively disposed in the cavities and respectively electrically connected to the first antenna members, and a plating member disposed in at least one cavity among the cavities. The circuit pattern portion includes a circuit pattern and an insulating layer forming, for each of the through vias, an electrical connection path to the IC.

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit layer, a first package body, a first antenna and an electronic component. The circuit layer has a first surface and a second surface opposite to the first surface. The first package body is disposed on the first surface of the circuit layer. The first antenna penetrates the first package body and is electrically connected to the circuit layer. The electronic component is disposed on the second surface of the circuit layer.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: Disclosed in the present invention are a sensor packaging structure and a manufacturing method thereof. The sensor packaging structure includes a protection board, a circuit structure and a filling structure. A front surface of the circuit structure is connected to a first surface of the protection board. A second surface of the protection board is used as a sensing function surface. The filling structure is located on the outer periphery of the circuit structure and connected to the first surface of the protection board. The sensor packaging structure of the present invention uses the protection board as a protection layer of the functional circuit, which can effectively protect the functional circuit of the sensor. Meanwhile, the protection board is first connected to the circuit structure in the manufacturing method to avoid tolerance accumulation, increasing the manufacturing accuracy of the protection layer.

Abstract: The invention relates to semiconductor devices for converting ionizing radiation into an electrical signal. The present ionizing radiation sensor has an n+-i-p+ structure, produced using the planar process. The sensor contains an i-region in the form of a high-resistivity substrate of high-purity float-zone silicon with p-type conductivity, having on its front face n+-regions (2, 3), an SiO2 layer (4), aluminium metallization (5), and a passivation layer. On the front face of the substrate (1) n-regions (2) are formed by ion implantation; a masking layer of SiO2 (layer 4) is grown; aluminium metallization (5) is deposited; and a passivation layer (6) is applied.

Abstract: An imaging device includes a semiconductor substrate, pixels, a charge detector, charge storage portions, an output gate portion and a shift gate portion. The pixels and the charge detector are provided in the semiconductor substrate. The charge storage portions are provided on the charge detector side of the pixels, and linked to the pixels. The output gate portion is positioned between the charge detector and the charge storage portions, and includes charge transfer channels extending in a radial configuration in directions from the charge detector toward the pixels. The shift gate portion is positioned between one charge storage portion and one charge transfer channel. The shift gate portion includes a gate electrode provided on the semiconductor substrate. A planar configuration of the gate electrode has a side orthogonal to the extending direction of the one charge transfer channels, the side being most proximal to the one charge transfer channel.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a plurality of dies, a plurality of first conductive structures, an encapsulant, a second redistribution structure, and insulating layer, a plurality of second conductive structures, an antenna confinement structure, and a slot antenna. The dies and the first conductive structures are disposed on the first redistribution structure. The first conductive structures surround the dies. The encapsulant encapsulates the dies and the first conductive structures. The second redistribution structure is disposed on the dies, the first conductive structures, and the encapsulant. The insulating layer is over the second redistribution structure. The second conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

Abstract: The present disclosure relates to an imaging device, a driving method, and an electronic apparatus that can capture an image with a higher dynamic range. The imaging device includes a pixel region in which pixels are arranged, the pixels each including a photoelectric conversion unit that converts incident light into electric charges through electric conversion and stores the electric charges, and two or more charge storage units that store the electric charges transferred from the photoelectric conversion unit, and a drive unit that drives the pixels. The drive unit drives each pixel to cause the photoelectric conversion unit to repeatedly transfer electric charges with different exposure times to the two or more charge storage units during the light reception period of one frame. The present technology can be applied to an imaging device capable of capturing an HDR image, for example.

Abstract: A device transferring method for transferring a plurality of devices to a mounting substrate provided with a plurality of electrodes includes: a step of adhering an expandable tape to the plurality of devices formed on a front surface side of a substrate through a buffer layer; a step of applying a laser beam to the buffer layer from a back surface side of the substrate, to break the buffer layer; a step of moving the tape in a direction for spacing away from the substrate to separate the substrate and the plurality of devices from each other, thereby transferring the plurality of devices to the tape; a step of expanding the tape in such a manner that the layout of the plurality of devices corresponds to the layout of the plurality of electrodes; and a step of bonding the plurality of devices to the plurality of electrodes at once.

Abstract: A composite substrate production method of the invention includes (a) a step of mirror polishing a substrate stack having a diameter of 4 inch or more, the substrate stack including a piezoelectric substrate and a support substrate bonded to each other, the mirror polishing being performed on the piezoelectric substrate side until the thickness of the piezoelectric substrate reaches 3 ?m or less; (b) a step of creating data of the distribution of the thickness of the mirror-polished piezoelectric substrate; and (c) a step of performing machining with an ion beam machine based on the data of the thickness distribution so as to produce a composite substrate have some special technical features.

Abstract: An example sensor for image capturing may include a pixel array including a plurality of pixels; a read-out circuit configured to receive an analog electrical signal output from each of the plurality of pixels, convert the analog electrical signal into a digital electrical signal, and output the digital electrical signal; and a memory temporarily storing the digital electrical signal output from the read-out circuit and outputting at least part of the temporarily stored digital electrical signal to an external circuit.

Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.