Light Patents (Class 257/431)
  • Patent number: 10998361
    Abstract: An image-sensor package includes a cover glass, an image sensor, and an integrated circuit. The cover glass has a cover-glass bottom surface, to which the image sensor is bonded. The integrated circuit is beneath the cover-glass bottom surface, adjacent to the image sensor, and electronically connected to the image sensor. A method for packaging an image sensor includes attaching an image sensor to a cover-glass bottom surface of a cover glass, a light-sensing region of the image sensor facing the cover-glass bottom surface. The method also includes attaching an integrated circuit to the cover-glass bottom surface, a top IC-surface of the integrated circuit facing the cover-glass bottom surface.
    Type: Grant
    Filed: September 22, 2018
    Date of Patent: May 4, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventors: Wei-Feng Lin, Chun-Sheng Fan
  • Patent number: 10973425
    Abstract: The present invention describes vertically stacked and hermetically sealed implantable pressure sensor devices for measuring a physiological signal. The implantable device comprises multiple layers, including a first wafer having a pressure sensor configured to measure the physiological signal and a second wafer having at least a digitizing integrated circuit. The first wafer is vertically stacked or disposed over the second wafer so as to form a hermetic seal. The device may include one or more additional layers adapted for energy storage and transfer, such as a third layer having a super-capacitor and a fourth layer having a thin film battery.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: April 13, 2021
    Assignee: InjectSense, Inc.
    Inventor: Ariel Cao
  • Patent number: 10978597
    Abstract: A sensor includes a printed circuit board; at least one semiconductor chip arranged on the printed circuit board and includes a front-side contact, wherein the semiconductor chip is a radiation-detecting semiconductor chip; an embedding layer arranged on the printed circuit board and laterally adjoining the at least one semiconductor chip; and a contact layer connected to the front-side contact of the at least one semiconductor chip.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 13, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Dirk Becker, Matthias Sperl
  • Patent number: 10964737
    Abstract: A photoelectric conversion device includes: a light absorption layer that has a light entrance surface and a compound semiconductor material; a first electrode provided for each of the pixels, in opposed relation to an opposite surface to the light entrance surface; a first semiconductor layer of a first conductive type, with a bandgap energy larger than bandgap energy of the light absorption layer and that is provided between the light absorption layer and the first electrode; a second semiconductor layer of a second conductive type, with a bandgap energy larger than the bandgap energy of the light absorption layer and that is provided between the first semiconductor layer and the light absorption layer; and a first diffusion region of the second conductive type, in which the first diffusion region is provided between adjacent ones of the pixels and across the second semiconductor layer and the light absorption layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: March 30, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hideki Minari, Shunsuke Maruyama
  • Patent number: 10965369
    Abstract: Photonically integrated normal incidence photodetectors (NIPDs) and associated in-plane waveguide structures optically coupled to the NIPDs can be configured to allow for both in-plane and normal-incidence detection. In photonic circuits with light-generation capabilities, such as integrated optical transceivers, the ability of the NIPDs to detect in-plane light is used, in accordance with some embodiments, to provide self-test functionality.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 30, 2021
    Assignee: Juniper Networks, Inc.
    Inventors: John Parker, Brian Robert Koch, Gregory Alan Fish, Hyundai Park
  • Patent number: 10950671
    Abstract: A method for manufacturing a flexible touch panel, a flexible touch panel and a flexible touch device are provided. The method for manufacturing the flexible touch panel includes: forming a first indium tin oxide (ITO) film layer on a flexible base layer attached to a transparent substrate via an optical adhesive layer; and patterning the first ITO film layer to form a touch electrode of the flexible touch panel.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 16, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ting Zeng, Qicheng Chen, Hui Chen, Shichao Fei, Yangjie Li, Wanru Dong
  • Patent number: 10872915
    Abstract: An optical package structure includes a substrate, an optical element, a spacer and an encapsulant. The substrate has a top surface. The optical element is disposed adjacent to the top surface of the substrate and has a first height H1. The spacer surrounds the optical element and has a top surface. A distance between the top surface of the substrate and the top surface of the spacer is defined as a second height H2. The encapsulant is disposed between the optical element and the spacer, and has a third height H3 at a position adjacent to the optical element. The encapsulant covers at least a portion of the optical element. The optical element is exposed from the encapsulant, and H2>H1?H3.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Yun Hsu, Ying-Chung Chen
  • Patent number: 10872836
    Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Patent number: 10861884
    Abstract: A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 8, 2020
    Assignee: ARTILUX, INC.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 10854810
    Abstract: A passive magnetic device (PMD) has a base electrode, a multi-port signal structure (MPSS), and a substrate therebetween. The MPSS has a central plate residing in a second plane and at least two port tabs spaced apart from one another and extending from the central plate. The substrate has a central portion that defines a mesh structure between the base electrode and the central plate of the multi-port signal structure. A plurality of magnetic pillars are provided within the mesh structure, wherein each of the plurality of the magnetic pillars are spaced apart from one another and surrounded by a corresponding portion of the mesh structure. The PMD may provide a magnetically self-biased device that may be used as a radio frequency (RF) circulator, an RF isolator, and the like.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: December 1, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Andrew Arthur Ketterson, Xing Gu, Yongjie Cui, Xing Chen
  • Patent number: 10841526
    Abstract: An imaging device including a first imaging cell having a first photoelectric converter including a first electrode, a second electrode, and a first photoelectric conversion layer between the first electrode and the second electrode, and a first reset transistor one of a source and a drain of which is coupled to the first electrode; and a second imaging cell having a second photoelectric converter including a third electrode, a fourth electrode, and a second photoelectric conversion layer between the third electrode and the fourth electrode, and a second reset transistor one of a source and a drain of which is coupled to the third electrode. The imaging device further including a first voltage supply circuitry to supply a first voltage to the first reset transistor; and a second voltage supply circuitry to supply a second voltage different from the first voltage to the second reset transistor.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeyoshi Tokuhara, Sanshiro Shishido, Masaaki Yanagida
  • Patent number: 10818710
    Abstract: An image sensor may include a pixel array including different pixel blocks where a pixel block includes a block of adjacent unit pixels each unit responsive to light to produce photo-generated charges, a floating diffusion region disposed at a center of each unit pixel to receive the photo-generated charges, and transfer gates formed between the floating diffusion region and the unit pixel to control the transfer of the photo-generated charges. Each the pixel block may include an extra floating diffusion region at a center of the pixel block to interface with each of the adjacent unit pixels with the pixel block to photo-generated charges from each of the adjacent unit pixels and extra transfer gates that are formed between the extra floating diffusion region and the adjacent unit pixels to control the transfer of the photo-generated charges from the adjacent unit pixels to the extra floating diffusion region.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventor: Sung-Woo Lim
  • Patent number: 10757845
    Abstract: A high-frequency component includes a wiring substrate, a component mounted on an upper surface of the wiring substrate, a columnar member formed of a conductive resin and standing on the upper surface of the wiring substrate in a state of a lower end portion of the columnar member being fixed to the upper surface of the wiring substrate, and a shield case covering the component and the columnar member. The shield case has a lid plate disposed so as to face the upper surface of the wiring substrate and a side plate extending from an edge of the lid plate toward the upper surface of the wiring substrate, and an upper end portion of the columnar member is fixed to each of four corner portions of the lid plate, when viewed in a direction perpendicular to the upper surface of the wiring substrate.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 25, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshikazu Yagi, Kazushige Sato, Akihiro Hara, Noboru Morioka, Nobumitsu Amachi
  • Patent number: 10756228
    Abstract: The present disclosure relates to a sensor comprising: an array of photodetectors comprising a first subarray of at least one photodetector and a second subarray of at least one photodetector; a first optical arrangement to direct incoming photons toward the first subarray; and a second optical arrangement to direct incoming photons toward the second subarray.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: James Peter Drummond Downing
  • Patent number: 10735635
    Abstract: Systems and methods for implementing array cameras configured to perform super-resolution processing to generate higher resolution super-resolved images using a plurality of captured images and lens stack arrays that can be utilized in array cameras are disclosed. Lens stack arrays in accordance with many embodiments of the invention include lens elements formed on substrates separated by spacers, where the lens elements, substrates and spacers are configured to form a plurality of optical channels, at least one aperture located within each optical channel, at least one spectral filter located within each optical channel, where each spectral filter is configured to pass a specific spectral band of light, and light blocking materials located within the lens stack array to optically isolate the optical channels.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 4, 2020
    Assignee: FotoNation Limited
    Inventor: Jacques Duparre
  • Patent number: 10714521
    Abstract: To improve detection efficiency in a solid-state imaging element including a SPAD in which an electrode and wiring are placed in a central portion. A solid-state imaging element includes a photodiode and a light collecting section. The photodiode includes a light receiving surface and an electrode placed on the light receiving surface, and that outputs an electrical signal in accordance with light incident on the light receiving surface in a state where a voltage exceeding a breakdown voltage is applied to the electrode. The light collecting section causes light from a subject to be collected in the light receiving surface other than a region where the electrode is placed.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 14, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuhi Yorikado, Atsushi Toda, Susumu Inoue
  • Patent number: 10710875
    Abstract: In described examples, a device mounted on a substrate includes an encapsulant. In at least one example, an encapsulant barrier is deposited along a scribe line, along which the substrate is singulatable. To encapsulate one or more terminals of the substrate, an encapsulant is deposited between the encapsulant barrier and an edge of the device parallel to the encapsulant barrier.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jane Qian Liu, Gary Philip Thomson, Richard Allen Richter
  • Patent number: 10690755
    Abstract: A plurality of pixels of a solid-state imaging device include: a photoelectric converter which receives light from an object and converts the light into charge; a plurality of readers which read the charge from the photoelectric converter; a plurality of charge accumulators which accumulate the charge of the photoelectric converter; and a transfer controller which performs a transfer control including controlling whether the charge is transferred or blocked from being transferred. The readers read the charge of the photoelectric converter to the charge accumulators, the plurality of pixels include at least a first pixel and a second pixel, and the transfer controller performs the transfer control to cause addition of the charge read from each of the first pixel and the second pixel.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 23, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sei Suzuki, Tohru Yamada, Yasuyuki Shimizu
  • Patent number: 10672923
    Abstract: A front electrode for solar cells and a solar cell, the front electrode including a stepped structure at an outermost surface thereof, wherein the stepped structure is composed of n stages, in which n is an integer of 3 or greater, and an nth stage has a smaller cross-sectional area than an (n?1)th stage such that the (n?1)th stage is partially exposed, and the stepped structure occupies about 5% to about 100% of a total surface area of the outermost surface.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Dong Suk Kim, Hee In Nam, Sang Hee Park, Seok Hyun Jung, Jae Hwi Cho
  • Patent number: 10670724
    Abstract: A light detection and ranging (LIDAR) time of flight (TOF) sensor for inputting and outputting simultaneously and 3-dimensional laser scanning system including the same are disclosed. In one aspect, the sensor includes a substrate and a light receiving element array provided on the substrate and including a plurality of light receiving elements. The sensor also includes readout circuits configured to receive electrical signals from the light receiving elements and perform signal processing on the electrical signals. The sensor further includes metal lines disposed on the light receiving element array in parallel, provided to correspond to the number of the light receiving elements, and configured to connect the light receiving elements to the readout circuits in one-to-one correspondence.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 2, 2020
    Assignee: Korea Electronics Technology Institute
    Inventors: Yeon Kug Moon, Young Bo Shim
  • Patent number: 10651225
    Abstract: In some embodiments, the present disclosure relates to a three-dimensional integrated chip. The three-dimensional integrated chip includes a first integrated chip (IC) die and a second IC die. The first IC die has a first image sensor element configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second IC die has a second image sensor element configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. A first band-pass filter is arranged between the first IC die and the second IC die and is configured to reflect electromagnetic radiation that is within the first range of wavelengths.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Patent number: 10651231
    Abstract: A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 12, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Endo, Tetsuya Itano, Kazuo Yamazaki, Kyouhei Watanabe, Junji Iwata
  • Patent number: 10644185
    Abstract: Provided is an infrared detecting device with high SNR. The infrared detecting device includes: a semiconductor substrate; a first compound semiconductor layer; a light receiving layer formed on the first compound semiconductor layer and containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s); a third compound semiconductor layer; and a second compound semiconductor layer containing at least In, Al, and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), in which the first compound semiconductor layer includes, in the stated order, a first A layer, a first B layer, and a first C layer, each containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), and the proportion(s) of the Al composition or the Al composition and the Ga composition of each layer satisfy a predetermined relation(s).
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 5, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Yoshiki Sakurai, Osamu Morohara, Hiromi Fujita
  • Patent number: 10636822
    Abstract: In a photoelectric-conversion element having a large light receiving region for a high-speed transfer, and a solid-state image sensor including the photoelectric-conversion element, the photoelectric-conversion element includes first to eighth charge read-out regions, which are provided at positions symmetric with respect to a center position of a light receiving region and first to eighth field-control electrodes, which are arranged on both sides of charge-transport paths extending from the center position of the light receiving region to the first to eighth charge read-out regions, respectively, and change depletion potentials of the charge-transport paths and the octuple charge-transfer channels.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 28, 2020
    Assignee: National University Corporation Shizuoka University
    Inventors: Shoji Kawahito, Min-Woong Seo, Keita Yasutomi, Yuya Shirakawa
  • Patent number: 10629641
    Abstract: A fan-out sensor package includes: a first connection member having a through-hole and including a first wiring layer; a sensor chip disposed in the through-hole; an optical lens disposed in the through-hole and attached to the sensor chip; an encapsulant encapsulating at least portions of the first connection member, the sensor chip, and the optical lens; and a second connection member including a first insulating layer disposed on the first connection member, the sensor chip, and the optical lens, a redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering the redistribution layer. The redistribution layer electrically connects the first wiring layer and the connection pads, the first insulating layer has a cavity exposing at least a portion of one surface of the optical lens, and one side of the cavity is closed by the second insulating layer.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae Kul Lee
  • Patent number: 10598967
    Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 24, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Adams, Prakash B. Gothoskar, Vipulkumar Patel, Mark Webster
  • Patent number: 10593615
    Abstract: A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Damian Sojka
  • Patent number: 10509244
    Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan, Vibhor Jain, John J. Pekarik
  • Patent number: 10510790
    Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10498981
    Abstract: An imaging device includes: a first unit pixel cell including first and second electrodes, a first photoelectric conversion layer therebetween, and a first signal detection circuit connected to the first electrode; and a voltage supply circuit supplying a voltage to the second electrode. The voltage supply circuit forms exposure periods and one or more non-exposure periods that separate the exposure periods from each other by changing the voltage. The exposure and non-exposure periods are included in each of a first frame period and a second frame period subsequent to the first frame period. Timing of a start and an end of each of the exposure periods in the first frame period is the same as that of each of the exposure periods in the second frame period. Magnitude of change of the voltage in the first frame period is different from that of the voltage in the second frame period.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: December 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yasuo Miyake
  • Patent number: 10484632
    Abstract: An imaging element that images a subject through an imaging optical system, and includes a plurality of pairs each including a photoelectric conversion unit which is formed within a semiconductor substrate, receives one of a pair of luminous flux passed through different portions arranged in one direction of a pupil area of the imaging optical system, and accumulates electric charges corresponding to a light reception amount, and a photoelectric conversion unit which is formed within the semiconductor substrate, receives the other one of the pair of luminous flux, and accumulates electric charges corresponding to a light reception amount, each of pixels including the photoelectric conversion units constituting the pair includes an electric charge retaining unit as defined herein, and when being viewed in a direction perpendicular to the semiconductor substrate, the electric charge retaining unit included in the pixel is disposed in an area as defined herein.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 19, 2019
    Assignee: FUJIFILM Corporation
    Inventor: Makoto Kobayashi
  • Patent number: 10473853
    Abstract: Various embodiments of a fully integrated avalanche photodiode receiver and manufacturing method thereof are described herein. A photonic device includes a silicon-on-insulator (SOI) substrate with a buried oxide (BOX) layer therein, an avalanche photodiode integrated with the SOI substrate, a capacitor integrated with the SOI substrate, a resistor integrated with the SOI substrate, and silicon passive waveguides as well as bonding pads integrated with the SOI substrate.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 12, 2019
    Assignee: SiFotonics Technologies Co., Ltd.
    Inventors: Mengyuan Huang, Tzung-I Su, Su Li, Naichuan Zhang, Pengfei Cai, Wang Chen, Ching-yin Hong, Dong Pan
  • Patent number: 10461082
    Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Nadia M. Rahhal-Orabi, Tahir Ghani
  • Patent number: 10453987
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Patent number: 10453880
    Abstract: A semiconductor element includes a semiconductor region (11) of a first conductivity type, a buried charge-generation region (16) of a second conductivity type, buried in an upper portion of the semiconductor region (11) to implement a photodiode (D1) together with the semiconductor region (11) to generate charges, a charge-readout region (15) of the second conductivity type, provided in the semiconductor region (11) to accumulate the charges transferred from the buried charge-generation region (16), and a reset-performing region (12) of the second conductivity type, provided in the semiconductor region (11), a variable voltage is applied to the reset-performing region (12) to change the height of a potential barrier generated in the semiconductor region (11) sandwiched between the charge-readout region (15) and the reset-performing region (12) to exhaust the charges accumulated in the charge-readout region (15).
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 22, 2019
    Assignee: National University Corporation Shizuoka University
    Inventors: Shoji Kawahito, Min-Woong Seo
  • Patent number: 10411109
    Abstract: A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Tak H. Ning, Sufi Zafar, Oscar van der Straten
  • Patent number: 10412245
    Abstract: According to the present invention, there is provided a method of manufacturing a light-transmitting member for an image reading apparatus configured to read an image on a conveyed original, the method including: disposing a plurality of substrates each having a first light-transmitting surface and a second light-transmitting surface opposed to each other so that a part of the first light-transmitting surface of one of two adjacent substrates is in contact with a part of the second light-transmitting surface of another of the two adjacent substrates; and providing coating on the first light-transmitting surface of each of the plurality of substrates.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 10, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tokuji Takizawa, Akira Matsumoto
  • Patent number: 10361235
    Abstract: An image sensor including a substrate, an image sensing element, and an adhesive layer is provided. The substrate has an arc surface. The image sensing element is disposed on the arc surface and curved to fit the contour of the arc surface. The adhesive layer is disposed on the arc surface and encapsulates the image sensing element.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 23, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Shu Yang, Hsiang-Hung Chang
  • Patent number: 10347670
    Abstract: A photodetection element according to an embodiment includes: a photodiode cell, the photodiode cell including: a semiconductor substrate; a first semiconductor layer disposed on the semiconductor substrate; a second semiconductor layer disposed in a region including an interface between the semiconductor substrate and the first semiconductor layer, the second semiconductor layer being of the same conductivity type as the semiconductor substrate; and a third semiconductor layer disposed in a surface region of the first semiconductor layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 9, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Keita Sasaki
  • Patent number: 10340135
    Abstract: In an embodiment, a method for transferring a pattern constituted by vertical spacers arranged on a template with intervals to the template, includes depositing by plasma-enhanced cyclic deposition a layer as a spacer umbrella layer substantially only on a top surface of each vertical spacer made of silicon or metal oxide, wherein substantially no layer is deposited on sidewalls of the vertical spacers and on an exposed surface of the template, followed by transferring the pattern constituted by the vertical spacers to the template by anisotropic etching using the vertical spacers with the spacer umbrella layers.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 2, 2019
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 10321079
    Abstract: The present disclosure relates to a solid-state imaging apparatus, a manufacturing method of the same and an electronic device which can make an apparatus size further smaller. A solid-state imaging apparatus includes: a laminate of a first structure in which a pixel array unit in which pixels that perform photoelectric conversion are two-dimensionally arranged is formed and a second structure in which an output circuit unit configured to output pixel signals output from the pixels to an outside of an apparatus is formed. The output circuit unit, a first through hole via which penetrates through a semiconductor substrate constituting part of the second structure, and an external terminal for signal output connected to the outside of the apparatus are disposed below the pixel array unit of the first structure. The present disclosure can be applied, for example, to a solid-state imaging apparatus or the like.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 11, 2019
    Assignee: Sony Corporation
    Inventor: Shinji Miyazawa
  • Patent number: 10312391
    Abstract: An avalanche photodiode has a first diffused region of a first diffusion type overlying at least in part a second diffused region of a second diffusion type; and a first minority carrier sink region disposed within the first diffused region, the first minority carrier sink region of the second diffusion type and electrically connected to the first diffused region. In particular embodiments, the first diffusion type is N-type and the second diffusion type is P-type, and the device is biased so that a depletion zone having avalanche multiplication exists between the first and second diffused regions.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 4, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Vincent Venezia, Dyson H. Tai, Bowei Zhang
  • Patent number: 10297708
    Abstract: A photodetector includes a detector material having an upper layer, a lower layer, and at least one sidewall. Also included as part of the photodetector are a first contact electrically coupled to the detector material through the upper layer and a second contact electrically coupled to the detector material through the lower layer. Diffused into the sidewall by a passivation process is a dopant material operable to electrically isolate the first contact from the second contact via the sidewall. The dopant material is provided by a passivation layer deposited on the sidewall.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: May 21, 2019
    Assignee: The United States of America, as represented by the Secretary of the Air Force
    Inventors: Gamini Ariyawansa, Joshua M. Duran, Charles J. Reyner, John E. Scheihing
  • Patent number: 10295745
    Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 21, 2019
    Assignee: The Research Foundation for The State University of New York
    Inventors: Douglas Coolbaugh, Thomas Adam, Gerald L. Leake
  • Patent number: 10290780
    Abstract: A method for manufacturing a light-emitting device includes: providing first and second substrates each including a plurality of packages, the packages each having a recess and a light-emitting element mounted in the recess; performing potting by supplying a resin member containing particles of a fluorescent material into the recess of each of the packages of the first substrate; spreading the resin member in the recess of each of the packages of the first substrate; measuring a height of an upper surface of the resin member spread in the recess of at least one of the packages of the first substrate; and adjusting a quantity of the resin member to be supplied into the recess of each of the packages of the second substrate depending on the measured height of the upper surface of the resin member.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 14, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Shu Morizumi, Shinya Nakagawa
  • Patent number: 10263030
    Abstract: Implementations of image sensors may include: a first die including a plurality of detectors adapted to convert photons to electrons; a second die including a plurality of transistors, passive electrical components, or both transistors and passive electrical components; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, passive electrical components, or transistors and passive electrical components of the second die may be adapted to enable operation of the plurality of detectors of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 16, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swarnal Borthakur, Marc Sulfridge, Vladimir Korobov
  • Patent number: 10207948
    Abstract: The present invention relates to an improved cordierite glass-ceramic. In order to improve the materials properties, it is proposed that the glass-ceramic comprising SiO2, Al2O3, MgO and Li2O contains cordierite as main crystal phase and that a secondary crystal phase of the glass-ceramic comprises high-quartz solid solution and/or keatite solid solution. The invention further relates to a process for producing such a glass-ceramic and the use of such a glass-ceramic.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 19, 2019
    Assignee: SCHOTT AG
    Inventors: Meike Schneider, Oliver Hochrein, Bianca Schreder, Bernd Ruedinger, Martun Hovhannisyan
  • Patent number: 10195758
    Abstract: A cut data generating apparatus configured to generate cut data for a cutting apparatus including a cut mechanism to cut a pattern from a workpiece, the cut data generating apparatus comprising: a controller, the controller being configured to control the cut data generating apparatus to: identify a size of an original pattern to be cut; judge whether the size of the original pattern identified is larger than a size of the workpiece; divide the original pattern into plural divided patterns smaller than the size of the workpiece in case the size of the original pattern is larger than the size of the workpiece; and generate cut data for cutting each of the divided patterns, determine whether at least one of the plural divided patterns divided falls within one workpiece along with another divided pattern, and generate cut data for cutting the divided patterns from one workpiece in case at least one of the divided patterns falls within one workpiece along with another divided pattern.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 5, 2019
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Daisuke Abe
  • Patent number: 10192919
    Abstract: An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a semiconductor substrate. Trench isolation structures may separate the analog circuitry from the digital circuitry on the substrate. The trench isolation structures may be formed from dielectric-filled trenches in the substrate that isolate the portion of the substrate having the analog circuitry from the portion of the substrate having the digital circuitry. The trench isolation structures may prevent digital circuit operations such as switching operations from negatively affecting the performance of the analog circuitry. Additional trench isolation structures may be interposed between portions of the substrate on which bond pads are formed and other portions of the substrate to prevent capacitive coupling between the bond pad structures and the substrate, thereby enhancing the high frequency operations of the image sensor.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 29, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Rupert Barabash Barr, Aaron Kenneth Belsher, Giovanni Deamicis
  • Patent number: 10172241
    Abstract: Provided is a flexible device, which includes a flexible substrate, a plurality of electrode lines provided on the flexible substrate and configured to contact the following anisotropic conductive film and then extend to a side of the flexible substrate, an anisotropic conductive film configured to contact the electrode line and laminated on the flexible substrate, a plurality of bumps provided on the anisotropic conductive film, and a circuit board having an electronic device provided at one side thereof and configured to contact the plurality of bumps.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 1, 2019
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Kyung Wook Baek, Keon Jae Lee, Geon Tae Hwang, Hyeon Kyun Yoo, Do Hyun Kim, Yoo Sun Kim