Abstract: A particle, includes a semiconductor nanocrystal. The nanocrystal is doped.

Abstract: An apparatus and method are disclosed for encapsulating an OLED device formed on a flexible substrate. The OLED device is moisture protected by an encapsulation which sandwiches the OLED device between two transparent dielectric metal oxide layers. The oxide layers are formed in a chamber which includes a plurality of processing stations for forming successive atomic layers of oxides along passes of the flexible substrate within the chamber.

Abstract: The present invention, a III-nitride light emitting diode (LED) and a manufacture method thereof, forms a magnetic metal layer in a conventional III-nitride LED by the method of thermal evaporation, e-beam evaporation, ion sputtering, or electroplate. Due to the eddy current effect, heat is generated by using electromagnetic oven inducing with electromagnetic wave to activate the p-type semiconductor material in III-nitride LED. The present invention has advantages of providing the equipments of simple structure and low cost. The contact resistance between the semiconductors and electrodes is reduced while the III-nitride compound semiconductor material is activated.

Abstract: A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.

Abstract: A cascaded organic electroluminescent device with connecting units having improved voltage stability is disclosed. The device comprises an anode, a cathode, a plurality of organic electroluminescent units disposed between the anode and the cathode, wherein the organic electroluminescent units comprise at least a hole-transporting layer and an electron-transporting layer, and a connecting unit disposed between each adjacent organic electroluminescent unit, wherein the connecting unit comprises, in sequence, an n-type doped organic layer, an interfacial layer, and a p-type doped organic layer, and wherein the interfacial layer prevents diffusion or reaction between the n-type doped organic layer and the p-type doped organic layer.

Abstract: A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage value, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby preventing the occurrence of the electromagnetic noise and an excessively large voltage.

Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance.

Abstract: A gallium nitride-based light emitting element with improved light emission efficiency. A gallium nitride-based light emitting element is constructed by forming an n type GaN buffer layer, an n type GaN layer, an InGaN emissive layer, and a p type GaN layer in that order on a substrate, and forming a negative electrode and a positive electrode. A transparent ZnO electrode is formed on the p type GaN layer and abutting the positive electrode. Uniform current is supplied to the emissive layer by the ZnO electrode, and, at the same time, light from the emissive layer is transmitted through the ZnO electrode and externally emitted.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: The present invention, a III-nitride light emitting diode (LED) and a manufacture method thereof, forms a magnetic metal layer in a conventional III-nitride LED by the method of thermal evaporation, e-beam evaporation, ion sputtering, or electroplate. Due to the eddy current effect, heat is generated by using electromagnetic oven inducing with electromagnetic wave to activate the p-type semiconductor material in III-nitride LED. The present invention has advantages of providing the equipments of simple structure and low cost. The contact resistance between the semiconductors and electrodes is reduced while the III-nitride compound semiconductor material is activated.

Abstract: A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.

Abstract: There is provided a susceptor with a built-in electrode and a manufacturing method therefor, in which there is no danger of corrosive gas or plasma or the like penetrating to the inside of the substrate, which has excellent corrosion resistance and plasma resistance, in which nonconductivity under high temperatures is improved, and in which leakage current does not occur.

Abstract: Coils for use within high density plasma chambers are provided that do not electrically disconnect or short circuit following repeated depositions and that produce films having reduced in-film defect densities. To reduce in-film defect densities, dielectric inclusion content, porosity, grain size and surface roughness of a coil are reduced, while the mechanical strength of the coil is increased so as to both decrease defect generation and thermal creep rate (e.g., to prevent electrical disconnection or short circuiting of the coil following repeated depositions).

Abstract: A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction of a diode in a single crystalline substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with most of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and a more stable and conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.

Abstract: The invention relates to a semiconductor device of the type sealed in glass, comprising a silicon semiconductor body having a pn-junction between opposing faces which are connected to slugs of a transition metal by means of a bonding layer, the bonding layer comprising a quantity of aluminum in the range between 7 and 15 wt. % and a quantity of silver in the range between 85 and 93 wt. %.

Abstract: A thin film diode and method of fabrication having large current capability and low-turn on voltage is provided as a switching or protective device against electrostatic discharge in integrated devices such as magnetoresistive sensors and the like. A first semiconductor thin film layer of NiO.sub.x having p type properties is disposed on an arbitrary substrate, such as alumina, glass, silicon dioxide, silicon and the like. A second semiconducting layer of tin oxide or indium oxide or other transparent oxide is joined to the first layer to form a p/n junction. In one method of fabrication, the p/n junction is formed in a sputtering process under a partial oxygen pressure to control the stoichiometry of the films. Gold and Gold Indium contacts are attached to the films to provide electrical contacts. The device is enclosed in a protective coating and connected in parallel with an electronic device subject to electrostatic discharge.

Abstract: A compliant layer metallization for relieving thermal and mechanical stress developed between a semiconductor and a semiconductor submount. The compliant layer metallization includes a compliant layer, a wetting layer and a barrier layer. The compliant layer provides thermal and mechanical stress relief. The wetting layer ensures adequate wetting during soldering. The barrier layer prevents diffusion of bonding material into the compliant layer and/or into the semiconductor during solder-bonding. The compliant layer metallization design promotes ease of manufacturing.

Abstract: Chalcopyrite compound semiconductor thin films represented by I-III-VI.sub.2-x V.sub.x or I-III-VI.sub.2-x VII.sub.x, and semiconductor devices having a I-III-VI.sub.2 /I-III-VI.sub.2-x V.sub.x or I-III-VI.sub.2 /I-III-VI.sub.2-x VII.sub.x chalcopyrite homojunction are provided. Such chalcopyrite compound semiconductor thin films are produced by radiating molecular beams or ion beams of the I, III, VI, and V or VII group elements simultaneously, or by doping I-III-VI.sub.2 chalcopyrite thin films with VII-group atoms after the formation thereof. Pollution-free solar cells are also provided, which are formed by the steps of forming a structure of a lower electrode, a chalcopyrite semiconductor thin film, and an upper electrode and radiating accelerated ion beams of a V, VII, or VIII group element thereto.

Abstract: Briefly stated, the present invention provides a vertical current flow semiconductor device (17). The vertical current flow semiconductor device (17) includes a semiconductor substrate (12) having an intermediate conductor layer (16) on a surface of the substrate (12). An active layer (11) that is used for forming active elements (20, 21, 22, 23) of the vertical current flow semiconductor device (17) is on the intermediate conductor layer (16). The intermediate conductor layer (16) forms an ohmic contact with the active layer (11).

Abstract: The present invention relates to a composite material. This material comprises at least one layer A of III-V compound and one epitaxial layer B on said layer of III-V compounds, the epitaxial layer corresponding to the empirical formula REPc, where RE is chosen from the group comprising the rare earths (scandium, yttrium, preferably lanthanum, lanthanides, and their mixtures); and where Pc is chosen from the elements of column V of the periodic table of the elements and their mixtures, and, when Pc contains arsenic, the compound REPc is at least a ternary compound.Application is to the electronics industry.