With Backside Illumination (e.g., With A Thinned Central Area Or Non-absorbing Substrate) Patents (Class 257/460)
  • Patent number: 5852322
    Abstract: A radiation-sensitive detector element has an active area which is formed between two adjoining layer areas of a layer arrangement and within which a conversion of incident electromagnetic radiation into electrical signals takes place. Taking into consideration the penetration depth of the radiation, the position of the active area in relation to the two limiting surfaces is selected in such a way that at least two layer areas for connecting the detector element to an evaluation circuit can be mounted on a surface located opposite the radiation-sensitive surface which is impinged by the incident radiation.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: December 22, 1998
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventor: Peter Speckbacher
  • Patent number: 5831309
    Abstract: Semifinished products designed as composite bodies for electronic or opto-electronic semiconductor components are known. The composite bodies are made of a disk-shaped, transparent quartz glass substrate and a wafer made of a semiconductor material. The directly bonded surfaces of the quartz glass substrate and wafer are polished before being mutually bonded. In order to create a semifinished product that resists temperatures above 900.degree. C., such as those used to produce semiconductor circuits in industrially feasible times, without raising fears of a substantial reduction of the adhesive forces, chipping of the wafers away from each other or an undesirable deformation of the composite body, the substrate quartz glass is a synthetic quartz glass with at least 10.sup.14.0 poise viscosity at 950.degree. C. which does not fall below 10.sup.12 poise at 1050.degree. C.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: November 3, 1998
    Assignee: Heraeus Quarzglas GmbH
    Inventors: Wolfgang Englisch, Reinhold Uebbing
  • Patent number: 5763903
    Abstract: An avalanche photodiode for detecting x-rays and other radiation comprises a first substrate having a portion removed therefrom, a first insulating film formed on the first substrate, a second substrate comprising a floating zone silicon semiconductor substrate disposed on the first insulating film, an impurity region selectively formed in the second substrate at a surface corresponding to the removed portion, a PN junction formed on the second substrate, a glass substrate mounted to the second substrate, a first electrode formed on the first substrate for applying a voltage to the impurity region, a second electrode formed on the second substrate for applying a voltage to the second substrate, a third electrode formed on the glass substrate and electrically connected to the second electrode, and an integrated circuit package having a lead pin connected to the third electrode. Accordingly, a shallow depletion layer may be provided on a floating zone SOI substrate.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: June 9, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Masaaki Mandai, Tomoyuki Yoshino, Tadao Akamine, Yutaka Saitoh, Junko Yamanaka, Osamu Koseki
  • Patent number: 5729038
    Abstract: Semiconductor-on-glass integrated circuits may include photodetectors which are stimulated by backside light passing through the glass substrate; this provides information reception by optical communication. Bipolar and field effect transistors are shielded from the light by their buried layers. Further, LEDs integrated together with photodetectors permits all optical communication among glass substrate chips. Alternative uses of glass substrate include thermal isolation for efficient thermally regulated integrated circuits.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: March 17, 1998
    Assignee: Harris Corporation
    Inventors: William Ronald Young, Anthony L. Rivoli
  • Patent number: 5608255
    Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: March 4, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Eric A. Martin, Kenneth Vaccaro, William Waters, Joseph P. Lorenzo, Stephen Spaziani
  • Patent number: 5308980
    Abstract: A hybrid infrared focal plane array detector employs a detector layer and transparent substrate bonded to a thin semiconductor readout integrated circuit and thicker readout circuit substrate. The readout circuit is rigidly bonded to the readout substrate to form a composite structure having a thermal coefficient of expansion substantially matching that of the detector portion. The hybrid device may be cooled from room temperature to cryogenic operation temperatures without thermal mismatch structural problems.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: May 3, 1994
    Assignee: Amber Engineering, Inc.
    Inventor: Jeffrey Barton
  • Patent number: 5304500
    Abstract: Each diode of an indium antimonide electro-optical detector array on a dielectric backing transparent to optical energy to be detected includes a junction that less than about a half micron from the diode surface on which the energy is initially incident. The optical energy is incident on a P-type doped region prior to being incident on a bulk N-type doped region. Both P-and N-type doped regions of adjacent diodes are spaced from each other. Metal electrically connects the P-type doped regions together without interfering substantially with the incident optical energy. A multiplexer integrated circuit substrate extends parallel to the backing and includes an array of elements for selective readout of the electric property of the diodes. The elements and diodes have approximately the same topographical arrangement so that corresponding ones of the elements and diodes are aligned. An array of indium columns or bumps connects the corresponding aligned elements and diodes.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: April 19, 1994
    Assignee: Cincinnati Electronics Corporation
    Inventors: Harold A. Timlin, Charles J. Martin
  • Patent number: 5264699
    Abstract: A hybrid infrared focal plane array detector employs a thinned detector layer and substrate directly bonded to a conventional semiconductor readout integrated circuit substrate. The infrared detector layer and transparent substrate is thinned to a thickness of approximately 25-400.mu. to allow the detector to act like a flexible membrane to elastically respond to thermal mismatch due to differing coefficients of thermal expansion between the detector and semiconductor readout circuit as the hybrid device is cooled from manufacturing at room temperature to cryogenic operation temperatures. By thinning the detector substrate to a desired thickness, essentially unlimited hybrid detector sizes may be obtained. Additionally, the detector layer and substrate may be divided into sub-arrays to provide further resistance to stress induced from thermal mismatch.
    Type: Grant
    Filed: February 20, 1991
    Date of Patent: November 23, 1993
    Assignee: Amber Engineering, Inc.
    Inventors: Jeffrey Barton, Arthur H. Lockwood
  • Patent number: 5227656
    Abstract: Each diode of an indium antimonide electro-optical detector array on a dielectric backing transparent to optical energy to be detected includes a junction that less than about a half micron from the diode surface on which the energy is initially incident. The optical energy is incident on a P-type doped region prior to being incident on a bulk N-type doped region. Both P- and N-type doped regions of adjacent diodes are spaced from each other. Metal electrically connects the P-type doped regions together without interfering substantially with the incident optical energy. A multiplexer integrated circuit substrate extends parallel to the backing and includes an array of elements for selective readout of the electric property of the diodes. The elements and diodes have approximately the same topographical arrangement so that corresponding ones of the elements and diodes are aligned. An array of indium columns or bumps connects the corresponding aligned elements and diodes.
    Type: Grant
    Filed: November 6, 1990
    Date of Patent: July 13, 1993
    Assignee: Cincinnati Electronics Corporation
    Inventors: Harold A. Timlin, Charles J. Martin
  • Patent number: 5198881
    Abstract: A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.
    Type: Grant
    Filed: August 7, 1991
    Date of Patent: March 30, 1993
    Assignee: Massachusetts Institute of Technology
    Inventors: Jammy C. Huang, Mordechai Rothschild, Barry E. Burke, Daniel J. Ehrlich, Bernard B. Kosicki
  • Patent number: 5198685
    Abstract: A photoelectric conversion apparatus having a thin plate glass wear-resisting layer is formed on photoelectric conversion devices, drive circuit and signal lines. An original document is disposed on the wear-resisting layer to confront the photoelectric conversion devices. Light is emitted from a light source disposed to confront the light transmissive substrate on the side opposing the original document, transmitted through a light transmissive substrate and applied to the original document. Reflected light from the original document is received by the photoelectric conversion devices so that electric signals transmitted from the photoelectric conversion devices can be read out through the signal lines.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: March 30, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masashi Kitani, Hisanori Tsuda, Katsunori Terada, Satoshi Itabashi, Tetsuya Shimada
  • Patent number: 5192991
    Abstract: A polycrystalline semiconductor device and a method of manufacturing the device are disclosed. An amorphous semiconductor film is deposited on a glass substrate and given thermal treatment at a crystallization temperature of 600.degree. C. or lower to form a polycrystalline photoconductive strucutre. The substrate is made from a material having the property of contracting at a percentage different than the semiconductor film by 10% or less, the contraction being caused by the thermal treatment.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: March 9, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Hosokawa