With Specified Schottky Metal Patents (Class 257/473)
  • Patent number: 10283609
    Abstract: A nitride semiconductor device is disclosed, where the nitride semiconductor device is a type of field effect transistor having a gate electrode and an insulating film covering the gate electrode. The gate electrode has stacked metals of nickel (Ni) and gold (Au), while, the insulating film is made of silicon nitride (Si). A feature of the gate electrode of the present invention is that the nickel layer contains silicon (Si) atoms at an atomic concentration from 0.01 at % to 10 at %.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 7, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Patent number: 9893192
    Abstract: To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device formed using an oxide semiconductor and having favorable electrical characteristics. A semiconductor device includes an island-shaped semiconductor layer over an insulating surface; a pair of electrodes in contact with a side surface of the semiconductor layer and overlapping with a part of a top surface of the semiconductor layer; an oxide layer located between the semiconductor layer and the electrode and in contact with a part of the top surface of the semiconductor layer and a part of a bottom surface of the electrode; a gate electrode overlapping with the semiconductor layer; and a gate insulating layer between the semiconductor layer and the gate electrode. In addition, the semiconductor layer includes an oxide semiconductor, and the pair of electrodes includes Al, Cr, Cu, Ta, Ti, Mo, or W.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Kazuya Hanaoka
  • Patent number: 9576949
    Abstract: A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Wan-Yen Lin, Ming-Hsiang Song, Cheng-Hsiung Kuo, Yue-Der Chih
  • Patent number: 9236434
    Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: January 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chiharu Ota, Takashi Shinohe, Makoto Mizukami, Johji Nishio
  • Patent number: 9231068
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 5, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventor: Hong Shen
  • Patent number: 9035321
    Abstract: There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 19, 2015
    Assignee: SHOWA DENKO K.K.
    Inventors: Akihiro Matsuse, Kotaro Yano
  • Publication number: 20150123169
    Abstract: Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au).
    Type: Application
    Filed: October 29, 2014
    Publication date: May 7, 2015
    Inventors: Shiban Kishan TIKU, Viswanathan RAMANATHAN
  • Patent number: 9018638
    Abstract: A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 28, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chee-Wee Liu, Hui-Hsuan Wang
  • Patent number: 8969993
    Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8969995
    Abstract: High-efficiency Schottky diodes (HED) and rectifier systems having such semiconductor devices are provided, which Schottky diodes (HED) are composed of at least one Schottky diode combined with an additional semiconductor element, e.g., with magnetoresistors (TMBS) or with pn diodes (TJBS), and have trenches. Such high-efficiency Schottky diodes make it possible to construct rectifiers which are suitable for higher temperatures and can therefore be used in motor vehicle generators, without particular cooling measures such as heat sinks being required.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Gert Wolf, Markus Mueller
  • Patent number: 8916946
    Abstract: The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 23, 2014
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Yoshiyuki Doi, Yoshifumi Muramoto, Takaharu Ohyama
  • Patent number: 8901698
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8878327
    Abstract: A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tyng Yen, Young-Shying Chen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 8878329
    Abstract: A high voltage device having a Schottky diode integrated with a MOS transistor includes a semiconductor substrate a Schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the Schottky diode, and a control gate covering a portion of the Schottky diode and the first doped region positioned on the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 4, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Min-Hsuan Tsai
  • Patent number: 8878363
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 8847200
    Abstract: A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 30, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Roy E. Scheuerlein
  • Patent number: 8830725
    Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Donald S Bethune, Kailash Gopalakrishnan, Andrew J Kellock, Rohit S Shenoy, Kumar R Virwani
  • Patent number: 8809988
    Abstract: A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: August 19, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ji-Hyoung Yoo, Martin E. Garnett
  • Patent number: 8803125
    Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 8796808
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 5, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Patent number: 8785970
    Abstract: A bidirectional switch controllable by a voltage between its gate and rear electrode and including an N-type semiconductor substrate surrounded with a P-type well; on the front surface side, a P-type well in which is formed a first N-type region; on the rear surface side, a P-type layer in which is formed a second N-type region. The well is doped to less than 1016 at./cm3, the exposed surfaces of this well being heavily P-type doped. At least a third P-type region, of same doping level as the well, is formed on the front surface side in the substrate, and contains at least a fourth N-type region of a doping level lower than 1017 at./cm3, on which is formed a Schottky contact.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (TOURS) SAS
    Inventor: Samuel Menard
  • Patent number: 8723229
    Abstract: In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 13, 2014
    Assignee: Panasonic Corporation
    Inventors: Masahiro Hikita, Kenichiro Tanaka, Tetsuzo Ueda
  • Patent number: 8704322
    Abstract: The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 22, 2014
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Yoshiyuki Doi, Yoshifumi Muramoto, Takaharu Ohyama
  • Patent number: 8648437
    Abstract: A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: February 11, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8643134
    Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: February 4, 2014
    Assignee: Avogy, Inc.
    Inventors: Madhan Raj, Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano
  • Patent number: 8630326
    Abstract: A hybrid integrated optical device includes a substrate comprising a silicon layer and a compound semiconductor device bonded to the silicon layer. The device also includes a bonding region disposed between the silicon layer and the compound semiconductor device. The bonding region includes a metal-semiconductor bond at a first portion of the bonding region. The metal-semiconductor bond includes a first pad bonded to the silicon layer, a bonding metal bonded to the first pad, and a second pad bonded to the bonding metal and the compound semiconductor device. The bonding region also includes an interface assisted bond at a second portion of the bonding region. The interface assisted bond includes an interface layer positioned between the silicon layer and the compound semiconductor device, wherein the interface assisted bond provides an ohmic contact between the silicon layer and the compound semiconductor device.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Skorpios Technologies, Inc.
    Inventors: Stephen B. Krasulick, John Dallesasse
  • Patent number: 8624347
    Abstract: A Schottky barrier diode includes a semiconductor layer having a plurality of trenches formed by digging in from a top surface and having mesa portions formed between adjacent trenches, and a Schottky metal formed to contact the top surface of the semiconductor layer including inner surfaces of the trenches.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: January 7, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshiteru Nagai, Kohei Makita
  • Patent number: 8611388
    Abstract: A composite integrated optical device includes a substrate including a silicon layer and a waveguide disposed in the silicon layer. The composite integrated optical device also includes an optical detector bonded to the silicon layer and a bonding region disposed between the silicon layer and the optical detector. The bonding region includes a metal-assisted bond at a first portion of the bonding region. The metal-assisted bond includes an interface layer positioned between the silicon layer and the optical detector. The bonding region also includes a direct semiconductor-semiconductor bond at a second portion of the bonding region.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: December 17, 2013
    Assignee: Skorpios Technologies, Inc.
    Inventors: Stephen B. Krasulick, John Dallesasse
  • Patent number: 8592938
    Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 26, 2013
    Assignee: Avogy, Inc.
    Inventors: Madhan Raj, Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano
  • Publication number: 20130234278
    Abstract: The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Applicant: CREE, INC.
    Inventors: Helmut Hagleitner, Saptharishi Sriram
  • Patent number: 8530904
    Abstract: A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Treu, Ralf Siemieniec
  • Patent number: 8525288
    Abstract: In the diffusion region (3) of the second conductivity mode, a more highly doped region of the same conductivity mode (5) is introduced in such a manner that the region of the first conductivity mode (2) which is covered by the metal silicide (9) and of the second conductivity mode (3) are connected in a conductive manner. The region (3) of the second conductivity mode is diffused in such a manner that it reaches the more highly doped region (1) of the first doping type (1), with an outward diffusion of the doping from the more highly doped substrate layer (1) into the more weakly doped layer (2) of the same conductivity mode in the direction of the semiconductor surface taking place at the same time.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: September 3, 2013
    Assignee: Eris Technology Corporation
    Inventors: Michael Reschke, Hans-Jurgen Hillemann, Klaus Gunther
  • Patent number: 8513674
    Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 20, 2013
    Assignee: Showa Denko K.K.
    Inventors: Akihiko Sugai, Yasuyuki Sakaguchi
  • Patent number: 8502337
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8487396
    Abstract: A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8461632
    Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: June 11, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noriaki Tsuchiya, Yoichiro Tarui
  • Patent number: 8395140
    Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: March 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 8368165
    Abstract: A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H—SiC body.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: February 5, 2013
    Assignee: Siliconix Technology C. V.
    Inventor: Giovanni Richieri
  • Patent number: 8368166
    Abstract: A junction barrier Schottky diode has N-type well having a surface and first peak impurity concentration; P-type anode region in surface of the well having second peak impurity concentration; N-type cathode contact region in surface of the well and laterally spaced from a first wall of the anode region having third peak impurity concentration; and first N-type region in surface of the well and laterally spaced from second wall of the anode region having fourth impurity concentration. Center of the spaced region between the first N-type region and the second wall of the anode region has fifth peak impurity concentration. Ohmic contact is made to the anode region and cathode contact region. Schottky contact is made to the first N-type region. First and fifth peak impurity concentrations are less than the fourth peak impurity concentration. The fourth peak impurity concentration is less than the second and third peak impurity concentrations.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: February 5, 2013
    Assignee: Intersil Americas Inc.
    Inventors: Dev Alok Girdhar, Michael David Church
  • Patent number: 8324704
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 4, 2012
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8319310
    Abstract: A Schottky gate (27?, 27?) of a metal-semiconductor FET (20?, 20?) is formed on a semiconductor comprising substrate (21) by, etching a gate recess (36) so as to expose a slightly depressed surface (362) of the substrate (21), the etching step also producing surface undercut cavities (363) extending laterally under the etch mask (43) from the gate recess (36), then conformally coating the slightly depressed surface (362) with a first Schottky forming conductor (40?) and substantially also coating inner surfaces (366) of the surface undercut cavities (363), and forming a Schottky contact to the semiconductor comprising substrate (21), adapted when biased to control current flow in a channel (22) extending between source (23) and drain (24) of the FET (20?, 20?) under the gate recess (36).
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 27, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jenn Hwa Huang
  • Patent number: 8253216
    Abstract: A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts. Vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 28, 2012
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventor: TingGang Zhu
  • Patent number: 8232609
    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
  • Patent number: 8178940
    Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 15, 2012
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
  • Patent number: 8154028
    Abstract: An infrared external photoemissive detector can have an n-p heterojunction comprising an n-type semiconductor layer and a p-layer; the n-layer semiconductor comprising doped silicon embedded with nanoparticles forming Schottky barriers; and the p-layer is a p-type diamond film. The nanoparticles can be about 20-30 atomic percentage metal particles (such as silver) having an average particle size of about 5-10 nm. The p-layer can have a surface layer that has a negative electron affinity. The n-layer can be in the range of about 3 ?m to 10 ?m thick, and preferably about 3 ?m thick. The doped silicon can be doped with elements selected from the list consisting of phosphorus and antimony.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: April 10, 2012
    Assignee: Howard University
    Inventor: Clayton W. Bates, Jr.
  • Patent number: 8053853
    Abstract: An image sensor device includes a semiconductor substrate having a light-sensing region, and a first and second electrode embedded within the substrate. The first and second electrode forms an array of slits, the array of slits is configured to allow a wavelength of light to pass through to the light-sensing region. A method for making an image sensor device includes providing a semiconductor substrate, forming a plurality of pixels on the semiconductor substrate, and forming a plurality of slits embedded within each of the plurality of pixels. The plurality of slits is configured to allow a wavelength of light to pass through to each of the plurality of pixels.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiunn-Yih Chyan, Gwo-Yuh Shiau, Chia-Shiung Tsai
  • Patent number: 8018020
    Abstract: The invention provides a Schottky barrier diode in which a forward voltage is low, a backward leakage current is small, and a withstanding voltage of an element is high, by improving both the forward voltage VF and the backward leakage current IR. A Schottky barrier diode of the invention includes a semiconductor substrate whose surface is provided with a semiconductor layer of first conduction type, a plurality of semiconductor layers of second conduction type provided as junction barriers at a predetermined depth from the surface of the semiconductor layer of first conduction type, an annular shape guard ring comprised of a semiconductor layer of second conduction type to surround the semiconductor layer of second conduction type on the surface of the semiconductor layer of first conduction type, and a metal layer disposed so as to contact the semiconductor layer of first conduction type and the semiconductor layer of second conduction type.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: September 13, 2011
    Assignee: Panasonic Corporation
    Inventor: Kazuhiro Oonishi
  • Patent number: 8013414
    Abstract: A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: September 6, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: TingGang Zhu
  • Patent number: 7999346
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: August 16, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 7985615
    Abstract: The present invention relates to embodiments of TPV cell structures based on carbon nanotube and nanowire materials. One embodiment according to the present invention is a p-n junction carbon nanotube/nanowire TPV cell, which is formed by p-n junction wires. A second embodiment according to the present invention is a carbon nanotube/nanowire used as a p-type (or n-type), and using bulk material as the other complementary type to a form p-n junction TPV cell. A third embodiment according to the present invention uses a controllable Schottky barrier height between a one-dimensional nanowire and a metal contact to form the built-in potential of the TPV cells.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 26, 2011
    Assignee: The Regents of the University of California
    Inventors: Fei Liu, Ma Siguang, Kang L. Wang