Abstract: A PIN active pixel sensor array including self aligned encapsulated electrodes and a method for forming the same the method including forming an electrically conductive layer over a substrate; forming a first doped semiconducting layer over the conductive layer; photolithographically patterning and etching through a thickness portion of the first doped semiconducting layer and conductive layer to expose the substrate to form a plurality of spaced apart electrodes having an upper portion comprising the first doped semiconducting layer; blanket depositing a second doped semiconducting layer to cover the spaced apart electrodes including the exposed substrate; and, etching through at least a thickness portion of the second doped semiconducting layer.

Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.

Abstract: The present invention provides a Schottky Structure in gallium arsenide (GaAs) semiconductor device, which comprises a gallium arsenide (GaAs) semiconductor substrate, a titanium (Ti) layer on a surface of said gallium arsenide (GaAs) semiconductor substrate to form Schottky contact, a diffusion barrier layer on a surface of said titanium (Ti) layer to block metal diffusion, and a first copper layer on a surface of said diffusion barrier layer.

Abstract: A preferred embodiment of the present invention provides a Schottky diode formed from a conductive anode contact, a semiconductor junction layer supporting the conductive contact and a base layer ring formed around at least a portion of the conductive anode contact. In particular, the base layer ring has material removed to form layer material gap (e.g., a vacuum gap) adjacent to the conductive anode contact. A dielectric layer is also provided to form one boundary of the base layer material gap.

Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.

Abstract: A three-terminal semiconductor transistor device comprises a semiconductor base region in contact with a first electric terminal, a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region. The conductive emitter region is in contact with a second electric terminal. The three-terminal semiconductor transistor device further includes a conductive collector region in contact with the semiconductor base region, forming a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region. The conductive collector region is in contact with a third electric terminal. The tunneling currents through the first and the second Schottky barrier junctions are substantially controlled by the voltage of the semiconductor base region.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: A Schottky barrier field effect transistor has a gate electrode formed with a field plate in order to achieve a high withstanding voltage, where the thickness of the dielectric layer between the channel layer and the field plate, the distance between the Schottky contact and the drain and the length of the field plate falls within the range of 300 nanometers to 600 nanometers thick, the range from 800 nanometers to 3000 nanometers long and the range of the distance between the Schottky contact and the drain is plus or minus 400 nanometers, respectively, so that the distortion and the return-loss are improved without sacrifice of the withstanding voltage.

Abstract: The present invention provides a Schottky Structure in gallium arsenide (GaAs) semiconductor device, which comprises a gallium arsenide (GaAs) semiconductor substrate, a titanium (Ti) layer on a surface of said gallium arsenide (GaAs) semiconductor substrate to form Schottky contact, a diffusion barrier layer on a surface of said titanium (Ti) layer to block metal diffusion, and a first copper layer on a surface of said diffusion barrier layer.

Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: A preferred embodiment of the present invention provides a Schottky diode (100) formed from a conductive anode contact (102), a semiconductor junction layer (104) supporting the conductive contact (102) and a base layer ring (108) formed around at least a portion of the conductive anode contact (102). In particular, the base layer ring (108) has material removed to form a base layer material gap (118) (e.g., a vacuum gap) adjacent to the conductive anode contact (102). A dielectric layer (110) is also provided to form one boundary of the base layer material gap (118).

Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.

Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: The invention relates to a semiconductor component with adjacent Schottky (5) and pn (9) junctions positioned in a drift area (2, 10) of a semiconductor material. The invention also relates to a method for producing said semiconductor component.

Abstract: A Schottky electrode is formed of an alloy, which is composed of two or more kinds of metal materials in combinations that provide different Schottky barrier heights with respect to a semiconductor and that form no intermetallic compound.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: A microwave monolithic integrated circuit comprises a T-shaped gate electrode including a Schottky gate electrode formed on a first region of a compound semiconductor substrate, a pair of ohmic electrodes making an ohmic contact with a surface of the substrate in the first region at respective sides of the T-shaped gate electrode, a lower capacitor electrode pattern formed on a second region of the compound semiconductor substrate with a composition substantially identical with a low-resistance, top electrode constituting the T-shaped gate electrode on the Schottky gate electrode, a dielectric film formed on the lower electrode pattern, and an upper electrode pattern formed on the dielectric film.

Abstract: The specification describes a Schottky barrier device with a distributed guard ring where the guard ring is spaced from the barrier by an MOS gate so that the guard ring and barrier are connected at low bias by an inversion layer. According to the invention, the MOS gate is used to precisely space the guard ring from the Schottky barrier.

Abstract: On a Schottky tunnel junction with Schottky metal as a source, an extremely thin and a high density impurities semiconductor layer having a conduction type different from that of a high density impurities semiconductor constituting the base junction is formed, and height and width of this extremely thin high density impurities semiconductor layer are controlled by adjusting a voltage loaded to a MOS gate formed on this tunnel junction section, so that a main portion of the drain current comprises a carrier passing through the barrier because of the tunnel effect and a carrier moving over this barrier. In addition, a CMOS structure is made to prepare a three-dimensionally or three-dimensionally integrated circuit.

Abstract: A method of producing a semiconductor device includes a semiconductor substrate and a gate embedding layer. A pair of side walls made of insulating layers having a width are formed on the inner surface of a first opening and the gate embedding layer is formed by using the pair of side walls and a first insulating layer as masks so that the embedded portion and the first extending portion are self-aligned and, consequently, the first extending portion is symmetrical with respect to the embedded portion. Accordingly, the first extending portion of the gate electrode is offset toward the drain electrode or source electrode.

Abstract: A diode for sensing hydrogen and hydrocarbons and the process for manufacturing the diode are disclosed. The diode is a Schottky diode which has a palladium chrome contact on the C-face of an n-type 6H Silicon carbide epilayer. The epilayer is grown on the C-face of a 6H silicon carbide substrate. The diode is capable of measuring low concentrations of hydrogen and hydrocarbons at high temperatures, for example, 800° C. The diode is both sensitive and stable at elevated temperatures.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.

Abstract: This invention discloses a Schottky barrier rectifier formed in a semiconductor chip of a first conductivity type having a cathode electrode connected thereto near a bottom surface of the semiconductor chip. The Schottky rectifier further includes an epitaxial layer of the first conductivity type of a reduced doping concentration than the semiconductor chip near a top surface of the semiconductor chip. The Schottky rectifier further includes a high resistivity region disposed near peripheral edges of the semiconductor chip containing a reduced dopant concentration than the epitaxial layer. The Schottky rectifier further includes an anode electrode defined by a conductive layer disposed on top over the epitaxial layer wherein the conductive layer having all peripheral edges disposed on top of the high resistivity region. In a preferred embodiment, e.g.

Abstract: In this invention, a new, simple and small-size hydrogen-sensitive palladium (Pd) membrane/semiconductor Schottky diode sensor has been developed and fabricated. First, a high quality undoped GaAs buffer layer and an n-type GaAs epitaxial layer with the carrier concentration of 2.times.10.sup.17 cm.sup.31 3 is grown by molecular beam epitaxy (MBE) on a semi-insulated GaAs substrate. Then a thin Pd membrane is evaporated on the surface of the n-type GaAs epitaxial layer by the vacuum evaporation technique. It is well-known that palladium metal has excellent selectivity and sensitivity on hydrogen gas. When hydrogen gas diffuses to the Pd membrane surface, the hydrogen molecules will dissociate into hydrogen atoms. Some of the hydrogen atoms diffuse through the thin metal layer and form the palladium hydride near the metal-semiconductor interface. The hydride may effectively lower the work function of Pd metal.

Abstract: The invention concerns the fabrication and characterization of vertical geometry transparent Schottky barrier ultraviolet detectors based on n.sup.- /n.sup.+ -GaN and AlGaN structures grown over sapphire substrates. Mesa geometry devices of different active areas were fabricated and characterized for spectral responsitivity, speed and noise characteristics. The invention also concerns the fabrication and characterization of an 8.times.8 Schottky barrier photodiode array on GaN with a pixel size of 200 .mu.m by 200 .mu.m.

Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.

Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.

Abstract: In an HEMT, a channel forming layer is arranged above a semi-insulating substrate via a buffer layer. A spacer layer is arranged on the channel forming layer and an electron supplying layer and a Schottky contact layer are sequentially arranged on the spacer layer. A diffusion preventing layer, for preventing a metal element of a gate electrode from diffusing into the channel forming layer, is arranged in the Schottky contact layer.

Abstract: In the manufacture of a field effect transistor which can improve the breakdown voltage between a gate and a drain and can also prevent a gate lag, an oxide film is formed or wet cleaning is carried out over the semiconductor surface of an inter-source-gate region while a nitride film is formed or dry cleaning is carried out over the semiconductor surface of an inter-gate-drain region, in order that surface traps in the semiconductor surface of the inter-gate-drain region, which is not covered with electrode metal, is greater in number than those in the semiconductor surface of the inter-source-gate region.

Abstract: A semiconductor device has a metal pattern composed of a material reacting on water and a metal protective film formed between an intrusion path of water and the metal pattern on the surface of a part of the metal pattern. The metal pattern is composed of a refractory metal, a refractory metal compound or aluminum, and the metal protective film is formed of any of gold, platinum, palladium, gold alloy, platinum alloy, palladium alloy and lanthanum hexaboron.

Abstract: An ohmic contact electrode for a semiconductor device which has a low contact resistance and high stability. The ohmic contact electrode includes: a semiconductor substrate; an atomic doping layer developed on the semiconductor substrate wherein the atomic doping layer is formed by doping impurities such that an energy level of the layer is higher than a Fermi level; a semiconductor layer developed on the atomic doping layer wherein the semiconductor layer is formed of the same material as in the semiconductor substrate; a metal electrode formed on the semiconductor layer for establishing an electric connection with the semiconductor substrate; wherein the semiconductor layer has a thickness sufficient for carriers to transfer between the metal electrode and the atomic doping layer by tunneling through the semiconductor layer.

Abstract: A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET.

Abstract: In a Schottky barrier diode, concentration of an electrical field at an edge of an insulation layer is suppressed to improve the reverse breakdown voltage. An n- layer of a compound semiconductor substrate having an n+ layer and the n- layer is configured in the form of a mesa. An insulation layer is formed on at least a skirt portion and a slant portion of the mesa. An anode is formed on the insulation layer and n- layer, and a cathode is formed on the n+ layer. Thus, concentration of an electrical field at an edge of the insulation layer is canceled at least in part by an electrical field generated at the anode on the slant portion to improve the reverse breakdown voltage.

Abstract: A semiconductor device includes a compound semiconductor body having a recess, the recess having a bottom and a hollow, and a refractory metal gate electrode having a lower portion within the hollow. The compound semiconductor body includes a compound semiconductor substrate; a channel layer including a compound semiconductor of a first conductivity type, the channel layer being located on the substrate between the gate electrode and the substrate; first active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor of the first conductivity type located on regions of the substrate sandwiching the recess.

Abstract: A Schottky barrier diode having improved breakdown characteristics has an n.sup.+ semiconductor layer and an n.sup.- semiconductor layer provided on the n.sup.+ semiconductor layer. The n.sup.- semiconductor layer is configured to form a mesa. An insulating layer is formed so as to expose the upper surface of the mesa. An anode electrode is provided on the exposed surface and a side surface of the mesa, while a cathode is electrically connected to the n.sup.+ layer. A plasma treated layer is provided in the n.sup.- semiconductor layer so as to extend inwardly from at least a portion of the side surface of the mesa.

Abstract: A structure and method for making HEMTs with a gate metal having a layer comprising titanium, a layer comprising vanadium over the layer comprising titanium, and a layer comprising gold over the layer comprising vanadium. Such HEMTs are insensitive to hydrogen.

Abstract: A power GaAs Schottky diode with a chemically deposited Ni barrier having a reverse breakdown voltage of 140 V, a forward voltage drop at 50 A/cm.sup.2 of 0.7 V at 23.degree. C., 0.5 V at 150.degree. C. and 0.3 V at 250.degree. C. and having a reverse leakage current density at -50 V of 0.1 .mu.A/cm.sup.2 at 23.degree. C. and 1 mA/cm.sup.2 at 150.degree. C. The high-voltage high-speed power Schottky semiconductor device is made by chemically depositing a nickel barrier electrode on a semiconductor which includes gallium arsenide and then etching the device to create side portions which are treated and protected to create the Schottky device.

Abstract: A silicon carbide trench MOSFET is provided that includes a first conductivity type semiconductor substrate made of silicon carbide. A first conductivity type drift layer and a second conductivity type base layer, both made of silicon carbide, are sequentially formed by epitaxial growth on the semiconductor substrate. The first conductivity type drift layer has a lower impurity concentration than the semiconductor substrate. A first conductivity type source region is formed in a part of a surface layer of the second conductivity type base layer. A gate electrode is received through an insulating film, in a first trench extending from a surface of the first conductivity type source region to reach the first conductivity type drift layer. A Shottky electrode disposed on an inner surface of a second trench having a greater depth than the first trench.

Abstract: A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed.

Abstract: To provide a Schottky junction device having a super-lattice arranged in the Schottky interface in order to secure a high Schottky barrier and at the same time showing a high speed response by resolving the phenomenon of piled-up holes at the upper edge of the valence band, while maintaining the height of the Schottky barrier. A Schottky junction device having a Schottky junction of a semiconductor and a metal and a superlattice on the interface of the semiconductor and the metal, wherein the upper edge of the valence band of said superlattice is varied to show a turn to a specific direction. The phenomenon of hole-piling up at the upper end of the valence band is resolved while maintaining the height of the Schottky barrier and consequently such a Schottky junction device shows an excellent high speed response.