To Compound Semiconductor Patents (Class 257/472)
  • Patent number: 10957816
    Abstract: An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Jack O. Chu, Christos Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Devendra K. Sadana
  • Patent number: 10930797
    Abstract: A Schottky barrier diode includes: an n? type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n? type layer and separated from each other; an anode disposed on the n? type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate. The p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n? type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: February 23, 2021
    Assignee: HYUNDAI MOTOR COMPANY, LTD.
    Inventors: Dae Hwan Chun, Youngkyun Jung, Nack Yong Joo, Junghee Park, Jong Seok Lee
  • Patent number: 10896970
    Abstract: A process of forming a field effect transistor (FET) of a type of high electron mobility transistor (HEMT) reducing damages caused in a semiconductor layer is disclosed. The process carries out steps of: (a) depositing an insulating film on a semiconductor stack; (b) depositing a conductive film on the insulating film; (c) forming an opening in the conductive film and the insulating film by a dry-etching using ions of reactive gas to expose a surface of the semiconductor stack; and (d) forming a gate electrode to be in contact with the surface of the semiconductor stack through the opening, the gate electrode filling the opening in the conductive film and the insulating film.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tadashi Watanabe, Hajime Matsuda
  • Patent number: 10367053
    Abstract: Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yasuhiko Tanuma, Takashi Ishihara
  • Patent number: 10367090
    Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 30, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Konishi, Ryuusei Fujita, Kazuki Tani, Akio Shima
  • Patent number: 10192808
    Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: January 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chuan Hu, Chun-Hung Chen, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Ming-Tse Lin
  • Patent number: 10153242
    Abstract: Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 11, 2018
    Assignee: Kulite Semiconductor Products, Inc.
    Inventor: Sorin Stefanescu
  • Patent number: 9748230
    Abstract: A semiconductor apparatus having a trench Schottky barrier Schottky diode, which includes: a semiconductor volume of a first conductivity type, which semiconductor volume has a first side covered with a metal layer, and at least one trench extending in the first side and at least partly filled with metal. At least one wall segment of the trench, and/or at least one region, located next to the trench, of the first side covered with the metal layer, is separated by a layer, located between the metal layer and the semiconductor volume, made of a first semiconductor material of a second conductivity type.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 29, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 9704949
    Abstract: A charge-balanced (CB) diode may include one or more CB layers. Each CB layer may include an epitaxial layer having a first conductivity type and a plurality of buried regions having a second conductivity type. Additionally, the CB diode may include an upper epitaxial layer having the first conductivity type that is disposed adjacent to an uppermost CB layer of the one or more CB layers. The upper epitaxial layer may also include a plurality of junction barrier (JBS) implanted regions having the second conductivity type. Further, the CB diode may include a Schottky contact disposed adjacent to the upper epitaxial layer and the plurality of JBS implanted regions.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 11, 2017
    Assignee: General Electric Company
    Inventors: Reza Ghandi, Peter Almern Losee, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld
  • Patent number: 9577046
    Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichi Hori, Tsuyoshi Oota, Hiroshi Kono, Atsuko Yamashita
  • Patent number: 9478645
    Abstract: Provided is a longitudinal bidirectional device in which current flows in a layering direction of a semiconductor layered portion formed on a front surface of a substrate, the bidirectional device comprising a first semiconductor element that includes a first channel and is formed on the semiconductor layered portion; and a second semiconductor element that includes a second channel and is provided on the substrate side of the first semiconductor element within the semiconductor layered portion. The first semiconductor element further includes a first control electrode that controls the first channel and that is formed on a surface of the semiconductor layered portion that faces away from the substrate, and the second semiconductor element is formed on at least a portion of the surface of the semiconductor layered portion on which the first control electrode is formed and includes a second control electrode that controls the second channel.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 25, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsunori Ueno
  • Patent number: 9324827
    Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Jerome Ciavatti
  • Patent number: 9318324
    Abstract: A manufacturing method of an SiC epitaxial substrate of an embodiment includes performing a first and a second process alternately to form an n type SiC layer, the first process forming a first SiC layer with an epitaxial growth process by using a first source gas containing an n type impurity, and the second process forming a second SiC layer with an epitaxial growth process by using a second source gas containing the n type impurity, the second source gas having a higher atomic ratio between C (carbon) and Si (silicon) (C/Si) than that of the first source gas, a thickness of the second SiC layer being smaller than a thickness of the first SiC layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Chiharu Ota, Ryosuke Iijima, Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 9035414
    Abstract: A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Publication number: 20150130013
    Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Infineon Technologies AG
    Inventors: Holger Hüsken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Rösner, Holger Schulze
  • Patent number: 9029975
    Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: May 12, 2015
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Patent number: 9006584
    Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan, David Larkin, Dhaval Atul Saraiya
  • Patent number: 8994140
    Abstract: A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 31, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 8969921
    Abstract: A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Yuichi Minoura
  • Patent number: 8969993
    Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8969994
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli
  • Patent number: 8941093
    Abstract: A first electrode, an intrinsic first compound semiconductor layer over the first electrode, a second compound semiconductor layer whose band gap is smaller than that of the first compound semiconductor layer on the first compound semiconductor layer, and a second electrode over the second compound semiconductor layer are provided.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Tadahiro Imada
  • Patent number: 8940593
    Abstract: An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Jamal Ramdani
  • Patent number: 8937319
    Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 20, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Yusuke Maeyama, Ryohei Osawa, Yoshitaka Araki, Yoshiyuki Watanabe
  • Patent number: 8933532
    Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 13, 2015
    Assignee: Avogy, Inc.
    Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
  • Patent number: 8928108
    Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: January 6, 2015
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Patent number: 8916946
    Abstract: The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 23, 2014
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Yoshiyuki Doi, Yoshifumi Muramoto, Takaharu Ohyama
  • Patent number: 8912622
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate, a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer, a second-conductivity-type bottom layer, a Schottky metal, and a cathode electrode. The first first-conductivity-type semiconductor layer is provided on the semiconductor substrate and has a lower first-conductivity-type impurity concentration than the semiconductor substrate. The second first-conductivity-type semiconductor layer is provided on the first first-conductivity-type semiconductor layer and has a higher first-conductivity-type impurity concentration than the first first-conductivity-type semiconductor layer. The Schottky metal is provided on the second first-conductivity-type semiconductor layer. The Schottky metal contacts with partly the first first-conductivity-type semiconductor layer.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Arai, Takashi Tabuchi
  • Patent number: 8901698
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8901699
    Abstract: Integral structures that block the current conduction of the built-in PiN diode in a junction barrier Schottky (JBS) structure are provided. A Schottky diode may be incorporated in series with the PiN diode, where the Schottky diode is of opposite direction to that of the PiN diode. A series resistance or and insulating layer may be provided between the PiN diode and a Schottky contact. Silicon carbide Schottky diodes and methods of fabricating silicon carbide Schottky diodes that include a silicon carbide junction barrier region disposed within a drift region of the diode are also provided. The junction barrier region includes a first region of silicon carbide having a first doping concentration in the drift region of the diode and a second region of silicon carbide in the drift region and disposed between the first region of silicon carbide and a Schottky contact of the Schottky diode. The second region is in contact with the first region of silicon carbide and the Schottky contact.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: December 2, 2014
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal
  • Patent number: 8878329
    Abstract: A high voltage device having a Schottky diode integrated with a MOS transistor includes a semiconductor substrate a Schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the Schottky diode, and a control gate covering a portion of the Schottky diode and the first doped region positioned on the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 4, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Min-Hsuan Tsai
  • Publication number: 20140312355
    Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: AVOGY, INC.
    Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Hui Nie, Quentin Diduck, Ozgur Aktas
  • Patent number: 8866151
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first region of a second conductivity type selectively provided in a first major surface of the semiconductor layer, a second region of the second conductivity type selectively provided in the first major surface and connected to the first region, a first electrode provided in contact with the semiconductor layer and the first region, a second electrode provided in contact with the second region, and a third electrode electrically connected to a second major surface of the semiconductor layer opposite to the first major surface.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Noda, Ryoichi Ohara, Kenya Sano, Toru Sugiyama
  • Patent number: 8866134
    Abstract: Provided are a light-emitting device and a photovoltaic cell having excellent characteristics. A light-emitting device (10) includes a cathode (34), an anode (32), a light-emitting layer (50) interposed between the cathode (34) and the anode (32), and an electron injection layer (44) provided between the cathode (34) and the light-emitting layer (50) and connected to the cathode (34), in which at least one of the anode (32) and the cathode (34) contains a conductive material having an aspect ratio of 1.5 or more, and the electron injection layer (44) contains an organic compound having at least one of an ionic group and a polar group.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Takayuki Iljima, Kenta Tanaka, Masanobu Tanaka, Hideyuki Higashimura
  • Publication number: 20140264714
    Abstract: The invention provides a power semiconductor device including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm?2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and a power semiconductor structure comprising at least one doped AlxGa1?xN layer overlying the aluminum nitride single crystalline substrate.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: HEXATECH, INC.
    Inventors: Baxter Moody, Seiji Mita, Jinqiao Xie
  • Patent number: 8829613
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • Patent number: 8822311
    Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 2, 2014
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown, Donald R. Disney
  • Patent number: 8816399
    Abstract: A semiconductor device includes: an electron transit layer formed on a substrate and of a group III nitride-based compound semiconductor; an electron supply layer formed on the electron transit layer and of a group III nitride-based compound semiconductor having a higher band gap energy than the transit layer; a field plate layer formed on the supply layer, formed of a non-p-type group III nitride-based compound semiconductor, and having a lower band gap energy than the supply layer; a first electrode forming an ohmic contact with a two-dimensional electron gas layer in the transit layer at an interface thereof with the supply layer; and a second electrode forming a Schottky contact with the electron gas layer. The second electrode forms an ohmic contact, at a side wall of the field plate layer, with two-dimensional hole gas in the field plate layer at an interface thereof with the supply layer.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: August 26, 2014
    Assignees: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventor: Yoshihiro Ikura
  • Patent number: 8809987
    Abstract: Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: August 19, 2014
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Jing Chen, Li Yuan, Hongwei Chen, Chunhua Zhou
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8772901
    Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 8, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Madhur Bodbe
  • Patent number: 8766395
    Abstract: A device includes a Schottky barrier formed by a metal-semiconductor junction between a semiconductor nanowire and a metal contact. The metal contact at least partly encloses a circumferential area of each nanowire along the length thereof. The nanowire includes a low doped region that is part of the metal-semiconductor junction. The device can be fabricated using a method where two different growth modes are used, the first step including axial growth from a substrate giving a suitable template for formation of the metal-semiconductor junction, and the second step including radial growth enabling control of the doping levels in the low doped region.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 1, 2014
    Assignee: Qunano AB
    Inventor: Steven Konsek
  • Patent number: 8759816
    Abstract: A composite material is described. The composite material comprises semiconductor nanocrystals, and organic molecules that passivate the surfaces of the semiconductor nanocrystals. One or more properties of the organic molecules facilitate the transfer of charge between the semiconductor nanocrystals. A semiconductor material is described that comprises p-type semiconductor material including semiconductor nanocrystals. At least one property of the semiconductor material results in a mobility of electrons in the semiconductor material being greater than or equal to a mobility of holes. A semiconductor material is described that comprises n-type semiconductor material including semiconductor nanocrystals. At least one property of the semiconductor material results in a mobility of holes in the semiconductor material being greater than or equal to a mobility of electrons.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: June 24, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Keith William Johnston, Andras Geza Pattantyus-Abraham, Jason Paul Clifford
  • Patent number: 8716717
    Abstract: A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Naruhisa Miura, Yasuhiro Kagawa, Kenji Hamada, Yoshiyuki Nakaki
  • Patent number: 8704322
    Abstract: The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 22, 2014
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Yoshiyuki Doi, Yoshifumi Muramoto, Takaharu Ohyama
  • Publication number: 20140091424
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer and has an opening formed thereon; and an electrode that fills the opening, that is brought into contact with the compound semiconductor layer, and that is formed on the protective insulating film, in which an orientation state of a contact portion between the electrode and the compound semiconductor layer and an orientation state of a contact portion between the electrode and the protective insulating film are the same.
    Type: Application
    Filed: July 16, 2013
    Publication date: April 3, 2014
    Inventor: Kozo MAKIYAMA
  • Publication number: 20140061846
    Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.
    Type: Application
    Filed: August 21, 2013
    Publication date: March 6, 2014
    Applicant: Sony Corporation
    Inventors: Shigeru Kanematsu, Masashi Yanagita
  • Publication number: 20140054680
    Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 27, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Takao NAKAMURA, Hiroshi AMANO
  • Publication number: 20140048902
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Applicant: AVOGY , INC.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edward, Hui Nie, Isik C. Kizilyalli
  • Publication number: 20140048903
    Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming one or more p-type regions in the n-type GaN epitaxial layer by using a first ion implantation. At least one of the one or more p-type regions includes an edge termination structure.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: AVOGY, INC.
    Inventors: Andrew Edwards, Hui Nie, Isik Kizilyalli, Dave Bour