With Means To Prevent Edge Breakdown Patents (Class 257/483)
-
Patent number: 8115270Abstract: An electrostatic discharge protection device includes a first bipolar transistor having a collector terminal connected with a first power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with a second power supply terminal, a second bipolar transistor having a collector terminal connected with the second power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with the first power supply terminal, one of the first and second bipolar transistors ensuring a continuity between the collector terminal and emitter terminal under such conditions that a potential difference between the first or second power supply terminal and the input/output terminal is lower than a breakdown voltage at a PN junction between the emitter terminal and the base terminal of the other bipolar transistor.Type: GrantFiled: March 4, 2011Date of Patent: February 14, 2012Assignee: Renesas Electronics CorporationInventor: Takayuki Nagai
-
Publication number: 20110227135Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
-
Patent number: 7973381Abstract: A schottky diode of the trench variety which includes a trench termination having a thick insulation layer that is thicker than the insulation layer inside the trenches in its active region.Type: GrantFiled: September 8, 2004Date of Patent: July 5, 2011Assignee: International Rectifier CorporationInventor: Davide Chiola
-
Patent number: 7939905Abstract: According to an embodiment of the present invention, an electrostatic breakdown protection method protects a semiconductor device from a surge current impressed between a first terminal and a second terminal, the semiconductor device including: a diode impressing a forward-bias current from the first terminal to the second terminal; and a bipolar transistor impressing a current in a direction from the second terminal to the first terminal under an ON state, a continuity between a collector terminal and an emitter terminal of the bipolar transistor being attained before a potential difference between the first terminal and the second terminal reaches such a level that the diode is broken down.Type: GrantFiled: June 4, 2007Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventor: Takayuki Nagai
-
Patent number: 7923911Abstract: Metal induced polycrystallized silicon is used as the anode in a light emitting device, such as an OLED or AMOLED. The polycrystallized silicon is sufficiently non-absorptive, transparent and made sufficiently conductive for this purpose. A thin film transistor can be formed onto the polycrystallized silicon anode, with the silicon anode acting as the drain of the thin film transistor, thereby simplifying production.Type: GrantFiled: December 19, 2008Date of Patent: April 12, 2011Assignee: The Hong Kong University of Science and TechnologyInventors: Hoi Sing Kwok, Man Wong, Zhiguo Meng, Jiaxin Sun, Xiuling Zhu
-
Patent number: 7923804Abstract: A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure.Type: GrantFiled: February 9, 2009Date of Patent: April 12, 2011Assignee: MaxPower Semiconductor Inc.Inventors: Jun Zeng, Mohamed N. Darwish, Shih-Tzung Su
-
Patent number: 7898056Abstract: Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.Type: GrantFiled: December 9, 2008Date of Patent: March 1, 2011Assignee: Alvand Technology, Inc.Inventors: Mansour Keramat, Syed S. Islam, Mehrdad Heshami
-
Patent number: 7829970Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.Type: GrantFiled: April 22, 2008Date of Patent: November 9, 2010Assignee: Intersil Americas Inc.Inventors: Dev Alok Girdhar, Michael David Church
-
Patent number: 7825017Abstract: A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film.Type: GrantFiled: March 18, 2009Date of Patent: November 2, 2010Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki KaishaInventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Masaki Konishi
-
Patent number: 7821095Abstract: In one embodiment, a Schottky diode is formed on a doped region having a thickness less than about eighteen microns.Type: GrantFiled: July 14, 2006Date of Patent: October 26, 2010Assignee: Semiconductor Components Industries, LLCInventors: Rogelio J. Moreno, Linghui Chen
-
Patent number: 7781869Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.Type: GrantFiled: August 4, 2006Date of Patent: August 24, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoki Inoue, Koichi Sugiyama, Hideaki Ninomiya, Tsuneo Ogura
-
Patent number: 7741693Abstract: Trenches are formed in a semiconductor substrate, where the trenches include an outer trench and multiple inner trenches within the outer trench. A metal-oxide semiconductor (MOS) device and a trench MOS Schottky barrier (TMBS) device are also formed in the semiconductor substrate using the trenches. The MOS device could include the outer trench, and the TMBS device could include the inner trenches. At least one of the inner trenches may contact the outer trench, and/or at least one of the inner trenches may be electrically isolated from the outer trench. The MOS device could represent a trench vertical double-diffused metal-oxide semiconductor (VDMOS) device, and the TMBS device may be monolithically integrated with the trench VDMOS device in the semiconductor substrate. A guard ring that covers portions of the inner trenches and that is open over other portions of the inner trenches could optionally be formed in the semiconductor substrate.Type: GrantFiled: November 16, 2007Date of Patent: June 22, 2010Assignee: National Semiconductor CorporationInventor: Terry Dyer
-
Patent number: 7692262Abstract: A vertical rectifying and protection power diode, formed in a lightly-doped semiconductor layer of a first conductivity type, resting on a heavily-doped substrate of the first conductivity type, having a first ring-shaped region, of the first conductivity type more heavily-doped than the layer and more lightly doped than the substrate, surrounding an area of the layer and extending to the substrate; and a second ring-shaped region, doped of the second conductivity type, extending at the surface of the first region and on either side thereof; a first electrode having a thin layer of a material capable of forming a Schottky diode with the layer, resting on the area of the layer and on at least a portion of the second ring-shaped region with which it forms an ohmic contact.Type: GrantFiled: July 7, 2004Date of Patent: April 6, 2010Assignee: STMicroelectronics S.A.Inventors: Jean-Luc Morand, Emmanuel Collard, André Lhorte
-
Patent number: 7612426Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.Type: GrantFiled: November 15, 2005Date of Patent: November 3, 2009Assignee: Panasonic CorporationInventors: Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
-
Patent number: 7602036Abstract: A trench type junction barrier rectifier has silicon dioxide spacers at the bottom of trenches in a silicon surface and beneath the bottom of a conductive polysilicon filler in the trench. A Schottky barrier electrode is connected to the tops of the mesas and the tops of the polysilicon fillers. Further oxide spacers may be formed in the length of the polysilicon fillers.Type: GrantFiled: March 2, 2007Date of Patent: October 13, 2009Assignee: International Rectifier CorporationInventors: Carmelo Sanfilippo, Rossano Carta
-
Publication number: 20090236679Abstract: An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Inventors: Puo-Yu Chiang, Tsai Chun Lin, Chih-Wen Albert Yao, David Ho
-
Patent number: 7576011Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.Type: GrantFiled: May 11, 2007Date of Patent: August 18, 2009Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
-
Patent number: 7498651Abstract: Disclosed are a variety of junction termination structures for high voltage semiconductor power devices. The structures are specifically aimed at providing a high breakdown voltage while being constructed with a minimal number of process steps. The combination of an RIE etch and/or implantation and anneal process with a finely patterned mesh provides the desired radial gradient for maximum breakdown voltage. The structures provide control of both the conductivity and charge density within the region. These structures can beneficially be applied to all high voltage semiconductor device structures, but are of particular interest for wide bandgap devices as they tend to have very high breakdown fields and scaled dimensions of the depletion layer width.Type: GrantFiled: November 23, 2005Date of Patent: March 3, 2009Assignee: Microsemi CorporationInventor: Bart Van Zeghbroeck
-
Patent number: 7388272Abstract: A chip package including a carrier, a chip, a stiffener and a molding compound is provided. A producing method of the chip package includes the steps of disposing a bottom surface of the chip on the carrier; covering an edge of a top surface of the chip with the stiffener for protecting the edge; then wire bonding the top surface of the chip with the carrier; and forming the molding compound for encapsulating the chip, the stiffener and parts of the carrier.Type: GrantFiled: December 12, 2005Date of Patent: June 17, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Yi-Chuan Ding
-
Patent number: 7307329Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.Type: GrantFiled: July 8, 2004Date of Patent: December 11, 2007Assignee: Infineon Technologies AGInventors: Cartens Ahrens, Ulf Bartl, Bernd Eisener, Wolfgang Hartung, Christian Herzum, Raimund Peichl, Stefan Pompl, Hubert Werthmann
-
Patent number: 7265436Abstract: A method of forming an improved seal ring structure is described. A continuous metal seal ring is formed along a perimeter of a die wherein the metal seal ring is parallel to the edges of the die and sloped at the corner of the die so as not to have a sharp corner and wherein the metal seal ring has a first width at the corners and a second width along the edges wherein the first width is wider than the second width.Type: GrantFiled: February 17, 2004Date of Patent: September 4, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Kuan-Shou Chi
-
Patent number: 7211500Abstract: A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.Type: GrantFiled: September 27, 2004Date of Patent: May 1, 2007Assignee: United Microelectronics Corp.Inventors: Kuo-Ming Chen, Kun-Chih Wang, Hermen Liu, Paul Chen, Kai-Kuang Ho
-
Patent number: 7199442Abstract: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.Type: GrantFiled: July 15, 2004Date of Patent: April 3, 2007Assignee: Fairchild Semiconductor CorporationInventor: Praveen M. Shenoy
-
Patent number: 7176537Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 ? on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 ?.Type: GrantFiled: May 23, 2005Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Chung-Hu Ke, Min-Hwa Chi
-
Patent number: 7129558Abstract: A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.Type: GrantFiled: November 6, 2002Date of Patent: October 31, 2006Assignee: International Rectifier CorporationInventor: Slawomir Skocki
-
Patent number: 7112865Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.Type: GrantFiled: March 3, 2005Date of Patent: September 26, 2006Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
-
Patent number: 7102207Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.Type: GrantFiled: April 4, 2003Date of Patent: September 5, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tomoki Inoue, Koichi Sugiyama, Hideaiki Ninomiya, Tsuneo Ogura
-
Patent number: 7078783Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.Type: GrantFiled: January 29, 2004Date of Patent: July 18, 2006Assignee: STMicroelectronics S.A.Inventor: Frédéric Lanois
-
Patent number: 7071525Abstract: A Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region.Type: GrantFiled: January 27, 2004Date of Patent: July 4, 2006Assignee: International Rectifier CorporationInventors: Davide Chiola, Kohji Andoh, Silvestro Fimiani
-
Patent number: 6936905Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n? drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n? drift layer; a pair of field oxide regions and termination region formed into the n? drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer.Type: GrantFiled: April 24, 2003Date of Patent: August 30, 2005Assignees: Chip Integration Tech Co., Ltd.Inventor: Shye-Lin Wu
-
Patent number: 6855999Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. An insulating layer is deposited over a thermal oxide layer provided overlying a silicon semiconductor substrate. A contact opening is etched through the insulating layer and the thermal oxide layer to the silicon substrate. The contact opening is overetched whereby a shallow trench is formed within the silicon substrate underlying the contact opening wherein the shallow trench has a bottom and sidewalls comprising the silicon substrate. A first metal layer is deposited over the insulating layer and within the contact opening and within the shallow trench.Type: GrantFiled: September 6, 2002Date of Patent: February 15, 2005Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: Jei-Fung Hwang, Ruey-Hsing Liou, Chih-Kang Chiu
-
Patent number: 6798034Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.Type: GrantFiled: August 7, 2002Date of Patent: September 28, 2004Assignee: Diglrad CorporationInventor: Lars S. Carlson
-
Patent number: 6787871Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: GrantFiled: October 30, 2002Date of Patent: September 7, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
-
Patent number: 6740951Abstract: A Schottky rectifier includes a semiconductor structure having first and second opposing faces each extending to define an active semiconductor region and a termination semiconductor region. The semiconductor structure includes a cathode region of the first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face. The drift region has a lower net doping concentration than that of the cathode region. A plurality of trenches extends from the second face into the semiconductor structure and defines a plurality of mesas within the semiconductor structure. At least one of the trenches is located in each of the active and the termination semiconductor regions. A first insulating region is located adjacent the semiconductor structure in the plurality of trenches. A second insulating region electrically isolates the active semiconductor region from the termination semiconductor region.Type: GrantFiled: May 22, 2001Date of Patent: May 25, 2004Assignee: General Semiconductor, Inc.Inventors: Yan Man Tsui, Fwu-Iuan Hshieh, Koon Chong So
-
Publication number: 20040089908Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.Type: ApplicationFiled: October 29, 2003Publication date: May 13, 2004Inventors: John Charles Desko, Michael J. Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R. Jones, Thomas J. Krutsick, John Michael Siket, Brian Eric Thompson, Steven W. Wallace
-
Patent number: 6734520Abstract: A semiconductor component includes a first layer and at least one adjacent semiconductor layer or metallic layer, which forms a rectifying junction with the first layer. Further semiconductor layers and metallic layers are provided for contacting the component. Insulating or semi-insulating structures are introduced into the first layer in a plane parallel to the rectifying junction. These structures are shaped like dishes with their edges bent up towards the rectifying junction. A method of producing such a semiconductor component is also provided.Type: GrantFiled: May 18, 2001Date of Patent: May 11, 2004Assignee: Infineon Technologies AGInventors: Holger Kapels, Dieter Silber, Robert Plikat
-
Patent number: 6717229Abstract: A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.Type: GrantFiled: March 11, 2002Date of Patent: April 6, 2004Assignee: Fabtech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski, Wayne A. Smith
-
Patent number: 6707127Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.Type: GrantFiled: August 31, 2000Date of Patent: March 16, 2004Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Max Chen, Koon Chong So, Yan Man Tsui
-
Patent number: 6707128Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.Type: GrantFiled: June 10, 2002Date of Patent: March 16, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kouji Moriguchi, Yoshitaka Hokomoto
-
Patent number: 6670688Abstract: A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.Type: GrantFiled: June 7, 2002Date of Patent: December 30, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Satoh, Eisuke Suekawa
-
Patent number: 6653707Abstract: A preferred embodiment of the present invention provides a Schottky diode (100) formed from a conductive anode contact (102), a semiconductor junction layer (104) supporting the conductive contact (102) and a base layer ring (108) formed around at least a portion of the conductive anode contact (102). In particular, the base layer ring (108) has material removed to form a base layer material gap (118) (e.g., a vacuum gap) adjacent to the conductive anode contact (102). A dielectric layer (110) is also provided to form one boundary of the base layer material gap (118).Type: GrantFiled: September 8, 2000Date of Patent: November 25, 2003Assignee: Northrop Grumman CorporationInventors: Donald J. Sawdai, Augusto L. Gutierrez-Aitken
-
Patent number: 6627967Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: September 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
-
Patent number: 6583485Abstract: The invention relates to a semiconductor device, in particular a Schottky hybrid diode with a guard ring (S). The semiconductor device comprises a semiconductor substrate (1), an epitaxial layer (2) on which an insulating layer (3) with an opening (10) is deposited, with a Schottky metal layer (9) covering the epitaxial layer (2) lying at the bottom of the opening (10), and with an annular semiconductor region (4) which is present in the epitaxial layer (2). A doping region (6) is present in the epitaxial layer (2) along the outer contour of the semiconductor device, and in addition an oxide layer (8) is present on the epitaxial layer (2).Type: GrantFiled: March 28, 2001Date of Patent: June 24, 2003Assignee: Koninklijke Philips Electronics N.V.Inventor: Thomas Epke
-
Patent number: 6576973Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.Type: GrantFiled: December 22, 2000Date of Patent: June 10, 2003Assignee: STMicroelectronics S.A.Inventors: Emmanuel Collard, AndrĂ© Lhorte
-
Patent number: 6551911Abstract: A method for producing Schottky diodes having a protective ring in an edge region of a Schottky contact. The protective ring is produced by a protective ring material that is deposited onto a surface of a semiconductor layer, which surface is provided with a patterned masking layer beforehand, and the protective ring material subsequently being siliconized. In this case, the protective ring material constitutes a metal, in particular a high barrier metal, which has, in particular, platinum.Type: GrantFiled: January 26, 2000Date of Patent: April 22, 2003Assignee: Infineon Technologies AGInventors: Reinhard Losehand, Hubert Werthmann
-
Publication number: 20030052383Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.Type: ApplicationFiled: August 2, 2002Publication date: March 20, 2003Applicant: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Tatsuya Naito, Masahito Otsuki, Mitsuaki Kirisawa
-
Patent number: 6531743Abstract: A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.Type: GrantFiled: January 14, 2002Date of Patent: March 11, 2003Assignee: Oki Electric Industry Co., Ltd.Inventors: Norio Hirashita, Takashi Ichimori
-
Publication number: 20030025175Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
-
Patent number: 6509622Abstract: An integrated circuit including a die having a circuit area and a plurality of guard rings. The circuit area includes active devices, passive devices, and interconnects connected to form an integrated circuit. The plurality of guard rings includes a plurality of stacked guard rings having substantially equal widths and encircling the circuit area. Alternatively, the plurality of guard rings includes metallization level guard rings interleaved with one or more via level guard rings. Each of the one or more via level guard rings includes one or more guard rings encircling the circuit area. Alternatively, the plurality of guard rings includes a plurality of concentric guard rings encircling the circuit area. Each of the plurality of guard rings is fabricated from a metal, such as aluminum, copper, or silver, or an alloy of aluminum, copper, or silver.Type: GrantFiled: August 23, 2000Date of Patent: January 21, 2003Assignee: Intel CorporationInventors: Qing Ma, Jin Lee, Quan Tran, Harry Fujimoto
-
Patent number: 6476456Abstract: A Schottky contact is formed in the area of a MOSgated device semiconductor device chip which is occupied by a source pad. The Schottky contact is formed by the direct contact of the aluminum source electrode to the silicon chip in the source area. A different barrier metal can be used for the Schottky. A guard ring diffusion surrounds the Schottky metal.Type: GrantFiled: May 3, 2000Date of Patent: November 5, 2002Assignee: International Rectifier CorporationInventor: Milton J. Boden, Jr.