With Means To Prevent Edge Breakdown Patents (Class 257/483)
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Patent number: 6441454Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.Type: GrantFiled: February 1, 2001Date of Patent: August 27, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: Erwin A. Hijzen, Raymond J. E. Hueting
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Patent number: 6426542Abstract: An improved diode or rectifier structure and method of fabrication is disclosed involving the incorporation in a Schottky rectifier, or the like, of a dielectric filled isolation trench structure formed in the epitaxial layer adjacent the field oxide layers provided at the edge of the active area of the rectifier, for acting to enhance the field plate for termination of the electric field generated by the device during operation. The trench is formed in a closed configuration about the drift region and by more effectively terminating the electric field at the edge of the drift region the field is better concentrated within the drift region and acts to better interrupt reverse current flow and particularly restricts leakage current at the edges.Type: GrantFiled: February 25, 2000Date of Patent: July 30, 2002Inventor: Allen Tan
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Patent number: 6420768Abstract: A trench Schottky barrier rectifier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections.Type: GrantFiled: December 15, 2000Date of Patent: July 16, 2002Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato
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Patent number: 6410950Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.Type: GrantFiled: April 6, 1998Date of Patent: June 25, 2002Assignee: Infineon Technologies AGInventors: Roland Sittig, Karim-Thomas Taghizadeh-Kaschani
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Publication number: 20020074613Abstract: A trench Schottky barrier rectifier and a method of making the same are disclosed.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato
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Patent number: 6404026Abstract: A semiconductor device 100 has a substrate 11 including a high breakdown voltage transistor region where transistors with high breakdown voltage and high dielectric strength Qn and Qp are formed and a low breakdown voltage transistor region where transistors with low breakdown voltage and low dielectric strength are formed. The transistors with high voltage breakdown and high dielectric strength Qn and Qp and the transistors with low voltage breakdown and low dielectric strength operate at different voltages. In the high breakdown voltage transistor region, the semiconductor device has metal wiring layers 19a and 19b that are fed with a high potential. The metal wiring layers 19a and 19b are provided over the transistors with high voltage breakdown and high dielectric strength Qn and Qp through a first interlayer dielectric film 16 and a second interlayer dielectric film 17. An element isolation dielectric region 14 is provided over the substrate 11.Type: GrantFiled: December 27, 2000Date of Patent: June 11, 2002Assignee: Seiko Epson CorporationInventor: Masahiko Tsuyuki
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Patent number: 6376890Abstract: A high-voltage edge termination structure for planar structures. The planar structures have a semiconductor body of a first conductivity type whose edge area is provided with at least one field plate isolated from the semiconductor body by an insulator layer. The edge area of the semiconductor body is provided with floating regions of a second conductivity type. The floating regions are spaced at such a distance from one another that zones between the floating regions are depleted even at an applied voltage which is low in comparison with a breakdown voltage of the semiconductor body for the floating regions.Type: GrantFiled: December 8, 1999Date of Patent: April 23, 2002Assignee: Siemens AktiengesellschaftInventor: Jenoe Tihanyi
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Publication number: 20020005558Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4).Type: ApplicationFiled: April 8, 1999Publication date: January 17, 2002Inventors: ADAM R. BROWN, GODEFRIDUS A.M. HURKX, MICHAEL S. PETER, HENDRIK G.A. HUIZING, WIEBE B. DE BOER
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Patent number: 6303969Abstract: An improved diode or rectifier structure and method of fabrication is disclosed involving the incorporation in a Schottky rectifier, or the like, of a dielectric filled isolation trench structure formed in the epitaxial layer adjacent the field oxide layers provided at the edge of the active area of the rectifier, for acting to enhance the field plate for termination of the electric field generated by the device during operation. The trench is formed in a closed configuration about the drift region and by more effectively terminating the electric field at the edge of the drift region the field is better concentrated within the drift region and acts to better interrupt reverse current flow and particularly restricts leakage current at the edges.Type: GrantFiled: May 1, 1998Date of Patent: October 16, 2001Inventor: Allen Tan
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Publication number: 20010007369Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.Type: ApplicationFiled: February 23, 2001Publication date: July 12, 2001Inventors: Jun Zeng, Gary Mark Dolry, Praveen Shenoy MurAleedharan
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Patent number: 6177712Abstract: A Schottky barrier diode is provided which has a substrate including a first-conductivity-type low concentration layer and a first-conductivity-type high concentration layer, and a guard ring region, comprising a second-conductivity-type diffusion layer having an impurity surface concentration of not greater than 5×1017/cm3, formed in the first-conductivity-type low concentration layer. The first-conductivity-type low concentration layer has a thickness large enough to prevent a depletion layer that appears in the low concentration layer upon application of the maximum reverse voltage from reaching the first-conductivity-type high concentration layer.Type: GrantFiled: December 10, 1997Date of Patent: January 23, 2001Assignee: Fuji Electric Co., Ltd.Inventor: Yasushi Miyasaka
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Patent number: 6133617Abstract: Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.Type: GrantFiled: September 10, 1999Date of Patent: October 17, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Keizo Hirayama, Hideyuki Funaki, Fumito Suzuki, Akio Nakagawa
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Patent number: 6066884Abstract: The specification describes Schottky barrier devices with distributed guard rings. In one embodiment the guard ring only partially overlaps the barrier. In another embodiment the guard ring is spaced from the barrier throughout, but separated by an MOS gate so that the guard ring and barrier are connected at low bias by an inversion layer.Type: GrantFiled: March 19, 1999Date of Patent: May 23, 2000Assignee: Lucent Technologies Inc.Inventor: Thomas J. Krutsick
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Patent number: 6063996Abstract: A solar cell module according to the present invention includes at least a base material, a first insulating material formed on the base material, a photovoltaic element set including a plurality of photovoltaic elements formed on the first insulating material, and a second insulating material formed on the photovoltaic element set. The base material has an L or W shape. In one embodiment, the base material has an L section shape, and a bent portion is formed in a portion where no photovoltaic element is arrange. In another embodiment, the photovoltaic element set includes a wiring material for electrically connecting the photovoltaic elements, and a bent portion is formed in a portion where the wiring material is arranged. Power generation and heat collection efficiency are increased, and optical deterioration of a non-single-crystal semiconductor are decreased in the present solar cell modules.Type: GrantFiled: July 9, 1997Date of Patent: May 16, 2000Assignee: Canon Kabushiki KaishaInventors: Takeshi Takada, Kimitoshi Fukae, Toshihiko Mimura, Masahiro Mori, Satoru Shiomi
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Patent number: 6008512Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.Type: GrantFiled: April 28, 1993Date of Patent: December 28, 1999Assignee: Intersil CorporationInventor: James D. Beasom
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Patent number: 5982015Abstract: Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.Type: GrantFiled: February 17, 1999Date of Patent: November 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Keizo Hirayama, Hideyuki Funaki, Fumito Suzuki, Akio Nakagawa
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Patent number: 5917228Abstract: The present invention relates to a schottky-barrier diode capable of decreasing a leakage current due to damage generated on inner walls of trenches, and securing a large operation region for itself. In the device, an N.sup.- -type epitaxial layer is formed on a N.sup.+ -type silicon substrate. In a predetermined region in the epitaxial layer, a P.sup.+ -type base diffusion layer having high impurity concentration is formed. Trenches are formed through from the surface of the base diffusion layer to the epitaxial layer. In each of the trenches, an N.sup.- -type selective epitaxial growth region is formed. A schottky metal is formed on a surface comprising the surfaces of the base diffusion layer, which includes the selective epitaxial growth regions, and the epitaxial layer. Surface regions as the surfaces of the selective epitaxial growth regions filling the trenches function as diode operation regions.Type: GrantFiled: February 13, 1997Date of Patent: June 29, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Noboru Matsuda, Yoshiro Baba
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Patent number: 5914500Abstract: A semiconductor diode structure with a Schottky junction, wherein a metal contact and a silicon carbide semiconductor layer of a first conducting type form the junction and wherein the edge of the junction exhibits a junction termination divided into a transition belt (TB) having gradually increasing total charge or effective sheet charge density closest to the metal contact and a Junction Termination Extension (JTE) outside the transition belt, the JTE having a charge profile with a stepwise or uniformly deceasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the center part of the JTE towards the outermost edge of the termination.Type: GrantFiled: March 20, 1997Date of Patent: June 22, 1999Assignee: ABB Research Ltd.Inventors: Mietek Bakowski, Ulf Gustafsson
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Patent number: 5907179Abstract: A Schottky diode assembly includes a Schottky contact formed on a semiconductor substrate and having a semiconductor region of a first conduction type, a metal layer disposed adjacently on the semiconductor region, a protective structure constructed on a peripheral region of the Schottky contact and a doped region in the semiconductor substrate having a second conduction type of opposite polarity from the first conduction type. The doped region extends from a main surface of the semiconductor substrate to a predetermined depth into the semiconductor substrate. The doped region of the protective structure has at least two different first and second doped portions located one below the other relative to the main surface of the semiconductor substrate. The first doped portion is at a greater depth and has a comparatively lesser doping, and the second doped portion has a comparatively higher doping and a slight depth adjacent the main surface of the semiconductor substrate.Type: GrantFiled: April 25, 1997Date of Patent: May 25, 1999Assignee: Siemens AktiengesellschaftInventors: Reinhard Losehand, Hubert Werthmann
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Patent number: 5712502Abstract: An n- or p-doped semiconductor region accommodates the depletion zone of an active area of the semiconductor component with a vertical extension dependent upon an applied blocking voltage. The junction termination for the active area is constituted with a semiconductor doped oppositely to the semiconductor region, and is arranged immediately adjacently around the active area on or in a surface of the semiconductor region. The lateral extension of the junction termination is greater than the maximum vertical extension of the depletion zone, and the semiconductor region as well as the junction termination are constituted with a semiconductor with a band gap of at least 2 eV.Type: GrantFiled: March 27, 1996Date of Patent: January 27, 1998Assignee: Siemens AktiengesellschaftInventors: Heinz Mitlehner, Dietrich Stephani, Ulrich Weinert
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Patent number: 5672904Abstract: A Schottky barrier diode having improved breakdown characteristics has an n.sup.+ semiconductor layer and an n.sup.- semiconductor layer provided on the n.sup.+ semiconductor layer. The n.sup.- semiconductor layer is configured to form a mesa. An insulating layer is formed so as to expose the upper surface of the mesa. An anode electrode is provided on the exposed surface and a side surface of the mesa, while a cathode is electrically connected to the n.sup.+ layer. A plasma treated layer is provided in the n.sup.- semiconductor layer so as to extend inwardly from at least a portion of the side surface of the mesa.Type: GrantFiled: August 23, 1996Date of Patent: September 30, 1997Assignee: Murata Manufacturing Co., Ltd.Inventors: Tomoyasu Miyata, Koichi Sakamoto
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Patent number: 5612568Abstract: A low-noise Zener diode that enables to improve the surge resistance performance without degeneration of its low-noise characteristic is provided. The diode contains a semiconductor substrate of a first conductivity type and a first impurity doped region of a second conductivity type formed in a surface area of the substrate. The first impurity doped region has spaces into which no impurity of the second conductivity type is doped. The diode further contains a second impurity doped region of the second conductivity type formed in the first impurity doped region. The second impurity doped region has a depth less than that of the first impurity doped region. The second impurity doped region is contacted with the substrate in the spaces, producing main p-n junctions of the diode at respective interfaces of the second impurity doped regions and the substrate. The second impurity doped region is contacted with the first impurity doped region other than in the spaces.Type: GrantFiled: November 21, 1995Date of Patent: March 18, 1997Assignee: NEC CorporationInventor: Takao Arai
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Patent number: 5608244Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.Type: GrantFiled: August 24, 1994Date of Patent: March 4, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hideki Takahashi
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Patent number: 5539237Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.Type: GrantFiled: May 2, 1995Date of Patent: July 23, 1996Assignee: Texas Instruments IncorporatedInventors: James R. Todd, Joe R. Trogolo, Andrew Marshall, Eric G. Soenen
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Patent number: 5478764Abstract: A method of producing a semiconductor device including a Schottky barrier diode (SBD) comprising the steps of: selectively forming an insulating layer having a first contact hole and a second contact hole, on a (100) silicon semiconductor substrate; selectively forming a polysilicon layer extending from the first contact hole to the second contact hole, the polysilicon layer having a viahole within the first contact hole for selectively exposing the silicon semiconductor substrate; and selectively depositing a refractory metal (tungsten or molybdenum) layer on the polysilicon layer and an exposed portion of the substrate within the viahole by a selective CVD process, so that the SBD is formed between the exposed portion and the metal layer. The refractory metal layer is formed on the silicon of the exposed portion of the substrate and the polysilicon layer and is not formed on the insulating layer, and thus it is unnecessary to perform a photolithography process for patterning the refractory metal layer.Type: GrantFiled: May 10, 1994Date of Patent: December 26, 1995Assignee: Fujitsu LimitedInventor: Kenichi Inoue
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Patent number: 5389815Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.Type: GrantFiled: April 20, 1993Date of Patent: February 14, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hideki Takahashi
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Patent number: 5336905Abstract: Semiconductor device and method of manufacturing same, display device and support plate for same provided with such a semiconductor device. A semiconductor device having an insulating substrate on which a Schottky diode is formed between a metal layer and a semiconductor layer of polycrystalline or amorphous silicon extending over the metal layer is used inter alia in matrix display devices, such as LCDs. The Schottky diode forms part of a switching element of such a device and must have a low reverse current up to a reverse voltage of, for example, approximately 10 V. The known semiconductor device having Schottky diodes, in which the semiconductor material extends over a lateral surface of the Schottky metal, is found not to comply with this requirement. To overcome this deficiency a low leakage current is realized over a wide reverse voltage range due to the presence of a dielectric on the lateral surface of the Schottky metal. The dielectric suppresses the leakage current issuing from the lateral surface.Type: GrantFiled: July 1, 1992Date of Patent: August 9, 1994Assignee: U.S. Philips CorporationInventors: Antonie J. Bosman, Teunis J. Vink, Richard C. van Dijk, Frederikus R. J. Huisman
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Patent number: 5278443Abstract: A semiconductor device includes a diode having a Schottky barrier and a MOS transistor integrally formed in one and the same semiconductor substrate in which the diode and MOS transistor have their main electrode in common use. The diode has a first diode portion having a pn junction in a current-passing direction and a second diode portion having a combination of the Schottky barrier and another pn junction in the current passing direction.Type: GrantFiled: November 5, 1992Date of Patent: January 11, 1994Assignees: Hitachi, Ltd., Hitachi Haramachi Semiconductor, Ltd.Inventors: Mutsuhiro Mori, Yasumiti Yasuda, Naoki Sakurai, Hidetoshi Arakawa, Hiroshi Owada
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Patent number: 5262669Abstract: A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which includes a semiconductor substrate having an N.sup.+ -type semiconductor layer and an N-type semiconductor layer, a P.sup.+ -type semiconductor layer formed in the N-type semiconductor layer to provide a PN junction therebetween, the P.sup.+ -type semiconductor layer defining exposed regions of the N-type semiconductor layer, and a metal layer provided on an entire surface of the semiconductor substrate having the P.sup.+ -type semiconductor layer to provide contact surfaces of Schottky barrier between the metal layer and each of the exposed regions of the N-type semiconductor layer. In the structure, a configuration of the PN junction is provided to satisfy conditions given by 0.degree.<.theta..ltoreq.135.degree. and 3Wbi.ltoreq.W.ltoreq.2W.sub.B where .theta.Type: GrantFiled: April 17, 1992Date of Patent: November 16, 1993Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Masaru Wakatabe, Mitsugu Tanaka, Shinji Kunori