Specified Materials Patents (Class 257/485)
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Patent number: 6501145Abstract: The invention relates to a semiconductor component with adjacent Schottky (5) and pn (9) junctions positioned in a drift area (2, 10) of a semiconductor material. The invention also relates to a method for producing said semiconductor component.Type: GrantFiled: March 3, 2000Date of Patent: December 31, 2002Assignee: DaimlerChrysler AGInventors: Nando Kaminski, Raban Held
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Patent number: 6498381Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods are also provided.Type: GrantFiled: February 22, 2001Date of Patent: December 24, 2002Assignee: Tru-Si Technologies, Inc.Inventors: Patrick B. Halahan, Oleg Siniaguine
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Patent number: 6486524Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.Type: GrantFiled: February 22, 2000Date of Patent: November 26, 2002Assignee: International Rectifier CorporationInventor: Iftikhar Ahmed
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Patent number: 6452244Abstract: On a semiconductor layer 1 consisting of a substrate of a semiconductor single crystal or the like, a metallic layer 2 of a thickness of 20 nm or less is formed. The metallic layer 2 comprises a first area A directly contacting with the semiconductor layer 1, and a second area B that is interposed by an intermediate layer 3 consisting of an insulator, a metal different from the metallic layer 2 or a semiconductor different from the semiconductor layer 1 between the semiconductor 1 and the metallic layer 2, and of a thickness of 10 nm or less. The first area and the second area are different in their Schottky currents, further in their Schottky barrier heights. Any one of the respective areas A and B has an area of nanometer level, and the respective interfaces in each of the areas A and B have an essentially uniform potential barrier, respectively. Such a film-like composite structure contributes to a minute semiconductor device of nanometer level and realization of a new functional device.Type: GrantFiled: August 10, 1999Date of Patent: September 17, 2002Assignees: Japan Science and Technology Corporation, Kabushiki Kaisha ToshibaInventors: Tadao Miura, Touru Sumiya, Shun-ichiro Tanaka
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Publication number: 20020109201Abstract: A rectifying device and method of fabrication thereof is disclosed. The method comprises the steps of plating a metal (e.g., aluminum) layer on top and bottom surfaces of silicon wafer in a vacuum, cutting silicon wafer into a plurality of identical silicon dies, coupling a molybdenum layer on either top or bottom surface of silicon die by brazing metal film therebetween, performing an etching on silicon die after silicon die and molybdenum layers are formed together, filling a uniform glass paste onto the peripheral surface of silicon die between the molybdenum layers, and sintering the glass paste to form a glass layer on the peripheral surface of silicon die. This ensures that the rectifying device can operate normally when mounted on a high power high input current circuit. Also, a conductive metal (e.g., nickel or gold) layer is coated on the portion of either molybdenum layer which is not in contact with silicon die.Type: ApplicationFiled: February 9, 2001Publication date: August 15, 2002Inventor: Chein-Chang Chen
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Patent number: 6396076Abstract: A test structure determines the trench depth from etching in a resistive substrate. The test structure has a first contact and a second contact to the substrate. Between the first and second contact is disposed an etch window. A measurement of resistance between the first contact and the second contact is indicative of the depth of etching in the etch window.Type: GrantFiled: August 21, 2001Date of Patent: May 28, 2002Assignee: Hewlett-Packard CompanyInventor: Dennis W. Tom
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Patent number: 6362495Abstract: A dual-metal-trench silicon carbide Schottky pinch rectifier having a plurality of trenches formed in an n-type SiC substrate, with a Schottky contact having a relatively low barrier height on a mesa defined between adjacent ones of the trenches, and a Schottky contact having a relatively high barrier height at the bottom of each trench. The same metal used for the Schottky contact in each trench is deposited over the Schottky contact on the mesa. A simplified fabrication process is disclosed in which the high barrier height metal is deposited over the low barrier height metal and then used as an etch mask for reactive ion etching of the trenches to produce a self-aligned low barrier contact.Type: GrantFiled: March 5, 1999Date of Patent: March 26, 2002Assignee: Purdue Research FoundationInventors: Kipp J. Schoen, Jason P. Henning, Jerry M. Woodall, James A. Cooper, Jr., Michael R. Melloch
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Patent number: 6337151Abstract: A barrier film for a semiconductor device structure. The barrier film includes a compound including nitrogen and at least one of titanium or tantalum, nitrogen in a concentration that varies within the barrier film, and oxygen in a concentration that varies within the barrier film.Type: GrantFiled: August 18, 1999Date of Patent: January 8, 2002Assignee: International Business Machines CorporationInventors: Cyprian E. Uzoh, Daniel C. Edelstein, Andrew H. Simon
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Publication number: 20010054715Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.Type: ApplicationFiled: December 22, 2000Publication date: December 27, 2001Inventors: Emmanuel Collard, Andre Lhorte
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Patent number: 6320205Abstract: An edge termination for a semiconductor component containing a semiconductor body formed of silicon carbide. The edge termination has at least one diode chain that is insulated from the semiconductor body and provided with a plurality of semiconductor layers having alternating conductivity types.Type: GrantFiled: September 15, 2000Date of Patent: November 20, 2001Assignee: Infineon Technologies AGInventors: Frank Pfirsch, Roland Rupp
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Publication number: 20010040264Abstract: A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal as the seed layer, so that the metal layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.Type: ApplicationFiled: July 31, 2001Publication date: November 15, 2001Inventor: Nobukazu Ito
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Patent number: 6303998Abstract: A semiconductor device 14 capable of reducing the warpage in a substrate is provided. A semiconductor chip 12 is mounted on a substrate 10 made of an electro-insulating material by flip-chip bonding, so that connector terminals formed on the substrate 10 are connected to electrodes of the semiconductor chip 12 and a gap between the substrate 10 and the semiconductor chip 12 is filled with an underfiller 18. According to the present invention, in the semiconductor device 14, none of sides of the substrate 10 is parallel to any one of sides of the semiconductor chip 12, and none of diagonal lines S of the substrate 10 coincides with any one of diagonal lines T of the semiconductor chip 12.Type: GrantFiled: August 18, 1999Date of Patent: October 16, 2001Assignee: Shinko Electric Industries Co., Ltd.Inventor: Kei Murayama
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Publication number: 20010019165Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.Type: ApplicationFiled: May 8, 2001Publication date: September 6, 2001Applicant: California Institute of TechnologyInventors: Zvonimir Z. Bandic, Eric C. Piquette, Thomas C. McGill
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Patent number: 6160278Abstract: In this invention, a new, simple and small-size hydrogen-sensitive palladium (Pd) membrane/semiconductor Schottky diode sensor has been developed and fabricated. First, a high quality undoped GaAs buffer layer and an n-type GaAs epitaxial layer with the carrier concentration of 2.times.10.sup.17 cm.sup.31 3 is grown by molecular beam epitaxy (MBE) on a semi-insulated GaAs substrate. Then a thin Pd membrane is evaporated on the surface of the n-type GaAs epitaxial layer by the vacuum evaporation technique. It is well-known that palladium metal has excellent selectivity and sensitivity on hydrogen gas. When hydrogen gas diffuses to the Pd membrane surface, the hydrogen molecules will dissociate into hydrogen atoms. Some of the hydrogen atoms diffuse through the thin metal layer and form the palladium hydride near the metal-semiconductor interface. The hydride may effectively lower the work function of Pd metal.Type: GrantFiled: May 28, 1999Date of Patent: December 12, 2000Assignee: National Science CouncilInventors: Wen-Chau Liu, Huey-Ing Chen, Shiou-Ying Cheng
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Patent number: 6093952Abstract: A Schottky high power rectifier having a nitride insulator formed on the surface of a GaN substrate. The nitride insulator increases the electric field breakdown suppression at or near the surface of the rectifier below the insulator. In a preferred embodiment, the nitride insulator is an epitaxially grown aluminum nitride insulator.Type: GrantFiled: March 31, 1999Date of Patent: July 25, 2000Assignee: California Institute of TechnologyInventors: Zvonimir Z. Bandic, Eric C. Piquette, Thomas C. McGill
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Patent number: 6087704Abstract: Group III-V composites, which is used to manufacture Schottky contacts having the characteristics of higher energy gap, higher carriers mobility, etc., are applied for manufacturing high-speed devices. Therefore, in there years, Group III-V composite Schottky contacts are continuously being developed. In the invention, the surface treatment of composite semiconductor is used for reduce a surface state and oxidation, thereby increased the Schottky barriers of the Group III-V composite (such as, GaAs, InP, InAs and InSb) Schottky contacts. During experiments, a phosphorus sulphide/ammonia sulphide solution and hydrogen fluoride solution are used for the surface treatment to increase the amount of sulphur contained on the surfaces of substrates, reduce the surface state and remove various oxides. Furthermore, ultra-thin and really stable sulphur fluoride/phosphorus fluoride layers having high energy gaps are formed on various substrates.Type: GrantFiled: September 30, 1997Date of Patent: July 11, 2000Assignee: National Science CouncilInventors: Liann-Be Chang, Hung-Tsung Wang
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Patent number: 6087702Abstract: A method for forming a Schottky diode structure is disclosed. The method includes the steps of: a) Providing a substrate; b) forming a rare-earth containing layer over the substrate; and c) forming a metal layer over the rare-earth containing layer. The Schottky diode structure with a rare-earth containing layer has the properties of high-temperature stability, high Schottky barrier height (SBH), and low reverse leakage current.Type: GrantFiled: April 2, 1998Date of Patent: July 11, 2000Assignee: National Science CouncilInventors: Liann-Be Chang, Hang-Thung Wang
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Patent number: 6078071Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.Type: GrantFiled: June 9, 1999Date of Patent: June 20, 2000Assignee: Fujitsu Quantum Devices LimitedInventor: Hajime Matsuda
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Patent number: 6060757Abstract: An RF diode, and method for its manufacture, in which a well, doped n-conductive or p-conductive, is formed in a high-ohmic silicon substrate. A silicon epitaxial layer is provided over a first subregion of a surface of the well wherein the layer has the same conductivity type as the doped well. The silicon epitaxial layer is provided with a first Schottky contact layer onto which a first contact metallization is applied. A second subregion located next to the first subregion of the surface of the well is provided with a second Schottky contact layer onto which a second contact metallization is applied.Type: GrantFiled: August 27, 1998Date of Patent: May 9, 2000Assignee: Siemens AktiengesellschaftInventors: Reinhard Losehand, Hubert Werthmann
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Patent number: 5961741Abstract: The present invention provides a metal semiconductor optical device which is capable of thinly uniformly growing a metal film on a semiconductor substrate using a layer functioning as an interface active agent and decreasing the density of interface energy state occurring between the metal thin film and the semiconductor, to thereby enhance the optical absorption efficiency of light beam. The interface single atomic layer is formed by one of the group V elements, e.g., one of antimony(Sb) or arsenic(As). Additionally, the metal thin film has a thickness of approximately 30 .ANG..Type: GrantFiled: April 17, 1997Date of Patent: October 5, 1999Assignee: Electronics and Telecommunications Research InstituteInventors: Kang-Ho Park, Jeong-Sook Ha
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Patent number: 5914500Abstract: A semiconductor diode structure with a Schottky junction, wherein a metal contact and a silicon carbide semiconductor layer of a first conducting type form the junction and wherein the edge of the junction exhibits a junction termination divided into a transition belt (TB) having gradually increasing total charge or effective sheet charge density closest to the metal contact and a Junction Termination Extension (JTE) outside the transition belt, the JTE having a charge profile with a stepwise or uniformly deceasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the center part of the JTE towards the outermost edge of the termination.Type: GrantFiled: March 20, 1997Date of Patent: June 22, 1999Assignee: ABB Research Ltd.Inventors: Mietek Bakowski, Ulf Gustafsson
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Patent number: 5859464Abstract: An optoelectronic component has an Al.sub.2 O.sub.3 or Si substrate having a surface on which a buried CoSi.sub.2 layer is provided, a Si layer overlying the buried CoSi.sub.2 layer. A metal layer on a portion of this latter Si layer forms a diode between the metal layer, the underlying portion of the Si layer and the buried CoSi.sub.2 layer and a waveguide for a transparent portion of the metal layer delivers photon energy to the underlying portion of the Si layer.Type: GrantFiled: September 26, 1996Date of Patent: January 12, 1999Assignee: Forschungszentrum Julich GmbHInventors: Olaf Hollricher, Frank Ruders, Christoph Buchal, Hartmut Roskos, Jens Peter Hermanns, Elard Stein Von Kamienski, Klaus Rademacher
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Patent number: 5859465Abstract: A vertical conduction Schottky device having a reverse voltage rating in excess of 400 volts uses an aluminum barrier metal in contact with an N.sup.- epitaxial silicon surface. A diffused P.sup.+ guard ring surrounds the barrier metal contact and is spaced therefrom by a small gap which is fully depleted at a low reverse voltage to connect the ring to the barrier contact under reverse voltage conditions. Lifetime killing is used for the body of the diode.Type: GrantFiled: October 15, 1996Date of Patent: January 12, 1999Assignee: International Rectifier CorporationInventors: Kyle A. Spring, Perry L. Merrill
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Patent number: 5814874Abstract: A semiconductor device having a semiconductor substrate and an epitaxial layer deposited thereon which supports a patterned insulating layer on which a metal layer is provided. To achieve a lower capacitance of the semiconductor device with unchanged forward voltage, the epitaxial layer consists of first and second epitaxial layers, the first epitaxial layer which adjoins the semiconductor substrate having a higher dopant concentration than and being of the same conductivity type as the second epitaxial layer.Type: GrantFiled: July 16, 1996Date of Patent: September 29, 1998Assignee: General Semiconductor IrelandInventor: Guenter Igel
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Patent number: 5753960Abstract: A monolithically integrated circuit for carrying out different mixer and switch functions includes: at least one p-i-n diode and at least one Schottky diode monolithically integrated in the circuit. The p-i-n diode and Schottky diode are made from a common semiconductor layer sequence. The semiconductor layer sequence respectively includes: highly doped p-contact and n-contact layers, and a lightly doped insulating layer grown between the contact layers and which includes an etch arresting layer at a defined distance d from one of the contact layers.Type: GrantFiled: August 19, 1996Date of Patent: May 19, 1998Assignees: Daimler Benz AG, Temic Telefunken microelectronic GmbHInventor: Juergen Dickmann
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Patent number: 5744817Abstract: A hot carrier transistor can be formed with semiconductor thin-film technology, for example hydrogenated amorphous silicon (a-Si:H) technology as used for large-area electronics devices. The emitter and collector regions (2 and 3) comprise hydrogenated amorphous semiconductor material (a-Si:H) adjoining an intermediate semiconductor-rich amorphous metal-semiconductor alloy layer (a-Si.sub.1-x M.sub.x :H) which provides the base region 1. The amorphous nature of the alloy layer (1) and its low percentage of metal M, e.g 5%, presents a range of quantum mechanical environments for the hot carriers (21) through the base region (1) with spatial variations of wavelength and effective mass (m*.sub.1, m*.sub.2). The current transport through this base region (1) will therefore be spatially self-selective in that the carriers (21) will tend to pass through those areas where there is a resonance between the wave function, the barrier heights (h1,h2) and the base width (x1,x2).Type: GrantFiled: December 11, 1996Date of Patent: April 28, 1998Assignee: U.S. Philips CorporationInventor: John M. Shannon
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Platinum silicide Schottky diodes in a titanium-silicided CMOS-based high performance BICMOS process
Patent number: 5672898Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate at which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.Type: GrantFiled: July 25, 1996Date of Patent: September 30, 1997Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah -
Patent number: 5665993Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.Type: GrantFiled: March 26, 1996Date of Patent: September 9, 1997Assignee: Texas Instruments IncorporatedInventors: Stephen A. Keller, Rajiv R. Shah
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Patent number: 5644156Abstract: A semiconductor device includes a porous silicon layer with an impurity concentration of 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3, in which a plurality of pores are formed, and a thermal oxide film 0.01 to 10 .mu.m thick formed on the expanded surfaces of the porous silicon layer, wherein said expanded surfaces include internal surface of said pores.Type: GrantFiled: April 12, 1995Date of Patent: July 1, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Taketoshi Suzuki, Tadashi Sakai, Li Zhang, Taijun Murakami
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Patent number: 5536967Abstract: A Schottky gate electrode of a refractory metal silicide is formed on a compound semiconductor, by which the barrier height is maintained satisfactorily even after heat treatment above 800.degree. C. Accordingly, it is possible to form an impurity diffused region using the Schottky gate electrode as a mask and then to effect the recrystallization of the semiconductor or the activation of the impurity by heat treatment, so that source and drain regions can be positioned by self-alignment relative to the gate electrode.Type: GrantFiled: October 7, 1994Date of Patent: July 16, 1996Assignee: Fujitsu LimitedInventor: Naoki Yokoyama
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Patent number: 5517054Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.Type: GrantFiled: April 21, 1995Date of Patent: May 14, 1996Assignee: National Science CouncilInventors: Wen C. Huang, Tan F. Lei, Chung L. Lee
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Patent number: 5471072Abstract: Gold, which is the commonly used metallization on .beta.-silicon carbide, is known to degrade at temperatures above 450.degree. C. It also exhibits poor adhesion to silicon carbide. Schottky contacts with platinum metallization have rectifying characteristics similar to contacts with gold metallization. The platinum Schottky contacts remain stable up to 800.degree. C. Adhesion of the platinum deposited at slightly elevated temperatures is also superior to that for gold. Platinum provides a metallization that is physically more rugged and thermally more stable than conventional gold metallization.Type: GrantFiled: December 13, 1993Date of Patent: November 28, 1995Assignee: The United States of America as represented by the Secretary of the NavyInventor: Nicolas A. Papanicolaou
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Patent number: 5384470Abstract: A rectifying contact including a refractory metal carbide layer on a polycrystalline diamond layer provides high temperature operation and may be included in semiconductor devices, such as diodes and field effect transistors. The refractory metal carbide layer forms a substantially chemically non-reactive interface with the polycrystalline diamond. A single layer of substantially stoichiometric proportions of the refractory metal layer is provided in one embodiment of the rectifying contact. Another embodiment includes a second metal-rich refractory metal carbide layer on the stoichiometric layer. Yet another embodiment includes a carbon-rich refractory metal layer between the stoichiometric layer and the polycrystalline diamond layer. A metal field effect transistor including the rectifying contact may also be fabricated.Type: GrantFiled: November 2, 1992Date of Patent: January 24, 1995Assignee: Kobe Steel, USA, Inc.Inventors: Takeshi Tachibana, Dale G. Thompson, Jr., Jeffrey T. Glass
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Patent number: 5371400Abstract: Desirably, a Schottky barrier semiconductor diode has low forward direction rising voltage and high inverse direction yield voltage. A semiconductor device is provided with a first metal producing a low Schottky barrier and a second metal producing a high Schottky barrier. The forward direction rising voltage is reduced on account of the first metal. The inverse direction yield voltage, which is decreased due to the lowered forward rising voltage, is compensated for upon linking of depletion regions generated by forming the PN junction under the first metal layer and not under the second metal layer. As a result, a high inverse yield voltage is realized.Type: GrantFiled: November 9, 1993Date of Patent: December 6, 1994Assignee: Fuji Electric Co., Ltd.Inventor: Keiji Sakurai
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Patent number: 5371378Abstract: A diamond transistor includes a base layer formed of a conductive material which is lattice matched to diamond, and which is embedded between two epitaxial diamond layers to form a monolithic heterostructure. An emitter contact is electrically connected to one diamond layer and a collector contact is electrically connected to the other diamond layer. The base layer may be a solid base layer, in which case a metal base transistor is formed. Alternatively, the base layer may be a patterned base layer having a grid of laterally spaced apart conductor lines, in which case a permeable base transistor is formed. Alternatively, the epitaxial diamond layers may be doped diamond layers of the same conductivity type. The epitaxial diamond layers may be undoped diamond layers formed between highly doped diamond layers, with the collector and emitter contacts being formed on the highly doped diamond layers to provide low resistance contacts.Type: GrantFiled: June 8, 1992Date of Patent: December 6, 1994Assignee: Kobe Steel USA, Inc.Inventor: Kalyankumar Das
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Patent number: 5352908Abstract: A diamond Schottky diode including an electrically conductive substrate, a multi-layer structure of a semiconducting diamond layer and an insulating diamond layer, and a metal electrode. This diode has a greater potential barrier under a reversed bias and hence exhibits better rectifying characteristics with a smaller reverse current.Type: GrantFiled: November 3, 1993Date of Patent: October 4, 1994Assignee: Kabushiki Kaisha Kobe Seiko ShoInventors: Koji Kobashi, Koichi Miyata, Kozo Nishimura
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Semiconductor devices using epitaxial silicides on (111) surfaces etched in (100) silicon substrates
Patent number: 5323053Abstract: In accordance with the present invention, a silicon device fabricated on a (100) silicon substrate is provided with a (111) slant surface and an electrical contact comprising epitaxial low Schottky barrier silicide is formed on the (111) surface. For example, low resistance rare earth silicide contacts on V-groove surfaces are provided for the source and drain contacts of a field effect transistor. The resulting high quality contact permits downward scaling of the source and drain junction depths. As another example, rare earth silicide Schottky contacts are epitaxially grown on V-groove surfaces to provide low voltage rectifiers having both low power dissipation under forward bias and low reverse-bias leakage current.Type: GrantFiled: July 9, 1993Date of Patent: June 21, 1994Assignee: AT&T Bell LaboratoriesInventors: Sergey Luryi, Gabriel L. Miller -
Patent number: 5306928Abstract: A semiconductor device utilizing a non-doped diamond layer between a substrate and an active diamond layer. Such a structure decreases the resistivity and increases the carrier density. Further, when contacts are formed on the active layer, this layer structure reduces reverse leak current.Type: GrantFiled: May 18, 1992Date of Patent: April 26, 1994Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tunenobu Kimoto, Tadashi Tomikawa, Nobuhiko Fujita
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Patent number: 5298766Abstract: A diamond heterojunction diode having an improved rectifying characteristics with a small reverse current and a large forward current. Three layers are formed on a low-resistance p-type silicon substrate by the microwave plasma CVD in the order of a B-doped p type semiconducting diamond layer, an insulating undoped diamond layer (thinner than 1 .mu.m), and an n-type semiconducting silicon layer. Ohmic electrodes are formed on the front side of a n-type semiconducting silicon layer and the back side of a substrate. Under a forward bias, the electric field is applied to the intermediate insulating layer to accelerate the transport of holes and electrons. Under a reversed bias, the energy band has a notch as well as a potential barrier due to the intermediate layer thus preventing holes from transporting from the n-type semiconducting diamond layer to the p-type semiconducting diamond layer, resulting in the improved rectifying characteristics.Type: GrantFiled: March 20, 1992Date of Patent: March 29, 1994Assignee: Kabushiki Kaisha Kobe Seiko ShoInventors: Koji Kobashi, Kozo Nishimura, Shigeaki Miyauchi, Kazuo Kumagai, Rie Katoh
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Patent number: 5285084Abstract: Schottky diodes and gas sensors include a diamond layer having a Schottky contact thereon and an ohmic contact thereon, wherein the diamond layer includes a highly doped region adjacent the ohmic contact to provide a low resistance ohmic contact. Dramatically reduced frequency dependence of the capacitance/voltage characteristic of Schottky diodes and gas sensors formed thereby, compared to Schottky diodes and gas sensors which do not include the highly doped region adjacent the ohmic contact, is provided. The highly doped region is preferably boron doped at a concentration of at least 10.sup.20 atoms per cubic centimeter to form an ohmic contact with a contact resistance of less than 10.sup.-3 .OMEGA.-cm.sup.2. The ohmic contact is preferably a back contact on the face of the diamond layer opposite the Schottky contact.Type: GrantFiled: September 2, 1992Date of Patent: February 8, 1994Assignee: Kobe Steel USAInventors: Jesko von Windheim, Vasudev Venkatesan
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Patent number: 5278431Abstract: A rectifying contact includes a first semiconducting diamond layer, a second undoped diamond layer on the first layer, and a third relatively highly doped diamond layer on the second layer. The first semiconducting diamond layer may be formed on a supporting substrate. A bonding contact is preferably formed on the third relatively highly doped diamond layer for facilitating electrical connection thereto. The bonding contact is preferably a titanium carbide/gold bilayer. In one embodiment, an ohmic contact may be formed on the first semiconducting diamond layer by an electrically conductive substrate and an associated metal layer on an opposite side of the substrate from the semiconducting diamond layer. In another embodiment, an ohmic contact may be formed on the first semiconducting diamond layer by a fourth relatively highly doped diamond layer and an associated bonding contact on the fourth diamond layer.Type: GrantFiled: February 23, 1993Date of Patent: January 11, 1994Assignee: Kobe Development CorporationInventor: Kalyankumar Das
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Patent number: 5278430Abstract: A complementary semiconductor device incorporating semiconductor composed of diamond. Substantially, diamond is insulative. When both III group elementary atoms and V group elementary atoms are doped into diamond, the doped regions respectively turn into p-type and n-type semiconductors. The embodiment discretely dopes both III group elementary atoms and V group elementary atoms into a layer of diamond thin film to eventually form a complementary semiconductor device. The embodiment forms wiring system inside of the diamond thin film by selectively doping either III group elementary atoms or V group elementary atoms therein without forming wiring system only on the inter-layer insulation film.Type: GrantFiled: February 18, 1992Date of Patent: January 11, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Masakazu Kakumu
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Patent number: 5256897Abstract: An oxide superconducting device has a junction structure composed of at least one oxide superconductor and at least one insulator in which carriers have been generated. As the insulator in which carriers have been generated, there can be used, for example, SrTiO.sub.3 doped with Nb. With such a device, rectifying characteristics can be attained in the junction.Type: GrantFiled: July 10, 1991Date of Patent: October 26, 1993Assignee: Hitachi, Ltd.Inventors: Haruhiro Hasegawa, Toshiyuki Aida, Toshikazu Nishino, Mutsuko Hatano, Hideaki Nakane, Tokuumi Fukazawa
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Patent number: 5254869Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.Type: GrantFiled: June 28, 1991Date of Patent: October 19, 1993Assignee: Linear Technology CorporationInventors: John E. Readdie, Benjamin H. Kwan, Jeng Chang
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Patent number: 5241195Abstract: A merged P-I-N/Schottky power rectifier includes trenches, and P-N junctions along the walls of the trenches and along the bottoms of the trenches. By forming the P-N junctions along the trench walls, the total area of the P-N junctions relative to the surface area of the device can be increased, to thereby improve the device's on-state characteristics without sacrificing the total area of the Schottky region. The trenches may be U or V shaped in transverse cross-section or of other transverse cross-sectional shape, and the trenches may be polygonal or circular in top view.Type: GrantFiled: August 13, 1992Date of Patent: August 31, 1993Assignee: North Carolina State University at RaleighInventors: Shang-hui L. Tu, Bantval J. Baliga
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Patent number: 5202571Abstract: An electron emitting device is provided with a p-semiconductor layer formed on a semiconductor substrate. The p-semiconductor layer is composed of a diamond layer.Type: GrantFiled: July 3, 1991Date of Patent: April 13, 1993Assignee: Canon Kabushiki KaishaInventors: Keiji Hirabayashi, Noriko Kurihara, Takeo Tsukamoto, Nobuo Watanabe, Masahiko Okunuki