Abstract: A trench-type MOSgated device including high conductivity regions formed at the bottom of its trenches and field relief regions at or below the bottom of its channel region.

Abstract: A double diffusion MOSFET is disclosed which comprises: a drain region 13 of an N-type semiconductor layer formed on a semiconductor substrate 11; a body region 15 of a P-type semiconductor region formed in the drain region 13; an N-type source region 16 formed in the body region 15; and a gate electrode 21 formed on a surface of the body region 15, wherein the drain region 13 contains N+ type drain contact regions 18 and P+ type regions 19 such that those are put at an equal potential.

Abstract: A lateral double-diffused MOS transistor (LDMOS) has a body zone and additional body regions assigned to the body zone, thereby producing a “deep body.” The deep body results in a quasi one-dimensional course of the potential lines, with the result that the dielectric strength is increased. The self-alignment between gate and channel is preserved, and parameter fluctuations are reduced.

Abstract: A lateral semiconductor device (20) such as LDMOS, a LIGBT, a lateral diode, a lateral GTO, a lateral JFET or a lateral BJT, comprising a drift region (12) having a first surface (22) and a first conductivity type, first and second conductive (4, 8) extending into the drift region from the first surface. The lateral semiconductor device further comprises an additional region (24) or several additional regions, having a second conductivity type, between the first and second semiconductor regions (4, 8), the additional region extending into the drift region from the first surface (22), wherein the additional region forms a junction dividing the electric field between the first and second semiconductor regions when a current path is established between the first and second semiconductor regions. This allows the doping concentration of the drift region to be increased, thereby lowering the on-resistance of the device.

Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

Abstract: In order to improve the characteristics of the high breakdown voltage MOS, a semiconductor device of the present invention is characterized in that an LDMOS transistor, which comprises a source region 4, a channel region 8, and a drain region 5, and a gate electrode 7 formed on the channel region 8, and a drift region formed between the channel region 8 and the drain region 5, wherein an N?-type low concentration layer 22 serving as the drift region is formed shallowly at least below the gate electrode 7 (first N?-type layer 22A) but formed deeply in a neighborhood of the drain region 5 (second N?-type layer 22B).

Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.

Abstract: N+-type diffusion regions, P-type diffusion region and others are formed at and near a surface of an N?-type epitaxial layer on a p-type silicon substrate. Gate electrode portions are formed on P-type diffusion region located between N?-type diffusion regions and N?-type epitaxial layer with a gate insulating film therebetween. A source electrode and a drain electrode are formed. Under a field isolating film, a P-type diffusion region is formed discretely in a direction crossing a direction of a current flow in the on state. Thereby, such a semiconductor device is obtained that rising of an on resistance can be suppressed in an on state while keeping an effect of reducing an electric field.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A device structure of a LDMOSFET has trench type sinker formed using a trench process. A semiconductor layer of a first conductive type is formed within the device structure. A field area is formed in a trench structure on one side of the semiconductor layer and a gate electrode is formed on a given surface of the semiconductor layer. A channel layer of a second conductive type is formed by laterally diffusion from the field area to a width containing both sides of the gate electrode. The source area of LDMOS is electrically connected with the substrate through the sinker. By a piercing through the source area, the sinker divides the source area into two source areas. This division reduces the parasitic resistance as well as parasitic capacitance. In addition, the device structure eliminates the need for high temperature diffusion process and reduces lateral diffusion of the sinker.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.

Abstract: An n-type well is formed in a p?-type semiconductor substrate and a p?-type epitaxial layer is formed on; the n-type well. An n?-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF operation. A p-type island is formed in the n?-type well at a position above the n-type well to form an island region for high withstand-voltage separation. Thus, the withstand voltage of the separated island is improved.

Abstract: The invention relates to a semiconductor component with enhanced avalanche ruggedness. At the nominal current of this semiconductor component, in the event of an avalanche the voltage applied between two electrodes is 6 % or more above the static reverse voltage at the same temperature.

Abstract: A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.

Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.

Abstract: An LDMOS transistor includes drift regions from the body to the drain and the source terminals and is capable of handling high voltages at both the source and drain terminals. In one embodiment, a transistor includes a body region formed in a first well, a conductive gate formed over a first dielectric layer where the first dielectric layer overlies the first well, a second dielectric layer encircling the first dielectric layer, a drain region abutting one edge of the second dielectric layer and a source region abutting an opposite edge of the second dielectric layer. A first drift region is formed between the source region and the body region while a second drift region is formed between the drain region and the body region. Accordingly, the drain and source region of the transistor is interchangeable. In one embodiment, the first and second dielectric layers are a contiguous field oxide layer.

Abstract: A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Abstract: A high withstand voltage semicnductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.

Abstract: A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.

Abstract: A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.

Abstract: An LDMOS transistor includes a body region, a source region, a conductive gate, an alignment structure and a drain region. The conductive gate is insulated from the semiconductor layer by a dielectric layer and overlies the body region. The source region is formed in the body region and is formed self-aligned to a first edge of the conductive gate. The alignment structure is formed adjacent a second edge, opposite the first edge, of the conductive gate. The alignment structure has a first edge in proximity to the second edge of the conductive gate. The drain region is formed in the semiconductor layer self-aligned to the second edge, opposite the first edge, of the alignment structure. The alignment structure can be formed in a polysilicon layer or a dielectric layer. The incorporation of the alignment structure in the LDMOS transistor enables self-aligned drain region or drain contact opening to be formed.

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled togther and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers.

Abstract: A lateral semiconductor device (20) such as LDMOS, a UIGBT, a lateral diode, a lateral GTO, a lateral JFRT or a lateral BJT, comprising a drift region (12) having a first surface (22) and a first conductivity type, first and second conductive regions (4, 8) extending into the drift region from the first surface. The lateral semiconductor device further comprises an additional region (24) or several additional regions, having a second conductivity type, between the first and second semiconductor regions (4, 8), the additional region extending into the drift region from the first surface (22), wherein the additional region forms a junction dividing the electric field between the first and second semiconductor regions when a current path is established between the first and second semiconductor regions. This allows the doping concentration of the drift region to be increased, thereby lowering the on-resistance of the device.

Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first low concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.

Abstract: A level shifter is provided that facilitates reducing high-bias-voltage application to a MOSFET and improving the reliability thereof. The level shifter includes an NMOSFET formed of a first isolated region in the surface portion of a P-type substrate, a source, a channel and a drain in the surface portion of a first isolated region, and a gate above the first isolated region; a second isolated region in the surface portion of P-type substrate and space apart from first isolated region; and high-potential portions including pinch resistance with a high breakdown voltage in second isolated region.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: A lateral conduction superjunction semiconductor device has a plurality of spaced vertical trenches in a junction receiving layer of P− silicon. An N− diffusion lines the walls of the trench and the concentration and thickness of the N− diffusion and P− mesas are arranged to deplete fully in reverse blocking operation. A MOSgate structure is connected at one end of the trenches and a drain is connected at its other end. An N− further layer or an insulation oxide layer may be interposed between a P− substrate and the P− junction receiving layer.

Abstract: A power IC for an automobile engine control unit incorporating at least one semiconductor device comprising an N-channel insulated-gate filed-effect transistor formed on an SOI substrate, having an N-type layer having a concentration higher than a concentration of an N-type layer in contact with a p-body layer contacting a gate oxide film of the transistor. The high concentration N-type layer is formed in a region covering at most 95% of the source-drain distance between the p-body layer and a drain electrode of the transistor in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.

Abstract: Power MOSFET devices provide highly linear transfer characteristics (e.g., Id v. Vg) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Abstract: A power field effect transistor utilizes a retrograded-doped transition region to enhance forward on-state and reverse breakdown voltage characteristics. Highly doped shielding regions may also be provided that extend adjacent the transition region and contribute to depletion of the transition region during both forward on-state conduction and reverse blocking modes of operation. In a vertical embodiment, the transition region has a peak first conductivity type dopant concentration at a first depth relative to a surface on which gate electrodes are formed. A product of the peak dopant concentration and a width of the transition region at the first depth is preferably in a range between 1×1012 cm−2 and 7×1012 cm−2.

Abstract: A bidirectional semiconductor component having two symmetrical MOS transistor structures integrated laterally in a substrate and connected antiserially, their drain terminals being connected to one another. A zone having the same type of conductivity as the drain region yet a higher doping than that of the drain region is situated upstream from a pn junction of one of the MOS transistors in a junction area with the drain region.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: A lateral RF MOS transistor with at least one conductive plug structure comprising: (1) a semiconductor material of a first conductivity type having a first dopant concentration and a top surface; (2) a conductive gate overlying and insulated from the top surface of the semiconductor material; (3) at least two enhanced drain drift regions of the second conductivity type of the RF MOS transistor; the first region laying partially underneath the gate; the second enhanced drain drift region contacting the first enhanced drain drift region, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region; (4) a drain region of the second conductivity type contacting the second enhanced drain drift region; (5) a body region of said RF MOS transistor of the first conductivity type with the dopant concentration being at least equal to the dopant concentration of the semiconductor epi layer; (6) a source region of the second conductivi

Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.

Abstract: A RESURF super-junction device (51) is provided which comprises a plurality of electrodes (53) disposed in a layer of a first material (61) having a first conductivity type. Each of the plurality of electrodes contains a second material (57) of a second conductivity type which is encased in a dielectric material (55).

Abstract: A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift layers and RESURF layers are formed on the first drift layer and periodically arranged in a direction perpendicular to the direction of depth. The RESURF layer forms a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer. The impurity concentration in the first drift layer is different from that in the second drift layer. The drain electrode is electrically connected to the drain layer.

Abstract: Within both a lateral double diffused metal oxide semiconductor (LDMOS) device, and a method for fabrication thereof, there is formed a buried layer of polarity equivalent with a well region within which is formed a drain region. The buried layer is formed laterally aligned with respect to the well region, and separated therefrom by a portion of an epitaxial layer. The lateral double diffused metal oxide semiconductor (LDMOS) device exhibits enhanced electrical performance.

Abstract: A semiconductor component includes a RESURF transistor (100, 200, 300, 400, 500) that includes a first semiconductor region (110, 210, 310, 410, 510) having a first conductivity type and an electrically-floating semiconductor region (115, 215, 315, 415, 515, 545) having a second conductivity type located above the first semiconductor region. The RESURF transistor further includes a second semiconductor region (120, 220, 320, 420, 520) having the first conductivity type located above the electrically-floating semiconductor region, a third semiconductor region (130, 230) having the first conductivity type located above the second semiconductor region, and a fourth semiconductor region (140, 240, 340, 440, 540) having the second conductivity type located above the second semiconductor region.

Abstract: The present invention relates to a nonvolatile memory device having asymmetric source/drain regions and a fabricating method thereof. In the device, a first and second impurity regions are formed in a substrate, and are separated by a first channel region and a second channel region. A tunnel insulating layer, a charge storing layer, and a gate interlayer insulating layer is disposed on the substrate in the first channel region, with the gate interlayer insulating layer being extended over the substrate in the second channel region. A control gate is then disposed over the previously formed layers in both regions. The first channel region and the first impurity region are, respectively, wider than the second channel region and the second impurity region. Thus, the erase speed of the device can be increased in an erase operation, by allowing an increased hot-hole injection rate.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: A high withstand voltage insulated gate N-channel field effect transistor has N-type source and drain regions formed on a semiconductor substrate, and a channel forming region disposed between the source and drain regions. A gate insulating film is disposed over the channel forming region. A gate electrode is formed on the channel forming region through the gate insulating film. N-type low concentration regions are formed between respective ones of the drain region and the channel forming region and the source region and the channel forming region. Second insulating films are formed on respective ones of the low concentration regions. A P-type buried layer is formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, the gate insulating film, and the second insulating films. A P-type well layer is formed in a part of a region under the gate insulating film.

Abstract: A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.

Abstract: Power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage and a method for manufacturing the power devices are described.

Abstract: An LDMOS device is made on a semiconductor substrate 112. It has an N+ source and drain regions 120, 132 are formed within a P well region 122. An interlevel dielectric layer 140 encapsulates biased charge control electrodes 142a and they control the electric field within the area of the drift region 14 between P-base 122 and the N drain region 132 to increase the reverse breakdown voltage of the device. This permits the user to more heavily dope the drift region and achieve a lower on resistance.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.