Abstract: A high voltage integrated circuit (IC) has a passivation structure that shields the underlying circuit from the electrical effects of charge on the passivation structure. In one embodiment, the passivation structure comprises a silicon rich nitride layer in electrical contact with underlying circuit elements. The silicon rich nitride is highly resistive and permits only a negligible current between elements, but is conductive enough that charge on the surface of the passivation structure flows into the IC before the electric fields in the underlying circuit elements is significantly changed. In another embodiment, the passivation structure has two or more layers with a less conductive layer in contact with the underlying IC and overlying conductive layer which shields the IC from the effects of charge build up.

Abstract: A biasing method for and IC with enhanced reverse bias breakdown. A field plate covering the surface PN junction and extending laterally therefrom is biased to partially deplete the island under the field plate and the substrate supporting the island is biased to complete the total depletion of the island under the field plate, establishing a substantially merged vertical field at less than critical for avalanche. Because most of the charge is required to support the vertical component of the field, the rate of change in the horizontal component is small per unit of additional terminal voltage and the lateral extension of the field plate increases the breakdown voltage beyond the plane breakdown for a PN junction of a given doping profile.

Abstract: A semiconductor device of the RESURF type with a lateral DMOST (LDMOST), comprising a semiconductor body (1) of substantially a first conductivity type and a surface region (3) of a second conductivity type adjoining the surface (2). The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3), with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is at a distance from the back gate region (5). A number of breakdown voltage raising zones (9) of the first conductivity type are provided between the back gate region (5) and the drain region (8).

Abstract: An integrated circuit RESURF LDMOS power transistor combines SOI MOS technology with RESURF LDMOS technology to provide a source isolated high voltage power transistor with low "on" resistance for use in applications requiring electrical isolation between the source and substrate.

Abstract: It is usual in high-voltage integrated circuits to provide one or several breakdown-voltage-raising rings at the edge of a high-voltage island in the form of surface zones of the conductivity type opposite to that of the island. According to the invention, the function of these rings is locally taken over by one or several zones forming part of a circuit element and also provided with a breakdown-voltage-raising edge. Since the breakdown-voltage-raising zones are locally omitted alongside the island insulation, a major space saving can be achieved.

Abstract: The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

Abstract: A high breakdown voltage semiconductor device is disclosed which comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first semiconductor region formed on the first insulating layer and isolated at its side by an isolating region, a second semiconductor region of a first conductivity type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region, a third semiconductor region of a second conductivity type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the isolating region in a manner to be spaced apart from the second semiconductor region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region.

Abstract: A power transistor having an epitaxial layer within an isolation region is formed in a semiconductor substrate. A buried diffusion within the substrate with vertical diffusions contacting it form the isolation region. A drain, source, gate, and drift region are formed within the epitaxial layer such that a RESURF LDMOS transistor is formed having its source isolated from the substrate. Multiple power transistors may share the buried isolation region. A P type semiconductor substrate allows the power transistor and high performance CMOS circuitry to be formed on the same semiconductor die.

Abstract: A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5).

Abstract: A semiconductor power device wherein the reverse voltage across the p.sup.+ -regions(s) and the n.sup.+ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n.sup.+ (or p.sup.+)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V.sub.B of the CB-layer invented is Ron ocV.sub.B.sup.113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.