Abstract: A semiconductor apparatus in which the height of the projected electrode (4) formed on the semiconductor element (1) is deformed plastically so as to unify the distance of the protruding surface of the projected electrode (4) and the surface of the electrode terminal (7) at the side of the circuit substrate (5), and the semiconductor element and the circuit substrate are connected electrically with reliability. A method for producing the semiconductor apparatus also is disclosed. After the semiconductor element (1) is positioned on the predetermined part of the circuit substrate (5), the projected electrode (4) is deformed plastically by pushing the semiconductor element (1) from the back and the height of the projected electrode (4) is processed appropriately.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.

Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

Abstract: A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P−-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N+-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 1015-1016 atoms/cm3 where it contacts the semiconductive film.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer.

Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.

Abstract: An N+ buried diffusion region is formed between a P− silicon substrate and an N− epitaxial layer and a P+ buried diffusion region is formed between the N+ buried diffusion region and the N− epitaxial layer. An N diffusion region, a P diffusion region and an N diffusion region are formed in the surface for the N− epitaxial layer. The surface of the P+ buried diffusion region located, approximately, beneath the N diffusion region is recessed so as to go far away from the N diffusion region and a narrowed part is formed in this part. Thereby, in the OFF condition, the depletion layer further extends in the part where the narrowed part is formed. As a result, the withstanding voltage of the semiconductor device is increased.

Abstract: Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are provided in the first and second stripe-shaped trenches, respectively. A UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.

Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Abstract: A semiconductor substrate has a first main surface with a plurality of trenches 5a sandwiching a region in which p and n diffusions regions 2 and 3 are formed to provide a p-n junction along the depth of the trenches. P diffusion region 2 has a doping concentration profile provided by a p dopant diffused from a sidewall surface of one trench 5a, and n diffusion region 3 has a doping concentration profile provided by an n dopant diffused from a sidewall surface of the other trench 5a. A heavily doped n+ substrate region 1 is provided at a second main surface side of p and n diffusion regions 2 and 3. A depth Ld of trench 5a from the first main surface is greater than a depth Nd of p and n diffusion regions 2, 3 from the first main surface by at least a diffusion length L of the p dopant in p diffusion region 2 or the n dopant in n diffusion region 3 in manufacturing the semiconductor device. A high withstand voltage and low ON-resistance semiconductor device can thus be obtained.

Abstract: A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.

Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Abstract: A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.

Abstract: The reduction in breakdown voltage of a device which contains adjoining regions of relatively high and low impurity concentrations within a dielectrically isolated island of an integrated circuit architecture is effectively countered by biasing the material surrounding the island, such as a support polysilicon substrate or the fill material of a isolated trench, at a prescribed bias voltage that is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value that is no more positive than half the difference between the most positive and the most negative of the bias voltages that are applied to the integrated circuit.

Abstract: A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at least one-half of the length of the field oxide layer (20).

Abstract: A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.

Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described and include a layer of amorphous silicon for passivating and terminating the device junctions. The layer of amorphous silicon is deposited atop the metal contact and atop and overlying insulation layer and expose the source pad. A layer of silicon nitride may be deposited atop the layer of amorphous silicon. The layer of amorphous silicon minimizes gate leakage.

Abstract: A composite bump structure and methods of forming the composite bump structure. The composite bump structure comprises a polymer body of relatively low Young's Modulus compared to metals covered by a conductive metal coating formed at the input/output pads of an integrated circuit element or substrate. The composite bump is formed using material deposition, lithography, and etching techniques. A layer of soldering metal can be formed on the composite bumps if this is desired for subsequent processing. A base metal pad covering the integrated circuit element input/output pad can be used to provide added flexibility in location of the composite bump. The composite bump can be formed directly on the input/output pad or on the base metal pad.

Abstract: The high breakdown voltage semiconductor device comprises an insulating film, a semi-insulating high resistance film formed on the insulating film, a first semiconductor layer of the first conductivity type formed on the high resistance film, a second semiconductor layer of the second conductivity type formed on a surface of the first semiconductor layer, a third semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer so as to be apart from the second semiconductor layer, and having an impurity concentration higher than that of the first semiconductor layer, and a resurf layer formed in a space between the second and third semiconductor layers on the surface of the first semiconductor layer, and having an impurity concentration lower than that of the second semiconductor layer.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral MOS device on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and over at least a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A lateral silicon carbide (SiC) semiconductor device includes a SIC substrate of a first conductivity type, a SiC epitaxial layer of the first conductivity type on the substrate and a SiC surface layer on the SiC epitaxial layer. The SiC surface layer has a SiC first region of the first conductivity type, a SiC lateral drift region of a second conductivity type opposite to that of the first conductivity type adjacent the first region and forming a p-n junction therewith, and a SiC second region of the second conductivity type spaced apart from the first region by the drift region. By providing the drift region with a variable doping level which increases in a direction from the first region to the second region, compact SiC semiconductor devices such as high-voltage diodes or MOSFETs can be formed which can operate at high voltages, high temperatures and high frequencies, thus providing a substantial advantage over known devices.

Abstract: A semiconductor component including a silicon carbide substrate. A pn junction includes doped layers of the substrate. The pn junction includes at a surface of the substrate a low doped first conductivity type layer and at a portion of the surface of the substrate a highly doped second conductivity type layer. An edge termination region of the pn junction laterally surrounds the pn junction provided at an edge of at least one of the layers of the pn junction. The edge termination region includes zones of the second conductivity type located at an edge of the highly doped second conductivity type layer. A charge content of the zones decreases toward an edge of the edge termination region in accordance with at least one characteristic selected from the group consisting of a stepwise or continuously decreasing total charge towards an outer border of the edge termination region and a decreasing effective sheet charge density toward an outer border of the edge termination region.

Abstract: A semiconductor component, which comprises a pn junction, where both the p-conducting and the n-conducting layers of the pn junction constitute doped silicon carbide layers and where the edge of at least one of the conducting layers of the pn junction, exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having first and second main surfaces, a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer, the second semiconductor layer including a first region having a relatively high injection efficiency and a second region having a relatively low injection efficiency and the first region being surrounded by the second region, a third semiconductor layer of the first conductivity type formed on the second main surface of the first semiconductor layer, a first electrode selectively formed on the second semiconductor layer of the second conductivity type and connected to at least the first region, and a second electrode formed on the third semiconductor layer of the first conductivity type.

Abstract: A pn-diode of SiC has a first emitter layer part doped with first dopants having a low ionization energy and a second part designed as a grid and having portions extending vertically from above and past the junction between the drift layer and the first part and being laterally separated from each other by drift layer regions for forming a pn-junction by the first part and the drift layer adjacent such portions at a vertical distance from a lower end of the grid portions. The different parameters of the device are selected to allow a depletion of the drift layer in the blocking state form a continuous depleted region between the grid portions, to thereby screen off the high electric field at the pn-junction so that it will not be exposed to high electrical fields.

Abstract: A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.

Abstract: In many circuits in which a current is switched off, a high voltage appears at the drain electrode of a transistor, in particular in the case of an inductive load. When a lateral high-voltage DMOST is used, such a high voltage may lead to instability in the transistor characteristics or may even damage the transistor. To avoid this problem, the drain of a high-voltage LDMOST is locally provided with a strongly doped n-type zone 18, 21 (in the case of an n-channel transistor) which extends, seen from the surface, down into the semiconductor body to a greater depth than does the source zone 8, so that a pn-junction is formed at a comparatively great depth in the semiconductor body having a breakdown voltage that is lower than the BV.sub.ds of the transistor without this zone. The energy stored in the inductance may thus be drained off through breakdown of the pn-junction.

Abstract: A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.

Abstract: A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region.

Abstract: The epitaxial substrate of a semiconductor chip device has a resurf diffusion in at least one of its isolated wells in the device chip surface. The wells are separated by junction diffusions. The thickness of the epitaxial layer is reduced by placing an increased percentage of its total charge for given a breakdown voltage (punch-through voltage) in the lower portion of the layer.

Abstract: A power transistor incorporating a constant-voltage diode maintains the breakdown voltage of the constant-voltage diode at a specified level and prevents local breakdown of an insulating film located between an A1 field plate electrode and a base region of the transistor by spacing the A1 field plate electrode located on a collector region by a distance "d" from the base region.

Abstract: An MOS gated semiconductor device includes a metal source contact electrode which extends across the top of a overlaying oxide layer that is formed atop the gate electrode. The source metal thus extends over the channel region to provide a physical metal shield against the migration of ionic contaminants that may be present in the plastic device housing, particularly during high temperature operation. The metal shield substantially improves the device characteristics under high temperature bias conditions.

Abstract: An integrated device including a structure for protection against electric fields. The protection structure may include a first region of conducting material electrically connected to the gate/source region of the device at a first potential. The protection structure may also include a second region of conducting material electrically connected to the drain region of the device at a second potential differing from the first. In one embodiment, the first region of conducting material is comb-shaped, and includes a first number of fingers separated by a plurality of gaps. The second region of conducting material includes portions extending at the aforementioned gaps to form a comb structure. Thus, the body of semiconductor material of the device sees a protection region formed by a pair of interlocking comb structures at an intermediate potential between the first and second potentials.

Abstract: A back-source MOSFET uses a source electrode on a second surface of a substrate to reduce noise which would otherwise interfere with the logic circuit of a power integrated circuit. One embodiment includes a substrate of a first conductivity type and a base layer of a second conductivity type on a first surface of the substrate. A source region is electrically connected with the substrate. A source electrode is formed on a second surface of the substrate. A further embodiment includes a substrate of a first conductivity type and a base layer of a first conductivity type on a first surface of the substrate. A source electrode is formed on a second surface of the substrate.

Abstract: In a semiconductor electron emission device for causing an avalanche breakdown by applying a reverse bias voltage to a Schottky barrier junction between a metallic material or metallic compound material and a p-type semiconductor, and externally emitting electrons from a solid-state surface, a p-type semiconductor region (first region) for causing the avalanche breakdown contacts a p-type semiconductor region (second region) for supplying carriers to the first region, and a semi-insulating region is formed around the first region.

Abstract: An internal electrostatic discharge (ESD) protection circuit for semiconductor devices defines a structure for protecting adjacent n-channel devices. The first n-channel device includes a pair of n+ regions defining source and drain regions wherein the drain region is connected to a positive power supply terminal (V.sub.DD). The second, adjacent, n-channel device also includes a pair of n+ regions forming source and drain regions, respectively, wherein the source region of the second n-channel device is connected to a negative power supply terminal (V.sub.SS). The drain of the first n-channel device is laterally spaced, and isolated from the source of the second n-channel device by a thick field oxide region. The novel structure includes forming an N-conductivity type well that substantially overlaps the drain n+ region of the first n-channel device and extends toward the n+ region that forms the source of the second n-channel device.

Abstract: The reduction in breakdown voltage of a device which contains adjoining regions of relatively high and low impurity concentrations within a dielectrically isolated island of an integrated circuit architecture is effectively countered by biasing the material surrounding the island, such as a support polysilicon substrate or the fill material of a isolated trench, at a prescribed bias voltage that is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value that is no more positive than half the difference between the most positive and the most negative of the bias voltages that are applied to the integrated circuit.

Abstract: An n- or p-doped semiconductor region accommodates the depletion zone of an active area of the semiconductor component with a vertical extension dependent upon an applied blocking voltage. The junction termination for the active area is constituted with a semiconductor doped oppositely to the semiconductor region, and is arranged immediately adjacently around the active area on or in a surface of the semiconductor region. The lateral extension of the junction termination is greater than the maximum vertical extension of the depletion zone, and the semiconductor region as well as the junction termination are constituted with a semiconductor with a band gap of at least 2 eV.

Abstract: A FET including a channel region and a drift region in a channel layer with a source in the channel region and a drain in the drift region. The current channel between the source and drain defining a straight transistor portion and a curved transistor portion. An oxide with a thin portion overlying the channel region and a thick portion overlying the drift region, and a gate on the thin oxide overlying the current channel. A drain field plate and a gate field plate on the thick oxide with spaced apart edges and a damaged region underlying the edges of the field plates only in the curved transistor portion to reduce electric fields at the edges of the field plates. Also, the current channel has a greater length and the edges are spaced apart farther in the curved transistor portions.

Abstract: A high voltage transistor includes a semiconductor-on-insulator (SOI) region in which a source and a channel are formed. A drain drift region is further formed partly in the SOI region and partly in the bulk silicon region beyond SOI and a gate is coupled to said SOI channel.

Abstract: A lateral semiconductor device with enhanced breakdown characteristics includes a semiconductor substrate composite of first and second semiconductor substrates bonded to one another via an oxide film. An insulation film is buried in a separation trench which extends from a major surface of the first semiconductor substrate to the oxide film. An element region of 10 .mu.m or more in thickness is isolated by the separation trench from other element regions. First and second diffusion regions of opposite conductivity type are formed on the element region. The potential of the second substrate is fixed at one-third of the designed maximum breakdown voltage of the lateral semiconductor device. Alternatively, if the element region is 10 .mu.m or less in thickness, the potential of the second substrate is fixed at one-half of the designed maximum breakdown voltage of the lateral semiconductor device.

Abstract: An object of the present invention is to provide an LD-MOS transistor with a reduced device real estate and high breakdown strength. An extended drain region doped with phosphorus is formed in contact with an underside of an insulation layer and a drain diffusion region, respectively. The insulation layer is deposited over a conductive gate layer and a drain diffusion region, respectively.

Abstract: A semiconductor device of the RESURF type with a "low-side" lateral DMOST (LDMOST), comprising a semiconductor body (1) of predominantly a first conductivity type and a surface region (3) adjoining a surface (2) and of a second conductivity type. The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3) with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is present at a distance from the back gate region (5). A separation region (15) of the first conductivity type is provided around the LDMOST in the surface region (3), which separation region adjoins the surface (2) and extends towards the semiconductor body (1).

Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

Abstract: A semiconductor structure having one or a plurality of lateral, high-blocking semiconductor components in a semiconductor of a metalized substrate (2), a dielectric layer (3) contiguous to the substrate, a homogeneously doped drift zone (4) disposed above the dielectric layer, and having heavily-doped zones of the semiconductor components which are formed in or extend into the drift zone and are electrically contacted. At least the zones (5, 6) of the semiconductor components, which can have a high potential difference with respect to the substrate during operational functioning mode of the semiconductor components, extend up to the dielectric layer (3).

Abstract: A lateral silicon carbide transistor (10) utilizes a modulated channel region (18) to form an accumulation region that facilitates a low on-resistance. A doped region of the channel layer forms a channel insert (14) that also lowers the on-resistance of the transistor (10). A damage termination layer (27) is utilized to facilitate providing a high breakdown voltage. Field plates (23,24) also assists in increasing the breakdown voltage and decreasing the on-resistance of the transistor (10).