Abstract: To reduce the required diffusion depth of impurities in manufacturing a protective diode for protecting an insulated gate transistor from overvoltage so that the diode can be easily built in a chip of the transistor. A plurality of p-type diode layers are built in by diffusion through the windows in an insulation film disposed on an n-type region into which a depletion layers spread when the vertical field effect transistor to be protected is turned off, and a diode terminal A is led out from an electrode film that is in electrical contact with the diode layers. This configuration prevents depletion layers, spreading from the diode layers into the semiconductor region by the applied overvoltage, from joining with each other, and sufficiently lowers the breakdown voltage of the protective diode with respect to the withstand voltage of the transistor 10 or 20 even when the diffusion depth of the diode layer is one order of magnitude shallower than in conventional devices.

Abstract: An auxiliary MOSFET is integrated into a lateral IGBT structure with the source and drain of the auxiliary MOSFET in parallel with the emitter-base circuit of the IGBT. A driver, integrated with the IGBT chip, turns off the base emitter voltage to the IGBT before turning off the auxiliary MOSFET during turn off. The auxiliary MOSFET is turned off again at the beginning of the conduction period to ensure full conductivity modulation of the DMOS drain and maximum gain of the PNP transistor. Short circuit protection and overtemperature protection circuits are also integrated into the chip.

Abstract: A semiconductor device is provided with a surface-inactivated semiconductor layer provided on the surface of a compound semiconductor on which surface a semiconductor layer forming the depletion layer is provided, the semiconductor layer forming the depletion layer being of a conduction type opposite that of the compound semiconductor, and having a carrier density and thickness being capable of forming a depletion layer on the compound semiconductor. When a depletion layer is formed on the surface of the compound semiconductor by the semiconductor layer forming the depletion layer, the depletion layer has no charge so that the concentration of electrical fields is relaxed, the surface of the semiconductor is stabilized, and excellent dielectric breakdown performance is obtained.

Abstract: A lateral semiconductor device is disclosed having a semiconductor body of a first conductivity type, and a drift region having a second conductivity type opposite that of the first conductivity type and formed on a surface of the semiconductor body. A drain region formed in the drift region includes an end portion having a surface area including a predetermined surface radius of curvature and a first surface width; a transitional portion tapers from the first surface width to a second surface width; and a medial portion having the second surface width. A source region is formed in the drift region and spaced from the drain region.

Abstract: A high-breakdown-voltage MOS transistor includes a substrate of one conductivity and a semiconductor layer of the other conductivity type, a drain electrode, a diffusion layer of one conductivity type, a base region of one conductivity type, a source region, a gate electrode, a source electrode, and a heavily doped layer. The diffusion layer and the substrate are electrically connected to the source region.

Abstract: A semiconductor device includes a semiconductor body (1, 2) with an island-shaped region (3) adjoining the surface, in which a contact pad (6) is provided above the island-shaped region (3) and separated therefrom by an insulating layer (5). The island-shaped region (3) forms a pn-junction (34) with an adjoining isolating region (4). According to the invention, the device is provided with regions (40, 41) for increasing the breakdown voltage of the pn-junction (34).

Abstract: A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.

Abstract: A high voltage diode having a field plate and substrate separated from a high impurity concentration region by dielectric layers and biased to deplete the high impurity concentration region therebetween before critical field for avalanche is reached for the region.

Abstract: A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A field effect transistor in the component region has two doped wafer-line gate regions, which have been diffused in the component region with the aid of a first mask. Two heavily doped regions are diffused in the component region with the aid of a second mask, these regions forming the source region and the drain region of the transistor. The semiconductor body is easy to produce and is available commercially, which simplifies manufacture of the field effect transistor. Manufacture is also simplified because the configuration of both the component region and the parts of the transistor are determined by the simple choice of masks. The component region is weakly doped and is easy to deplete of charge carriers.

Abstract: A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).

Abstract: A high voltage silicon carbide MESFET includes an electric field equalizing region in a monocrystalline silicon carbide substrate at a face thereof, which extends between the drain and gate of the MESFET and between the source and gate of the MESFET. The region equalizes the electric field between the drain and gate and between the source and gate to thereby increase the breakdown voltage of the silicon carbide MESFET. The first and second electric field equalizing regions are preferably amorphous silicon carbide regions in the monocrystalline silicon carbide substrate. The amorphous regions are preferably formed by performing a shallow ion implantation of electrically inactive ions such as argon, using the source and drain electrodes and the metal gate as a mask, at a sufficient dose and energy to amorphize the substrate face. A third amorphous silicon carbide region may be formed at the face, adjacent and surrounding the MESFET to provide edge termination and isolation of the MESFET.

Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.

Abstract: A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor, an LIGBT or a lateral thyristor on the insulating layer. The semiconductor device (in the case of an LDMOS transistor) includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region formed of a continuous layer of a lightly-doped semiconductor material on the buried insulating layer, and a drain contact region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. A buried diode is formed in the substrate, and is electrically coupled to the drain contact region by a portion of the drift region which extends laterally in the region between the drain contact region and the buried diode.

Abstract: A high voltage integrated circuit (IC) has a passivation structure that shields the underlying circuit from the electrical effects of charge on the passivation structure. In one embodiment, the passivation structure comprises a silicon rich nitride layer in electrical contact with underlying circuit elements. The silicon rich nitride is highly resistive and permits only a negligible current between elements, but is conductive enough that charge on the surface of the passivation structure flows into the IC before the electric fields in the underlying circuit elements is significantly changed. In another embodiment, the passivation structure has two or more layers with a less conductive layer in contact with the underlying IC and overlying conductive layer which shields the IC from the effects of charge build up.

Abstract: A biasing method for and IC with enhanced reverse bias breakdown. A field plate covering the surface PN junction and extending laterally therefrom is biased to partially deplete the island under the field plate and the substrate supporting the island is biased to complete the total depletion of the island under the field plate, establishing a substantially merged vertical field at less than critical for avalanche. Because most of the charge is required to support the vertical component of the field, the rate of change in the horizontal component is small per unit of additional terminal voltage and the lateral extension of the field plate increases the breakdown voltage beyond the plane breakdown for a PN junction of a given doping profile.

Abstract: A semiconductor device of the RESURF type with a lateral DMOST (LDMOST), comprising a semiconductor body (1) of substantially a first conductivity type and a surface region (3) of a second conductivity type adjoining the surface (2). The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3), with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is at a distance from the back gate region (5). A number of breakdown voltage raising zones (9) of the first conductivity type are provided between the back gate region (5) and the drain region (8).

Abstract: It is usual in high-voltage integrated circuits to provide one or several breakdown-voltage-raising rings at the edge of a high-voltage island in the form of surface zones of the conductivity type opposite to that of the island. According to the invention, the function of these rings is locally taken over by one or several zones forming part of a circuit element and also provided with a breakdown-voltage-raising edge. Since the breakdown-voltage-raising zones are locally omitted alongside the island insulation, a major space saving can be achieved.

Abstract: The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

Abstract: A high breakdown voltage semiconductor device is disclosed which comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a first semiconductor region formed on the first insulating layer and isolated at its side by an isolating region, a second semiconductor region of a first conductivity type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region, a third semiconductor region of a second conductivity type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the isolating region in a manner to be spaced apart from the second semiconductor region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region.

Abstract: The efficiency of semiconductor cathodes based on avalanche breakdown is enhanced by using ".delta.-doping" structures. The quantization effects introduced thereby decrease the effective work function. A typical cathode structure has an n-type semiconductor region and a first p-type semiconductor region, with the n-type region having a thickness of at most 4 nanometers.

Abstract: A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5).

Abstract: A semiconductor power device wherein the reverse voltage across the p.sup.+ -regions(s) and the n.sup.+ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n.sup.+ (or p.sup.+)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V.sub.B of the CB-layer invented is Ron ocV.sub.B.sup.113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.