Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate including first and second areas; a first contact plug contacted with the substrate through the interlayer dielectric layer of the second area; an anti-peeling layer formed over the interlayer dielectric layer including the first contact plug; a second contact plug contacted with the substrate through the anti-peeling layer and the interlayer dielectric layer in the first area; and a variable resistance pattern contacted with the second contact plug.

Abstract: A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer.

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming an insulation layer on an access device followed by forming vias through the insulation layer to expose the first and second access device terminals. First and second interlayer conductors extending through the vias are formed next. Top surfaces of the interlayer conductors are oxidized to form oxide layers. The oxide layer on the first interlayer conductor forms a memory layer. On top of the insulation layer a layer of protection metal is formed covering the oxide layers. The layer of protection metal is patterned and etched to form a top electrode layer covering the memory layer. The oxide layer on the second interlayer conductor is removed. Parallel first and second access lines are then formed on the top electrode layer and the second interlayer conductor, respectively.

Abstract: An electronic device includes a switch element. The switch element includes a first electrode including a first metal nitride which is conductive, a second electrode, a switching layer interposed between the first electrode and the second electrode, and a first barrier layer which is interposed between the first electrode and the switching layer and includes a second metal nitride which is insulative, wherein a metal in the first metal nitride is the same as a metal in the second metal nitride, and a metal-to-nitrogen bonding ratio of the first metal nitride is different from a metal-to-nitrogen bonding ratio of the second metal nitride.

Abstract: A resistance changing element according to the present invention comprises a first electrode (101) and a second electrode (103); and an ion conducting layer (102) that is formed between the first electrode (101) and the second electrode (103) and that contains at least oxygen and carbon.

Abstract: Provided are a semiconductor device. The semiconductor device includes a memory block including a drain select line, word lines, and a source select line, which are spaced apart from one another and stacked in a direction perpendicular to a semiconductor substrate; and a peripheral circuit including a switching device connected to a bit line, which is disposed under a vertical channel layer vertically passing through the drain select line, the word lines, and the source select line.

Abstract: A resistive RAM and a method of manufacturing the same are provided. The resistive RAM includes a first electrode, a second electrode, a transition metal oxide (TMO) layer between the first and second electrodes, an activated metal layer between the first electrode and the TMO layer, and a metal oxynitride layer formed on a surface of the activated metal layer in the gas environment containing oxygen and nitrogen elements.

Abstract: An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer which is formed over a substrate; a contact plug which is coupled with the substrate by passing through the inter-layer dielectric layer and has a protruding portion over the inter-layer dielectric layer; a first variable resistance pattern which is formed over the contact plug; and a protective layer which covers the first variable resistance pattern and a portion of sidewalls of the contact plug in such a manner that the sidewalls of the contact plug are exposed.

Abstract: In one example, a customizable nonlinear electrical device includes a first conductive layer, a second conductive layer, and a thin film metal-oxide layer sandwiched between the first conductive layer and the second conductive layer to form a first rectifying interface between the metal-oxide layer and the first conductive layer and a second rectifying interface between the metal-oxide layer and the second conductive layer. The metal-oxide layer includes an electrically conductive mixture of co-existing metal and metal oxides. A method forming a nonlinear electrical device is also provided.

Abstract: An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface.

Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased.

Abstract: A resistance change memory device with a high ON/OFF radio can be provided according to an embodiment includes a first electrode containing a first element, a resistance change layer provided on the first electrode and containing an oxide of the first element, an oxygen conductive layer provided on the resistance change layer, containing a second element and oxygen, having oxygen ion conductivity, and having a relative permittivity higher than a relative permittivity of the resistance change layer, and a second electrode provided on the oxygen conductive layer. The resistance change layer undergoes dielectric breakdown earlier than the oxygen conductive layer when a voltage between the first electrode and the second electrode is continuously increased from zero.

Abstract: A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.

Abstract: A phase change memory and its fabrication method are provided. A bottom electrode structure is provided through a substrate. A mask layer is formed on the substrate and the bottom electrode structure. A first opening is formed in the mask layer to expose the bottom electrode structure. A spacer is formed on sidewalls and bottom surface portions of the first opening to expose a surface portion of the bottom electrode structure. The first opening including the spacer therein has a bottom width less than a top width. A heating layer is formed at least on the surface portion of the bottom electrode structure exposed by the spacer. A phase change layer is formed on the heating layer to completely fill the first opening. A top electrode is formed on the phase change layer and the mask layer.

Abstract: An electronic device includes a first electrode made of an inert material; a second electrode made of a soluble material; a solid electrolyte made of an ion-conductive material, wherein the first and second electrodes are in contact respectively with one of the faces of the electrolyte, either side of the electrolyte, wherein the second electrode supplies mobile ions flowing in the electrolyte towards the first electrode, to form a conductive filament when a voltage is applied between the first and second electrodes. The second electrode is a confinement electrode that includes an end surface in contact with the electrolyte which is less than the available surface of the electrolyte, such that confinement of the contact area of the confinement electrode on the solid electrolyte is obtained.

Abstract: A memory cell is included which has a selection transistor and a variable resistance device connected to a bit line through the selection transistor. The variable resistance device includes a first electrode which has a first metal material and is connected to the selection transistor, a second electrode which has a second metal material different from the first metal material, and an insulating film which is provided between the first electrode and the second electrode, has a third metal material different from the first metal material and the second metal material, and has oxygen. The second metal material has a greater normalized oxide formation energy than the first metal material.

Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (?) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

Abstract: A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, a second conductive layer, and a resistance change layer provided between the first conductive layer and the second conductive layer. The resistance change layer is capable of making a transition between a low-resistance state and a high-resistance state, and includes an oxide containing at least one of hafnium (Hf) and zirconium (Zr), at least one selected from the group consisting of barium (Ba), lanthanum (La), gadolinium (Gd) and lutetium (Lu), and nitrogen (N).

Abstract: A thin cap of metal alloy or metal-silicon compound is formed over a ternary oxide or ternary nitride ReRAM embedded resistor. At least one metal in the cap is the same as a metal in the embedded resistor. If the cap oxidizes slightly (e.g., incidental to a vacuum break, anneal, or subsequent treatment or deposition), the overall resistance of the memory cell is much less affected than it would be by the same amount of oxidation directly on a surface of the uncapped oxide or nitride embedded resistor.

Abstract: Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes.

Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer.

Abstract: A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating material element is positioned over and in contact with the first electrode. A phase change material is positioned over the first electrode and in contact with sidewalls of the insulating material element. The phase change material has a first surface in contact with a surface of the first electrode and a surface of the first dielectric material. A second electrode is in contact with a second surface of the phase change material, which is opposite to the first surface.

Abstract: A resistive memory device includes: a resistive layer which includes a first magnetic layer, a second magnetic layer, and a tunnel insulating layer interposed between the first magnetic layer and the second magnetic layer, and is switched between different resistance states; and a strained film formed over a sidewall of the resistive layer and applying a strain to the resistive layer, wherein the strained film includes a semiconductor material containing ions implanted therein

Abstract: A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to the memory cell via the first line and the second line, wherein the access circuit, on writing data in the access cell, uses a non-access-side first line driver to electrically connect a non-access first line adjacent to an access first line to a first potential power supply via a diode-connected transistor.

Abstract: A variable resistance layer between a first electrode and a second electrode includes: a first variable resistance layer contacting the first electrode; and a second variable resistance layer contacting the second electrode and having a lower degree of oxygen deficiency than the first variable resistance layer. A principal face of the first variable resistance layer which is close to the second variable resistance layer is flat. The second variable resistance layer is in contact with both the first variable resistance layer and the second electrode in a polygonal region including a vertex inward of an outline of the variable resistance layer and vertices along the outline when seen from a direction perpendicular to the principal face of the variable resistance layer, and is not in contact with at least one of the first variable resistance layer and the second electrode in a region outside the region inside the polygon.

Abstract: A memory cell (32C), including a first non-insulator (34C) and a second non-insulator (40C), different from the first non-insulator. The second non-insulator forms a junction (46C) with the first non-insulator. The cell further includes a first electrode (48C) which is connected to the first non-insulator and a second electrode (50C) which is connected to the second non-insulator. At least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.

Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. A second non-conductive layer is deposited above the first non-conductive layer. A second well is defined by the second non-conductive layer and positioned directly above the first well. A second electrically conductive liner lines at least one wall of the second well such that the second electrically conductive liner is not in physical contact with the first electrically conductive liner. Furthermore, the phase change material is deposited in the second well.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.

Abstract: A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.

Abstract: A solid state memory comprises a top electrode, a bottom electrode and an insulating switching medium that is disposed at a thickness based on a predetermined function. The insulating switching medium generates a conduction path in response to an electric signal applied to the device. The thickness of the insulating switching medium is a function of a filament width of the conduction path and operates to prevent rupture of a semi-stable region. The semi-stable region maintains filament structure over time and does not degrade into retention failure. The solid state memory can comprise one or more conducting layers that can operate to control the conductance at an on-state of the memory and offer oxygen vacancies or metal ions to the switching medium. The function of the thickness of the insulating switching medium can vary depending upon the number of conduction layers disposed at the insulating switching medium.

Abstract: A method of manufacturing a non-volatile memory element includes forming a first electrode; forming a variable resistance layer; and forming a second electrode. Forming the variable resistance layer includes forming a third metal oxide layer having a third metal oxide, forming a second metal oxide layer having a second metal oxide, and forming a first metal oxide layer e having a first metal oxide; wherein the variable resistance layer reversibly changes its resistance value in response to an electric signal applied between the first electrode and the second electrode; the first metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the second metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the third metal oxide is an oxygen-deficient metal oxide; and the first metal oxide layer is different in density from the second metal oxide layer.

Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element.

Abstract: A non-volatile memory cell and a magnetic field-partitioned non-volatile memory for multi-bit storage are provided. The non-volatile memory cell for multi-bit storage includes a bottom electrode. A resistance-changing memory material covers the bottom electrode. A top electrode including a high-mobility material is disposed on the resistance-changing memory material. The top electrode has two post portions supporting a bar-shaped portion. At least two bits are stored in portions of the resistance-changing memory material connecting to the top electrode when an external magnetic field is applied along different directions.

Abstract: An object is to control composition and a defect of an oxide semiconductor. Another object is to increase field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with off current suppressed. The oxide semiconductor is represented by InMO3(ZnO)n (M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and n is a non-integer number of greater than or equal to 1 and less than 50) and further contains hydrogen. In this case, the concentration of Zn is made to be lower than the concentrations of In and M (M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al). In addition, the oxide semiconductor has an amorphous structure. Here, n is preferably a non-integer number of greater than or equal to 50, more preferably less than 10.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include first, second and third conductive lines disposed at different vertical levels to define two intersections, and two memory cells disposed at the two intersections, respectively. The first and second conductive lines may extend parallel to each other, and the third conductive line may extend to cross the first and second conductive lines. The first and second conductive lines can be alternatingly arranged along the length of third conductive line in vertical sectional view, and the third conductive line may be spaced vertically apart from the first and second conductive lines.

Abstract: A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the memory cells, including the formation of a layer of a phase-change material having an original amorphous state at the end of the steps of manufacturing the memory cells. The method for implementing the embedded system includes, after the steps of manufacturing the memory cells, at least the following steps: (i) pre-programming the memory device consisting of an electrical recrystallization of a selection of memory cells from their original amorphous state; and (ii) assembling the pre-programmed memory device in the system during which the device is subjected to a temperature of between 240° C. and 300° C.

Abstract: A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode.

Abstract: A variable resistance memory device includes a lower electrode on a substrate, a variable resistance pattern on the lower electrode, and an upper electrode on the variable resistance pattern. The upper electrode is in contact with at least a sidewall of the variable resistance pattern.

Abstract: A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.

Abstract: Various embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to one or more memory elements, to store information. The electrode may comprise a number of metals, where a first one of the metals has a Gibbs free energy for oxide formation lower than the Gibbs free energy of oxidation of a second one of the metals.

Abstract: According to example embodiments, a resistance switching material element includes a resistance switching material layer between a first electrode and a second electrode, and a self-rectifying layer provided between the resistance switching material layer and one of the first and second electrodes. The second electrode may be on the first electrode.

Abstract: A semiconductor device includes a substrate extending in a horizontal direction. An active pillar is present on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate. A variable resistive pattern is present on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof. A gate is present at a sidewall of the active pillar.

Abstract: Phase-change memory cells for storing information in a plurality of programmable cell states. A phase-change component is located between first and second electrodes for applying a read voltage to the phase-change component to read the programmed cell state. The component includes opposed layers of phase-change material extending between the electrodes. A core component extends between the electrodes in contact with respective inner surfaces of the opposed layers. An outer component extends between the electrodes in contact with respective outer surfaces of the opposed layers. At least one of the core and outer component is formed of electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than the amorphous phase of the phase-change material in any of said cell states. The current path has a length dependent on size of the amorphous phase in the opposed layers.

Abstract: According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.

Abstract: In a method of manufacturing a variable resistance non-volatile memory device including non-volatile memory element layers stacked together by repeating the step (S100, S200 . . .

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.