Abstract: Provided are a conductive bridging random access memory (CBRAM) device and a manufacturing method thereof. The CBRAM device includes a first electrode, a semiconductor oxide electrolyte layer formed on the first electrode and including a plurality of metal vacancies, a second electrode formed on the semiconductor oxide electrolyte layer, wherein when a positive voltage is applied to the second electrode, cations are reduced to the metal vacancies in the semiconductor oxide electrolyte layer to form a metal bridge.

Abstract: The present invention relates to memristive devices including a resistance-switching element and a barrier element. In particular examples, the barrier element is a monolayer of a transition metal chalcogenide that sufficiently inhibits diffusion of oxygen atoms or ions out of the switching element. As the location of these atoms and ions determine the state of the device, inhibiting diffusion would provide enhanced state retention and device reliability. Other types of barrier elements, as well as methods for forming such elements, are described herein.

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction.

Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Abstract: A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.

Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.

Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.

Abstract: Novel structures and compositions for multilayer light-emitting electrochemical cell devices are described, particularly those that are adapted to work with stable and printable electrode metals, that optimize recombination efficiency, lifetime and turn-on kinetics. In particular, embodiments of the present invention provide improved performance and extended lifetime for doped electronic devices, where ionic doping levels, ionic support materials content, and electronic transport content are advantageously structured within the device. The doping profile of mobile or semi-mobile ionic dopants is intentionally made to be non-uniform to enhance doping in the interface regions of a device where the active layer interfaces with the electrode.

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.

Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

Abstract: A method for producing a device includes depositing a lower electrode metal and a film whose resistance changes. The film whose resistance changes and the lower electrode metal are etched to form a pillar-shaped phase-change layer and a lower electrode. A reset gate insulating film and a reset gate metal are deposited and etched to form reset gates.

Abstract: A charge trapping memristor is disclosed. An example charge trapping memristor includes a first electrode and second electrode configured on opposite sides of a channel to generate an electric potential across the channel, and a charge barrier. The example charge trapping memristor also includes a charge trapping material configured to store and release an electric charge therein, wherein storing and releasing the electric charge changes electrical properties of the channel.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a plurality of first memory elements and a plurality of first interlayer dielectric layers alternately stacked along a first side surface of the vertical electrode; and a plurality of second memory elements and a plurality of second interlayer dielectric layers alternately stacked along a second side surface of the vertical electrode, and the plurality of first memory elements correspond to the plurality of second interlayer dielectric layers, respectively, in the vertical direction.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

Abstract: A resistive random access memory including a first electrode, a separating medium, a resistance changing layer and a second electrode is disclosed. The first electrode has a mounting face. The separating medium is arranged on the first electrode and forms a through hole. A part of the first electrode is not covered by the separating medium. The separating medium has a first dielectric. The resistance changing layer extends along the part of the first electrode as well as along an inner face and the second face of the separating medium. The resistance changing layer has a second dielectric having a dielectric constant larger than a dielectric constant of the first dielectric by 2 or less. The second electrode is arranged on the resistance changing layer. In this arrangement, the problem of unstable forming voltage of the conventional resistive random access memory can be solved.

Abstract: A memory device comprising a conglomerate material interposed between a first electrode and a second electrode is provided. The conglomerate material includes nanocrystalline grains embedded in an amorphous matrix. During operations, phase change reactions occur at the inter-grain boundaries in the conglomerate material so as to reduce the operation power.

Abstract: Provided is an electronic device. The electronic device according to an implementation of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate; an interlayer insulating layer formed over the substrate; a metal-containing insulating layer formed over the interlayer insulating layer and including a second metal; a contact hole formed through the interlayer insulating layer and the metal-containing insulating layer; a contact plug filling a portion of the contact hole; a contact pad formed over the contact plug so as to fill the remaining portion of the contact hole; and a variable resistance element formed over the contact pad, wherein the contact pad includes a metal-containing material including a first metal, and the second metal has a higher electron affinity than the first metal.

Abstract: A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase.

Abstract: Memories and methods of operating memories having memory cells sharing a resistance variable material.

Abstract: A double self-aligned phase change memory device structure, comprising spaced-apart facing phase change memory film members symmetrically arranged with respect to one another, each of the phase change memory film members at an upper portion thereof being in contact with a separate conductive element, and each of the phase change memory film members being in a range of from 5 nm to 25 nm in thickness. Also described are various methods of making such phase change memory device structure.

Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.

Abstract: A resistive random access memory (RRAM) cell with a composite capping layer is provided. A tantalum oxide based layer is arranged over a bottom electrode layer. The composite capping layer is arranged over and abutting the tantalum oxide based layer. The composite capping layer includes a first metal layer and a second metal layer overlying the first metal layer. The first metal layer is more reactive with the tantalum oxide based layer than the second metal layer. A top electrode layer is arranged over the composite capping layer. A method for manufacturing the RRAM cell is also provided.

Abstract: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.

Abstract: A method for manufacturing a memory device of an embodiment includes: forming on a substrate a block copolymer layer which contains a first polymer and a second polymer having lower surface energy than that of the first polymer; performing thermal treatment on the block copolymer layer, to separate the block copolymer layer such that a first phase containing the first polymer and extending in the first direction and a second phase containing the second polymer and extending in the first direction are alternately arrayed; selectively forming on the first phase a first metal wiring layer extending in the first direction; forming on the first metal wiring layer a memory layer where resistance changes by application of a voltage; and forming on the memory layer a second metal wiring layer which extends in a second direction intersecting in the first direction.

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Abstract: A semiconductor integrated circuit according to an embodiment includes: N (?1) input wiring lines; M (?1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (>M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines.

Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Abstract: A method of forming an RRAM cell structure is provided. The method includes forming dummy features over a substrate, and the dummy features have a gap therebetween. The method also includes depositing an oxide layer over the dummy features while forming a first V-shaped valley on the oxide layer. The method further includes partially planarizing the oxide layer while leaving the first V-shaped valley. In addition, the method includes forming a first electrode over the oxide layer while forming a second V-shaped valley on the first electrode. The method further includes forming a resistance variable layer over the first electrode in a conformal manner. The method still includes forming a second electrode over the resistance variable layer.

Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

Abstract: Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.

Abstract: A three-dimensional nonvolatile memory device includes a substrate defined with a slimming region, first and second pass regions on both sides of the slimming region, and a cell region adjacent to the slimming region with the first pass region interposed therebetween; a word line stack including a plurality of word lines stacked over the cell region, the first pass region, and the slimming region of the substrate; first wiring lines extending from the slimming region to the first pass region and electrically coupling some word lines with pass transistors formed in the first pass region of the substrate; and second wiring lines extending from the slimming region to the second pass region and electrically coupling remaining word lines, other than the some word lines, with pass transistors formed in the second pass region of the substrate.

Abstract: Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.

Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.

Abstract: A voltage-controlled spintronic device includes a magnetic layer having an effective anisotropy Keff; a non-magnetic insulating layer; a contact layer; the magnetic layer having an anisotropy switching threshold such that application of a polarization voltage Vmax allows switching of the effective anisotropy Keff from a direction perpendicular to the reference plane to a direction in the reference plane or vice versa, the magnetic layer including a first layer, with thickness tB, having a volume anisotropy KVB; a second layer, with thickness tA, having a surface anisotropy KSA and a volume anisotropy KVA; the surface anisotropy KSA and the volume anisotropies KVA and KVB respecting, over a given operating temperature range: Min(KSA(V=0), KSA(V=Vmax))<?{KVBtB+KVAtA)<Max(KSA(V=0), KSA(V=Vmax)). KSA(V=0) is the surface anisotropy when no polarization voltage is applied. KSA(V=Vmax) is the surface anisotropy when a polarization voltage Vmax is applied.

Abstract: An IGBT (15) is formed in a semiconductor substrate (1). A temperature sense diode (17) made of polysilicon or amorphous silicon is formed on the semiconductor substrate (1). After forming the IGBT (15), the temperature sense diode (17) is divided into a plurality of diodes by selectively oxidizing or sublimating part of the temperature sense diode (17). Thus, influences of variations in finished dimension of polysilicon on the characteristics can be eliminated. As a result, it is possible to reduce the size while reducing characteristic variations.

Abstract: Provided are resistive switching cells and methods of using such cells for controlling operation of liquid crystal display (LCD) cells in LCD devices. A resistive switching cell has two electrodes formed from transparent conductive oxides, such as indium oxide, indium tin oxide, or zinc oxide. One electrode may be connected to a LCD cell thereby forming an in series connection between the resistive switching cell and LCD cell. The other electrode may be used to power the LCD cell through the resistive switching cell. The resistive switching cell also includes a resistive switching layer disposed between the two electrodes. When the resistive switching layer is in its low resistive state, the LCD cell is subjected to an operating potential and produces light. However, when the resistive switching layer is in its high resistive state, the LCD cell is not subjected to the operating potential and does not produce light.

Abstract: A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract: A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer includes a chalcogen element, oxygen, and one or more transition metal elements selected from the group of Groups 4, 5, and 6 elements of the Periodic Table.

Abstract: The present disclosure relates to an RRAM cell having a multi-layer bottom electrode with an insulating core, which provides for good gap fill ability, and an associated method of formation. In some embodiments, the RRAM cell has a multi-layer bottom electrode with an insulating bottom electrode (BE) layer arranged laterally between sidewalls of a conductive lower BE layer and vertically between the conductive lower BE layer and a conductive upper BE layer. A dielectric data storage layer having a variable resistance is arranged over the multi-layer bottom electrode, and a top electrode is arranged over the dielectric data storage layer. The insulating core of the bottom electrode is better able to fill gaps with large aspect ratios than conductive materials, thereby giving the multi-layer bottom electrode a planar upper surface that avoids topography problems in overlying layers.

Abstract: A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.

Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.