Abstract: A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a spherical core-shell structure containing: a spherical conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. The resistance-switchable material is capable of exhibiting complementary resistive switching characteristics with improved reliability and stability as symmetrical uniform filament current paths are formed in respective resistive layers adjacent to two electrodes with the conductive core of the complementary resistance-switchable filler at the center due to the electric field control effect by the spherical complementary resistance-switchable filler.

Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.

Abstract: A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.

Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: A phase change material (PCM) device is disclosed. The PCM device includes a bottom electrode and an insulator layer over the bottom electrode. The PCM device further includes a resistive electrode over the insulator layer with a via in the insulator layer between one end of the resistive electrode and the bottom electrode. The PCM device further includes a PCM region over the resistive electrode and a top electrode over the PCM region.

Abstract: A light emitting diode memory includes a substrate, a tunneling structure, a current spreading layer, a first electrode layer and a second electrode layer. The tunneling structure is formed on the substrate. The tunneling structure includes first, second and third material layers. The current spreading layer is formed on the tunneling structure. The first electrode layer is formed on the substrate. The second electrode layer is formed on the current spreading layer. When a bias voltage applied to the first electrode layer and the second electrode layer is higher than a reset voltage, the light emitting diode memory is in a reset state. When the bias voltage is lower than a set voltage, the light emitting diode memory is in a set state. When the bias voltage is higher than a turn-on voltage, the light emitting diode memory emits a light beam.

Abstract: A method of manufacturing an integrated circuit system, includes, in part, providing a planar surface on an insulator, forming first and second bottom electrodes over the insulator substrate, forming a first electrolyte over the first and second bottom electrodes, forming a first top electrode over the first electrolyte, forming and depositing a second bottom electrode over the insulator substrate, patterning and removing the first top electrode and the first electrolyte from regions above the second bottom electrode, forming a second electrolyte above the second bottom electrode and the first tope electrode, forming a second top electrode above the second electrolyte, and patterning and removing the second top electrode and the second electrolyte from regions above the first bottom electrode.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

Abstract: Processing methods may be performed to remove unwanted materials from a substrate, such as a native oxide material. The methods may include forming an inert plasma within a processing region of a processing chamber. Effluents of the inert plasma may be utilized to modify a surface of an exposed material on a semiconductor substrate within the processing region of the semiconductor chamber. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified surface of the exposed material from the semiconductor substrate.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: According to one embodiment, a semiconductor includes a first wiring, a second wiring, a first electrode, a second electrode and a memory cell. The first wiring extends in a first direction. The second wiring extends in a second direction crossing the first direction. The first electrode is connected to the first wiring. The second electrode is connected to the second wiring. The memory cell is arranged between the first electrode and the second electrode. The memory cell includes a memory element electrically connected to the first electrode, and a selector provided between the memory element and the second electrode and electrically connected to the second electrode, and the memory element and the selector are of a same conductivity type.

Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.

Abstract: A memory structure for use in a memory device comprising at least one first layer and at least one second layer: the at least one first layer comprises a plurality of a first element, and the at least one second layer comprises a plurality of a second element; and, wherein the memory structure has an electrical resistive state that can be changed in response to an electromotive force being applied thereto.

Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

Abstract: A memory device includes: a first conductive column structure extending through a first dielectric layer, wherein the first conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to one end of the shell portion and disposed below the core structure; and a first phase change material layer formed over the first dielectric layer, wherein a lower boundary of the first phase change material layer contacts at least a first portion of the other end of the shell portion of the first conductive column structure.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

Abstract: In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.

Abstract: A resistance change memory element includes a lower electrode, a variable resistive layer disposed on the lower electrode and configured to include an oxygenated carbon structure, a barrier layer disposed on the variable resistive layer and configured to include an oxygen containable material that is able to be reversibly oxidized and reduced, and an upper electrode disposed on the barrier layer.

Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Abstract: A method of manufacture of a non-volatile memory system comprising: forming a dielectric layer having a hole; depositing a first electrode in the hole of the dielectric layer; applying an ion source layer over the first electrode; and depositing a second electrode over the ion source layer including: depositing an interface layer on the ion source layer, and applying a cap layer on the interface layer.

Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a barrier layer over at least one conductive line of the plurality of conductive lines, the barrier layer directly contacting an entire upper surface of the at least one conductive line, and forming a RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode over the barrier layer.

Abstract: Some embodiments relate to a method. A semiconductor substrate is received. The semiconductor substrate has an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate. A bottom electrode and a top electrode are formed over the interconnect structure over the memory region. The bottom electrode is coupled to a lower metal layer in the interconnect structure, and the bottom and top electrode are separated from one another by a data storage or dielectric layer. An interlayer dielectric (ILD) layer is formed over the top electrode. A trench opening having vertical or substantially vertical sidewalls is formed in the ILD layer and exposes an upper surface of the top electrode. An upper metal layer is formed in the trench opening and is in direct contact with the top electrode.

Abstract: A variable resistance memory device includes a pattern of one or more first conductive lines, a pattern of one or more second conductive lines, and a memory structure between the first and second conductive lines. The pattern of first conductive lines extends in a first direction on a substrate, and the first conductive lines extend in a second direction crossing the first direction. The pattern of second conductive lines extends in the second direction on the first conductive lines, and the second conductive lines extend in the first direction. The memory structure vertically overlaps a first conductive line and a second conductive line. The memory structure includes an electrode structure, an insulation pattern on a central upper surface of the electrode structure, and a variable resistance pattern on an edge upper surface of the electrode structure. The variable resistance pattern at least partially covers a sidewall of the insulation pattern.

Abstract: The present invention provides a printed circuit board comprising: a dielectric layer (130); N pairs of differential signal vias (2) which penetrate through the dielectric layer wherein N is an integer more than one; N pairs of first strip conductors (101, 102) disposed on a first surface of the dielectric layer; a first ground conductor layer (103) disposed in the dielectric layer forming N first differential transmission lines (100) with the N pairs of first strip conductors and the dielectric layer; N pairs of second strip conductors (111,112) disposed on a second surface of the dielectric layer; a second ground conductor layer (113) disposed in the dielectric layer forming N of second differential transmission lines (110) with the N pairs of second strip conductors and the dielectric layer.

Abstract: A variable resistance memory device including a first conductive line extending in a first direction on a substrate, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell pillar connected to the first conductive line and the second conductive line at a crossing point therebetween and including a heating electrode layer and a variable resistance layer in contact with the heating electrode layer such that both sidewalls of the heating electrode layer are aligned with both sidewalls of the first conductive line in the first direction.

Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures.

Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.

Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.

Abstract: A method for manufacturing a memory cell includes forming a stack of layers comprising a first electrode and a dielectric layer, and forming a second electrode. Forming the second electrode includes depositing the second electrode on the dielectric layer, and defining the contour of the second electrode in such a way that the second electrode forms a protruding element above the dielectric layer having inclined flanks, the angle between the flanks of the second electrode forming an acute angle with the plane wherein the dielectric layer mainly extends.

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Abstract: A switch actuating device for actuating a switch by eight types of non-tactile gestures performed with an object emitting heat includes a gesture sensor with four pixels configured to detect heat emitted by the object. The pixels include thin films made of pyroelectric sensitive material which generate a signal that has signal deflections corresponding to a temporal intensity curve of the heat detected by the thin film of the corresponding pixel. The types of the gestures are determined with a signal processing unit which controls an actuator to actuate the switch when a performance of one of the types of the gestures is determined. The gesture types are determined during an approach phase when the object approaches the gesture sensor, a waiting phase during when the object remains close to the gesture sensor, and a subsequent translational phase when the object moves in one of eight directions.

Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode. A bottom dielectric layer is disposed on the first side of the bottom electrode around the gate structure. A top dielectric layer is disposed on the first side of the top electrode around the gate structure. A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode.

Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.

Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.

Abstract: A device for storing and/or transferring quantum data. The device has a plurality of elongate semiconductor structures arranged in side by said with each elongate semiconductor structure having a quantum well layer of one semiconductor material disposed between upper and lower layers of a different semiconductor material which share the same or essentially the same crystalline structure as that of the quantum well layer. Neighboring ones of the elongate semiconductor structures share a region forming a constriction between the neighboring ones of the elongate semiconductor structures.

Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

Abstract: A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 1×10-4 ohm-m.

Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.