Abstract: Provided are a phase change material containing carbon (C), a memory device including the phase change material, and a method of operating the memory device. The phase change material contains a main compound and an additive, wherein the main compound is In—Sb—Te and the additive includes carbon (C). A content a of the carbon (C) may be 0.005?a?0.30 atomic (at) %. The additive may further contain nitrogen (N), oxygen (O), boron (B), or a transition metal. The additive may include carbide instead of the carbon (C).

Abstract: Integrated snubber device on a semiconductor basis for wiring an electric network for absorbing electric energy from an electric energy store, of an electric network, including at least two terminals for being connected to the electric network to be wired, an electric resistor structure, and a reactance structure, which are connected between the terminals.

Abstract: The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.

Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed.

Abstract: An electro-optical device includes: a substrate; a plurality of wiring lines which is formed on the substrate; and an IC which is mounted on the substrate so as to be electrically connected to the plurality of wiring lines. At least a pair of wiring lines among the plurality of wiring lines include a first conductive layer formed on the substrate and a second conductive layer formed on at least the first conductive layer. The first conductive layer and the second conductive layer have different resistance values. The first conductive layer of one of the pair of wiring lines has a plurality of first resistors each extending toward the other wiring line, and the second conductive layer of the other wiring line has a second resistor extending toward the one wiring line. The plurality of first resistors is connected to the second resistor.

Abstract: A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage layers may contact first sidewalls of each of the at least one first semiconductor layer. A plurality of second semiconductor layers of a second conductivity type, opposite to the first conductivity type, may be interposed between the first sidewalls of each of the at least one first semiconductor layer and the plurality of first resistance variation storage layers. A plurality of bit line electrodes may be connected to each of the plurality of first resistance variation storage layers.

Abstract: A semiconductor memory device includes a variable resistance element including a first electrode, a current path forming region, and a second electrode. The current path forming region includes a first region made of a variable resistance material whose resistivity changes by applying voltage, and a second region formed by doping a metal element to the variable resistance material such that a resistivity of the second region is higher than that of the first region and is not changed by applying a voltage used to change the resistivity of the first region. The first region is in contact with the first electrode and the second electrode, and extends from one electrode side to the other electrode side. The second region is provided outside the first region in at least part of the current path forming region in direction extending from one electrode side to the other electrode side.

Abstract: A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.

Abstract: An electro-optic device includes a semiconducting layer in which is formed a waveguide, a modulator formed across the waveguide comprising a p-doped region to one side and an n-doped region to the other side of the waveguide, wherein at least one of the doped regions extends from the base of a recess formed in the semiconducting layer. In this way, the doped regions can extend further into the semiconducting layer and further hinder escape of charge carriers without the need to increase the diffusion distance of the dopant and incur an additional thermal burden on the device. In an SOI device, the doped region can extend to the insulating layer. Ideally, both the p and n-doped regions extend from the base of a recess, but this may be unnecessary in some designs. Insulating layers can be used to ensure that dopant extends from the base of the recess only, giving a more clearly defined doped region.

Abstract: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.

Abstract: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and wherein the lower mask and the upper mask comprise current-inhibiting regions.

Abstract: A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer.

Abstract: A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment.

Abstract: A semiconductor device is provided that includes: a base insulating film; a metal thin-film resistor that is provided on the base insulating film; a lower-layer insulating film that is formed under the base insulating film; and a wiring pattern that is formed on the lower-layer insulating film. In this semiconductor device, the base insulating film is formed on the lower-layer insulating film and the wiring pattern, and connecting holes are formed in the base insulating film located on the wiring patterns. The metal thin-film resistor has at least two belt-like portions and a return portion that continues to the belt-like portions. The belt-like portions are located at a distance from the region on the wiring pattern. The return portion connects at least two belt-like portions in a position at a distance from the region on the wiring pattern. The return portion is formed in a connecting hole via the region on the wiring pattern.

Abstract: In some aspects, a microelectronic structure is provided that includes (1) a first conducting layer; (2) a first dielectric layer formed above the first conducting layer and having a feature that exposes a portion of the first conducting layer; (3) a graphitic carbon film disposed on a sidewall of the feature defined by the first dielectric layer and in contact with the first conducting layer at a bottom of the feature; and (4) a second conducting layer disposed above and in contact with the graphitic carbon film. Numerous other aspects are provided.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

Abstract: A method of manufacturing a resistive divider circuit, comprising providing a silicon body (6) having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem (61) supporting a relatively wider silicon platform (62). A silicidation protection (SIPROT) layer (S) is deposited over the body (6) and intermediate taps and then patterned to expose the platform (62). A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.

Abstract: A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the pair of current input/output ports being used for flowing current through the first well along the direction parallel to a substrate surface. A second well of the first conductivity type is disposed between the pair of current input/output ports, the second well being shallower than the first well. A resistor element is provided which facilitates to have a desired resistance value.

Abstract: In a semiconductor device including a semiconductor substrate, and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 ?A/?m2.

Abstract: An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N.

Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A nonvolatile variable resistance memory device may include a lower electrode; a stacked structure including a first Cu compound layer disposed on the lower electrode, and a second Cu compound layer disposed on the first Cu compound layer; and an upper electrode disposed on the second Cu compound layer.

Abstract: According to one embodiment of the present invention, a CBRAM cell includes a solid electrolyte block having at least three solid electrolyte contacting areas, electrodes electrically connected to the solid electrolyte contacting areas, wherein conductive paths are formable, erasable or detectable within the solid electrolyte block by applying voltages between the solid electrolyte contacting areas using the electrodes as voltage suppliers, and wherein the contacting areas are spatially separated from each other such that conductive paths starting from different solid electrolyte contacting areas or ending at different solid electrolyte contacting areas do not overlap each other.

Abstract: Formed on an insulator are an N? type semiconductor layer having a partial isolator formed on its surface and a P? type semiconductor layer having a partial isolator formed on its surface. Source/drain being P+ type semiconductor layers are provided on the semiconductor layer to form a PMOS transistor. Source/drain being N+ type semiconductor layers are provided on the semiconductor layer to form an NMOS transistor. A pn junction formed by the semiconductor layers is provided in a CMOS transistor made up of the transistors. The pn junction is positioned separately from the partial isolators where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction.

Abstract: An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.

Abstract: A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.

Abstract: A programmable resistance memory element comprising a dielectric material between a programmable resistance memory material and a threshold switching material.

Abstract: A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed.

Abstract: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change bridge positioned between and electrically coupling the opposed sides of the electrodes to one another. The phase change bridge has a length, a width and a thickness. The width, the thickness and the length are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the width and the length of the phase change bridge are each less than the minimum photolithographic feature size.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.

Abstract: A semiconductor device includes a fuse circuit, which includes a first conductive region and a second conductive region. The first conductive region has a multi-layered structure, and the second conductive region has a less layered structure than the first conductive region.

Abstract: A semiconductor device equipped with an integrated circuit including a metal thin-film-resistor object is disclosed. The semiconductor device includes a lower layer side insulator film formed on a semiconductor substrate, a metal wiring pattern formed on the lower layer side insulator film, an underground insulator film having a silicon oxide-film that contains at least phosphor, or phosphor and boron in the uppermost layer formed on the lower layer side insulator film and the metal wiring pattern, and a connection hole formed in the underground insulator film on the metal wiring pattern. The metal thin-film-resistor object is formed covering the underground insulator film, and inside of the connection hole, and is electrically connected to the metal wiring pattern in the connection hole.

Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: Provided are a resistance random access memory including a resistance layer having a metal oxide and/or a metal ion dopant, which may be deposited at room temperature and which may have variable resistance characteristics, and a method of manufacturing the same.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: Storage cells for a phase change memory device and phase change memory devices are provided that include a first phase change material pattern and a first high-resist phase change material pattern on the first phase change material pattern. The first high-resist phase change material pattern has a higher resistance than the first phase change material pattern. Methods of fabricating such storage cells and/or memory devices are also provided.

Abstract: Resistor devices are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The conductive materials comprise between about 20% and about 50% of the total weight of the conductive loaded resin-based material. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, or the like.

Abstract: A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.

Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: A semiconductor device is provided that includes: a base insulating film; a metal thin-film resistor that is provided on the base insulating film; a lower-layer insulating film that is formed under the base insulating film; and a wiring pattern that is formed on the lower-layer insulating film. In this semiconductor device, the base insulating film is formed on the lower-layer insulating film and the wiring pattern, and connecting holes are formed in the base insulating film located on the wiring patterns. The metal thin-film resistor has at least two belt-like portions and a return portion that continues to the belt-like portions. The belt-like portions are located at a distance from the region on the wiring pattern. The return portion connects at least two belt-like portions in a position at a distance from the region on the wiring pattern. The return portion is formed in a connecting hole via the region on the wiring pattern.

Abstract: A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi2) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi2. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi2. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSi2 and converts a portion of the C49 TiSi2 to C54 TiSi2. The lower resistance of the C54 TiSi2 decreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.

Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Abstract: A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode includes LaNiO3 and the resistor layer includes doped SrZrO3.

Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.