Abstract: A buffered negative electrode-electrolyte assembly includes: a porous negative electrode comprising a metal, a transition metal nitride, or a combination thereof; a solid-state electrolyte; and a buffer layer between the porous negative electrode and the solid-state electrolyte. The buffer layer comprising a buffer composition according to Formula (1) MmNnZzHhXx. The buffer composition has an electronic conductivity that is less than or equal to 1×10?2 times an electronic conductivity of the solid-state electrolyte, and the buffer composition has an ionic conductivity less than or equal to 1×10?6 times an ionic conductivity of the solid-state electrolyte.

Abstract: The present invention discloses a system comprising: a rechargeable energy storage battery system comprising a monitoring module and an Internet of Things (IoT) based control module; a blockchain network; a processor; and a tangible non-transitory memory; wherein system is operable to receiving periodically by a smart battery management platform, battery related information and one or more environment factors; extracting, processing and analyzing, the battery related information to retrieve a real-time feature of the rechargeable energy storage battery system and the one or more environment factors affecting the battery life and the battery performance by a smart battery management platform; predicting in real-time battery health and life status by the smart battery management platform; rendering using immersive technology, real-time simulated display of situational awareness by a battery management platform; and sending a control signal to the IoT based control module of the rechargeable energy storage batte

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

Abstract: An inductor includes a magnetic body including a magnetic substance; a substrate disposed within the magnetic body; and an internal electrode disposed on at least one of an upper surface and a lower surface of the substrate. The substrate is disposed on an inclined with respect to at least one surface of the magnetic body.

Abstract: Packaged RF front end systems including a hybrid filter and an active circuit in a single package are described. In an example, a package includes an active die comprising an acoustic wave resonator. A package substrate is electrically coupled to the active die. A seal frame surrounds the acoustic wave resonator and is attached to the active die and to the package substrate, the seal frame hermetically sealing the acoustic wave resonator in a cavity between the active die and the package substrate.

Abstract: A chip or integrated circuit includes a layer that includes a first device and a second device. A scribe line is located between the first device and the second device and separates the first device from the second device. An electrically conductive connection traverses the scribe line and is coupled to the first device and the second device, thus connecting the first and second devices.

Abstract: A semiconductor device includes an electrical circuit having a first set of circuit elements, wherein the electrical circuit is in a circuit area on a first side of a substrate, and a first set of conductive pillars over the first side of the substrate. In the semiconductor device, a first conductive rail electrically connects to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail; and a first power cell extending through the substrate, wherein the first power cell includes a first number of power pillars extending through the substrate, wherein each of the first number of power pillars electrically connects to the first conductive rail in parallel.

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

Abstract: A semiconductor apparatus having a silicon substrate layer at least portion of which is doped with dopants of a conductivity type; and at least one insulator layer formed above the silicon substrate layer, wherein the at least one insulator layer and the dopants of the silicon substrate layer have opposite electric charges.

Abstract: Radiofrequency device with adjustable LC circuit comprising an electrical and/or electronic module. The invention relates to a communication device with a radio-frequency chip, said device comprising—an insulating support layer, —an electrical and/or electronic radiofrequency circuit on said insulating layer, said circuit comprising plates of an adjustable capacitor and/or an antenna spiral with adjustable inductance, —at least one element for adjusting a tuning frequency of the radiofrequency circuit. The device is distinguished in that said plates and/or spiral are included in an electrical and/or electronic chip card module, and in that said adjusting element connects an intermediate point of the spiral so as to decrease the available inductance and/or splits or links the plates so as to adjust the capacitance.

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

Abstract: An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.

Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

Abstract: A glass ceramics sintered body includes a glass phase and a ceramics phase dispersed in the glass phase. The ceramics phase includes alumina grains and zirconia grains. The glass phase includes an MO—Al2O3—SiO2—B2O3 based glass, where M is an alkaline earth metal. An area ratio of the alumina grains is 13 to 30%, and an area ratio of the zirconia grains is 0.05 to 6%, on a cross section of the sintered body.

Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of doped polycrystalline silicon layers stacked over one another, and an oxide layer between each adjacent pair of doped polycrystalline silicon layers. A number of the doped polycrystalline silicon layer is ranging from 2 to 6.

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip.

Abstract: An inductor includes: a substrate; a first wiring line located on the substrate; a second wiring line located above the first wiring line and spaced from the first wiring line through an air gap, at least a part of the second wiring line overlapping with at least a part of the first wiring line in plan view; a first supporting post connecting ends of the first and second wiring lines such that a direct current conducts between the first and second wiring lines through the first supporting post; and a second supporting post provided such that the second supporting post overlaps with the second wiring line in plan view, and overlaps with the first wiring line in plan view or is surrounded by the first wiring line in plan view, the second supporting post being insulated from the first wiring line, the second supporting post supporting the second wiring line.

Abstract: A semiconductor device structure and method for forming the same is disclosed. The structure incudes a silicon substrate having at least one trench disposed therein. An electrical and ionic insulating layer is disposed over at least a top surface of the substrate. A plurality of energy storage device layers is formed within the one trench. The plurality of layers includes at least a cathode-based active electrode having a thickness of, for example, at least 100 nm and an internal resistance of, for example, less than 50 Ohms/cm2. The method includes forming at least one trench in a silicon substrate. An electrical and ionic insulating layer(s) is formed and disposed over at least a top surface of the silicon substrate. A plurality of energy storage device layers is formed within the trench. Each layer of the plurality of energy storage device layers is independently processed and integrated into the trench.

Abstract: A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

Abstract: A package includes a first redistribution structure, a die, an encapsulant, a second redistribution structure, and an inductor. The die is disposed on the first redistribution structure. The encapsulant laterally encapsulates the die. The second redistribution structure is over the die and the encapsulant. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure. The second portion is embedded in the encapsulant and is connected to the first and third portions of the inductor. The third portion is embedded in the second redistribution structure.

Abstract: Some features pertain to a substrate, and a first inductor integrated into the substrate. The first inductor includes a plurality of first inductor windings in a first metal layer and a second metal layer. A second inductor is integrated into the substrate. The second inductor includes a first spiral in a third metal layer. The first spiral is located at least partially inside the plurality of first inductor windings, wherein the second inductor is perpendicular to the first inductor.

Abstract: An actuator system can be used to adjust a position of a component in a spatial light modulator. The actuator system has a pair of actuators that are coupled together by a frame that is used to adjust the height of the component relative to the substrate. The frame includes a pair of moment arms that are coupled to the actuators and a pair of connecting arms that are coupled to the moment arms. The connecting arms are then connected together at about the center of the frame, which portion of the frame can be used to raise or lower the plate. The center of the frame can be raised or lowered by a shortening or lengthening of the connecting arms relative to each other.

Abstract: A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

Abstract: The present disclosure provides an array substrate, including: a base substrate, a first metal, a buffer layer, a second metal, a second buffer layer, a third metal. A via is defined in the first buffer layer and the second buffer layer to electrically interconnect the first metal and the third metal, so that the first metal, the second metal and the third metal constitute parallel capacitors.

Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of doped semiconductor layers in a stacked configuration on a dielectric layer. The plurality of doped semiconductor layers each comprise a single crystalline semiconductor material. In the method, a memory stack layer is formed on an uppermost doped semiconductor layer of the plurality of doped semiconductor layers, and the memory stack layer and a plurality of doped semiconductor layers are patterned into a plurality of pillars spaced apart from each other. The patterned plurality of doped semiconductor layers in each pillar of the plurality of pillars are components of a bipolar junction transistor device, and the plurality of pillars are parts of a memory cell array having a cross-point structure.

Abstract: One illustrative IC product disclosed herein includes a first conductive line positioned at a first level within the IC product and a first conductive structure positioned at a second level within the IC product, wherein the second level is lower than the first level. In this illustrative example, the IC product also includes a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance and insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.

Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Abstract: Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode.

Abstract: A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: A memory device includes a memory cell array including a plurality of memory cells and a memory controller to control the plurality of memory cells. The memory cell array has a first fuse region including a plurality of first fuse cells having a same structure as the plurality of memory cells and a second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells. The memory controller has a fuse selection circuit selecting one of the first fuse region and the second fuse region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniplanar (e.g., single layer) passive circuitry and methods of manufacture. The structure includes: passive circuitry comprising plural components each of which are formed on a same wiring level; and interconnects on the same wiring level connecting the plural components of the passive circuitry.

Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.

Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes generating location weight data that includes a plurality of location weights assigned to a plurality of memory devices of the DST execution unit. A first one of the plurality of memory devices and a second one of the plurality of memory devices are selected for reallocation based on the location weight data. The reallocation is executed by removing a data slice from the first one of the plurality of memory devices and storing the data slice in the second one of the plurality of memory devices.

Abstract: Fabrication methods for a 3D multipath inductor, including forming a metal layer to form spiral turns about a center region, the spiral turns including segments that extend length-wise along the turns and having positions that vary from an innermost position and an outermost position relative to the center region; forming a lateral cross-over configured to couple portions of lateral segments in different relative positions from the center region to form lateral segment paths that have a substantially same length for all lateral segment paths in a grouping thereof; forming an additional metal layer to form spiral turns about the center region including corresponding geometry to the first metal layer; and forming a vertical cross-over configured to couple portions of segments on different metal layers to form vertical segment paths that have a substantially same length for all vertical segment paths in a grouping thereof.

Abstract: An inductance device includes a coil provided with at least one electrically conductive turn having a first portion of turn formed on a face of a first substrate, and a second portion of turn. A first end of the first portion is electrically connected to a first end of the second portion by a conductive connection, and the coil has a longitudinal axis, around which the at least one turn is formed, which is perpendicular to a dimension in thickness of the first substrate. The second portion is formed on a face of a second substrate different from the first substrate, with the face of the first substrate facing the face of the second substrate, with the conductive connection extending into an interstitial space located between the face of the first substrate and the face of the second substrate.