Including Resistive Element Patents (Class 257/536)
  • Patent number: 10892261
    Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee, Chia-Hong Jan
  • Patent number: 10867912
    Abstract: Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: December 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jaladhi Mehta, Brian Greene, Daniel J. Dechene, Ahmed Hassan
  • Patent number: 10854813
    Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Mattia Robustelli
  • Patent number: 10840323
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: November 17, 2020
    Assignee: United Semiconductor Japan Co., Ltd.
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Patent number: 10840241
    Abstract: Described examples include a semiconductor device having a resistor. The resistor includes a first terminal and a second terminal. The resistor also includes a first resistive element over an insulating layer over a substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor; and a parallel second resistive element over the insulating layer over the substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor. The resistor may also be coupled in series with another resistor.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sunglyong Kim, Richard Lee Valley, Tobin Daniel Hagan, Michael Ryan Hanschke, Seetharaman Sridhar
  • Patent number: 10840248
    Abstract: A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion. The winding portion is electrically connected with an overlying metal layer through contacts, and the terminal portion includes a polysilicon layer and a metal multilayer from the bottom up.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: November 17, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 10833262
    Abstract: A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: November 10, 2020
    Assignee: 4D-S, LTD.
    Inventors: Seshubabu Desu, Michael Van Buskirk
  • Patent number: 10833067
    Abstract: A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Scott H. Beasor, Zhenyu Hu
  • Patent number: 10790229
    Abstract: A semiconductor memory device according to an embodiment includes a substrate; a plate-like first conductivity layer provided above the substrate and extending parallel to a substrate plane to bestride first and second regions; a plate-like second conductivity layer provided above the first conductivity layer to be separated from the first conductivity layer, an end portion of the first conductivity layer has a protruding staircase shape in the first region, the second conductivity layer extending parallel to the first conductivity layer to bestride the first and second regions; a first contact connected to the first conductivity layer at a side surface or a bottom surface of the first conductivity layer and extending from the first conductivity layer toward the substrate, the first contact being connected at a position where the end portion of the first conductivity layer in the first region protrudes, and a diameter size of a portion of the first contact connected at a side surface or a bottom surface of th
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kenta Yoshinaga, Hideki Inokuma, Hisashi Kato, Masakazu Sawano
  • Patent number: 10748918
    Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10734568
    Abstract: A milliohm resistor is fabricated as a Josephson junction device that contains ferromagnetic or antiferromagnetic material of sufficient thickness to render the device entirely resistive between terminals. The device can have a resistance on the order of milliohms and can be consume a much smaller chip footprint than resistors of the same resistance fabricated using conventional resistive materials. Because the device can be fabricated without modification to processes used to fabricate reciprocal quantum logic (RQL) circuitry, it can easily be incorporated in RQL circuits to mitigate flux trapping or to perform other functions where very small resistances are needed. In particular, the device can burn off circulating currents induced by trapped flux without affecting the transmission of SFQ pulses through RQL circuitry.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 4, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Eric C. Gingrich
  • Patent number: 10720489
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 21, 2020
    Assignee: United Semiconductor Japan Co., Ltd.
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Patent number: 10679121
    Abstract: A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a stack structure disposed between the oxygen-containing layer and the second electrode, the stack structure including a plurality of reactive metal layers alternately arranged with a plurality of oxygen diffusion-retarding layers. The plurality of reactive metal layers are capable of reacting with oxygen ions of the oxygen-containing layer. The plurality of oxygen diffusion-retarding layers interfere with a movement of the oxygen ions from the oxygen-containing layer to the plurality of reactive metal layers.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang-Su Park, Hyung-Dong Lee
  • Patent number: 10651040
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 12, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Patent number: 10615132
    Abstract: An integrated circuit (IC) fabricated on a Silicon-On-Insulator (SOI) wafer, having a plurality of impedance elements cascoded in series, each impedance elements having a specified value. A subset of the impedance elements are arranged to bias a first tub at a specified very high voltage (VHV) multiplied by a first predetermined ratio. A further subset of the impedance elements are arranged to bias a second tub at VHV multiplied by a second predetermined ratio and each of the impedance elements are further arranged to bias a handle and a third surrounding tub at VHV multiplied by a third predetermined ratio. A method for designing an integrated circuit using fully dielectrically isolated processes which function reliably at higher operating voltages than that provided by the conventional processes.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 7, 2020
    Inventors: Alain Comeau, Stephen Swift
  • Patent number: 10553579
    Abstract: The present disclosure relates to a technical field of semiconductors and discloses a semiconductor resistor and a manufacturing method therefor.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 4, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10477196
    Abstract: A multi-display system (e.g., a display including multiple display panels) includes at least first and second displays (e.g., display panels or display layers) arranged substantially parallel to each other in order to display three-dimensional (3D) features to a viewer(s). An optical element(s) such as at least a refractive beam mapper (RBM) is utilized in order to reduce moiré interference.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: November 12, 2019
    Assignee: PURE DEPTH LIMITED
    Inventors: Gareth Paul Bell, Darryl Singh
  • Patent number: 10438941
    Abstract: A semiconductor apparatus including a substrate, an electrostatic discharge protection device, a resistor device, and a first metal layer is provided. The substrate defines a pad area and includes a first area and a second area. The first area has a recess, the second area is disposed in the recess, and the pad area is partially overlapped with the first area and the second area. The electrostatic discharge protection device is disposed in the first area of the substrate. The resistor device is disposed in the second area of the substrate. The first metal layer is disposed above and electrically connected to the electrostatic discharge protection device and the resistor device.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 8, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Yi-Yun Tsai, Chih-Hung Chen, Chin-Fu Chen
  • Patent number: 10290581
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 10256523
    Abstract: A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace with a first edge substantially parallel to a second edge and substantially equal in length to the second edge. The first trace includes a third edge substantially parallel to a fourth edge. The fourth edge is divided into three segments. The outer segments are a first distance from the third edge. The middle segment is a second distance from the third edge. Further, the coupler includes a second trace, which includes a first edge substantially parallel to a second edge and substantially equal in length to the second edge. The second trace includes a third edge substantially parallel to a fourth edge. The fourth edge is divided into three segments. The outer segments are a first distance from the third edge. The middle segment is a second distance from the third edge.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 9, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yang Li, Xuanang Zhu, Dinhphuoc Vu Hoang, Guohao Zhang, Russ Alan Reisner, Dmitri Prikhodko, Jiunn-Sheng Guo, Bradley David Scoles, David Viveiros, Jr.
  • Patent number: 10249769
    Abstract: An object of the disclosure is to take a CMOS varactor structure (NMOS in N-well or PMOS in P-well) and turn it in to a three terminal on-chip tuneable diffusion resistor. The diffusion resistor can be made with an n+ diffusion inside the p-substrate, or with a p+ diffusion inside an N-well that lies within the p-substrate. The resistor can be implemented in any existing CMOS or BICMOS silicon technology, without using additional masks. The resistor can be also implemented in a technology with FINFETs.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 2, 2019
    Assignee: Dialog Semiconductor, Inc.
    Inventor: Douglas Daley
  • Patent number: 10249379
    Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one MOS. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.
    Type: Grant
    Filed: September 13, 2014
    Date of Patent: April 2, 2019
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 10236289
    Abstract: A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate, forming a dielectric fill layer on the plurality of vertical fins, forming at least two dummy gate structures on the plurality of vertical fins, forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins, forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure, removing the replaceable resistor structure to form a trench, and forming a resistor structure in the trench.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10229966
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Patent number: 10191084
    Abstract: Embodiments are directed to techniques for providing a user-selected target resistance across a set of output terminals of a resistance-generating apparatus.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 29, 2019
    Assignee: IET Labs, Inc.
    Inventors: Benjamin Salim Sheena, Robert Michael Brown, Trung Q. Mai, David Sheena
  • Patent number: 10192870
    Abstract: An HVNMOS having a source follower configuration is disposed in an n? diffusion region that forms an HVJT. The lateral HVNMOS includes a p-type back gate region, source contact region, n+drain region, and gate electrode. The p-type back gate region and source contact region contact a p? isolation region and are separated from p+ common potential regions inside the p? isolation region. The source contact region is electrically connected to the COM electrode pad through a source follower resistor RSF. The p+ common potential regions are electrically connected to the p-type back gate region and source contact region of the HVNMOS through diffusion resistors provided between the p-type back gate region/source contact region of the HVNMOS and the p+ common potential region.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 29, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10157258
    Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 9985018
    Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 29, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
  • Patent number: 9972386
    Abstract: The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 15, 2018
    Assignee: IMEC
    Inventors: Pieter Blomme, Dirk Wouters
  • Patent number: 9972613
    Abstract: A semiconductor device includes a transistor having a plurality of transistor cells in a semiconductor body. Each transistor cell includes a control terminal and first and second load terminals. The transistor further includes a phase change material exhibiting a solid-solid phase change at a phase transition temperature Tc between 150° C. and 400° C. The control terminals of the plurality of transistor cells are electrically connected to one another.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Guenther Ruhl, Hans-Joerg Timme
  • Patent number: 9941209
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 9905514
    Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9847402
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second BBM layer on the first region and the second region.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 19, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Shih-Hung Tsai, Jyh-Shyang Jenq
  • Patent number: 9823279
    Abstract: A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: November 21, 2017
    Assignee: Micrel, Inc.
    Inventor: Cameron Jackson
  • Patent number: 9806020
    Abstract: A semiconductor device that includes a first wiring, a second wiring, and a first number of first resistance elements that are connected in parallel between the first wiring and the second wiring, and each of which has a negative first temperature coefficient. The semiconductor device further includes a second number of second resistance elements that are connected in parallel to the first resistance elements, each of which has a positive second temperature coefficient, the second temperature coefficient having an absolute value larger than an absolute value of the first temperature coefficient. The second number is smaller than the first number.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiaki Ishii
  • Patent number: 9793002
    Abstract: In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 17, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jefferson W. Hall
  • Patent number: 9786738
    Abstract: A semiconductor device including a well resistance element of high accuracy and high withstand voltage and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a well region, an input terminal, an output terminal, a separation insulating film, and an active region. The input terminal and the output terminal are electrically coupled to the well region. The separation insulating film is arranged to be in contact with the upper surface of the well region in an intermediate region between the input terminal and the output terminal. The active region is arranged to be in contact with the upper surface of the well region. The separation insulating film and the active region in the intermediate region have an elongated shape in plan view. In the intermediate region, a plurality of separation insulating films and a plurality of active regions are alternately and repeatedly arranged.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kiyoshi Hayashi
  • Patent number: 9773730
    Abstract: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 9761692
    Abstract: A method for fabricating semiconductor device preferably forms a stop layer composed of amorphous silicon between a first BM layer and a second BBM layer of one of the gate structure during the fabrication of a device having multi-VT gate structures. By doing so, it would be desirable to use the stop layer as a protecting layer during the etching process of work function metal layers and the second BBM layer so that the first BBM layer could be protected from etchant such as SC1 and the overall thickness of the first BBM layer and the performance of the device could be maintained.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Shih-Hung Tsai, Jyh-Shyang Jenq
  • Patent number: 9754898
    Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: September 5, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Mu-Hsuan Chan, Wan-Ting Chen, Chun-Tang Lin, Yi-Che Lai
  • Patent number: 9704624
    Abstract: An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the semiconductor substrate and having a first conductivity type, a first resistive region in the well having an L-shape and a second conductivity type, and a tuning element associated with the first resistive region. The IC may also include a resistance compensation circuit on the semiconductor substrate. The resistance compensation circuit may be configured to measure an initial resistance of the first resistive region, and generate a voltage at the tuning element to tune an operating resistance of the first resistive region based upon the measured initial resistance.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 11, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Alessandro Motta
  • Patent number: 9679894
    Abstract: A semiconductor variable resistance device includes: a substrate; a gate formed on the substrate, the substrate further including a first trench the first trench formed outside a side of the gate; first and second doped regions, formed in the substrate, the first and second doped regions formed on two sides of the gate, the first trench formed between the gate and the first doped region; and first and second lightly-doped drain (LDD) regions, formed in the substrate. The first LDD region is formed between the first trench and the first doped region. The second LDD region is formed between the gate and the second doped region. The first and second doped regions form a source and a drain, respectively. The first trench is deeper than the first and the second lightly-doped drain regions.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Hsiang Shu
  • Patent number: 9666797
    Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 30, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Yu-Yu Lin
  • Patent number: 9640529
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seung Song, Hwi-Chan Jun
  • Patent number: 9620711
    Abstract: An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both includes a plurality of sub-electrodes and a plurality of second material layers that are alternately arranged in the first direction, and wherein each of the second material layers has a thickness that is sufficiently small to enable the second material layers to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: April 11, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 9583534
    Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choong-jae Lee, Hong-kook Min, Bo-young Seo, Aliaksei Ivaniukovich, Yong-kyu Lee
  • Patent number: 9536878
    Abstract: Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: January 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Youn Kim
  • Patent number: 9502332
    Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Heun Lim, Hyo-Jung Kim, Ji-Woon Im, Kyung-Hyun Kim
  • Patent number: 9502651
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes an odd-numbered layer structure disposed over a substrate and including a plurality of first lines which extend in a first direction; an even-numbered layer structure disposed over the substrate and including a plurality of second lines which extend in a second direction crossing the first direction; and resistance variable layers interposed between the first lines, between the second lines, and between the first lines and the second lines, wherein the odd-numbered layer structure and the even-numbered layer structure are alternately stacked over the substrate.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hae-Chan Park
  • Patent number: 9496036
    Abstract: A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided to a bit line of the resistive memory cell. A first voltage is provided to a word line of the resistive memory cell, and a second voltage is provided to a source line of the resistive memory cell, wherein the first voltage is not increased while the second voltage is progressively increased. Thus, when the writing method for the resistive memory cell is performed, the voltage of the word line is not increased while the voltage of the source line is progressively increased, so as to expand voltage window for reset operation. And, the chance for occurring the complementary switching manifestation of the resistive memory cell due to excessive input voltages is reduced.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 15, 2016
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Pei-Hsiang Liao