Abstract: Buried N.sup.+ layers are formed in the surface of a substrate, on which first and second epitaxial layers are successively deposited. A vertical PNP transistor formed in the surface of the first epitaxial layer has a buried collector layer, a collector lead region, and a base contact region. The buried collector layer, the collector lead region, and the base contact region provide a buried anode layer, an anode lead region, and a cathode contact region, respectively, of a diode. The vertical PNP transistor and the diode are surrounded by N.sup.+ lead regions and the buried N.sup.+ layers.

Abstract: A semiconductor device relating to an improvement in an L-PNP transistor in particular is such that, on a semiconductor substrate of a first conductivity type, a base region is formed which has a second conductivity type opposite in conductivity to the first conductivity type. A first conductivity type impurity ion is implanted into the base region to provide at least two first diffusion layers there. The first diffusion layers have a first impurity concentration level and are formed as collector and emitter regions. A polysilicon layer is formed on the first diffusion layer in base region in an overhanging relation to the first diffusion layer and contains the first conductivity type impurity. A second diffusion layer is formed around the collector region and around the emitter region by diffusing an impurity from the polysilicon layer. The collector and emitter regions each are formed as a two-layered structure with their first and second diffusion layers.

Abstract: In one embodiment, an integrated driver circuit configuration for an inductive load element includes a highly doped substrate of p-conductivity, an epitaxial layer having the same conductivity type as the substrate and being applied on the substrate, an output terminal for connecting the inductive load element, a plurality of insulated wells being disposed in the epitaxial layer and having a well associated with the output terminal, and an n-doped region laterally surrounding the well associated with the output terminal. In another embodiment, the integrated driver circuit configuration for the inductive load element includes a highly doped substrate of p-conductivity, an epitaxial layer applied on the substrate, a plurality of insulated wells having an n-doped well, an n-doped region laterally surrounding the n-doped well, and an output terminal for connecting the inductive load element.

Abstract: An n.sup.- -type silicon active layer having a thickness of 6 .mu.m or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the active layer. The two devices are insulated and isolated from each other through a trench. The bipolar transistor has an n-type well layer formed in the surface of the active layer. A p-type well layer is formed in the surface of the n-type well layer. The thickness of the n-type well layer under the p-type well layer is set to be 1 .mu.m or more. A first n.sup.+ -type diffusion layer is formed in the surface of the n-type well layer. A p.sup.+ -type diffusion layer and a second n.sup.+ -type diffusion layer are formed in the surface of the p-type well layer. The n-type well layer and the first n.sup.+ -type diffusion layer serve as a collector region. The p-type well layer and the p.sup.+ -type diffusion layer serve as a base region. The second n.sup.

Abstract: A guard ring with the same conductivity as a device pocket surrounds the pocket and a pocket isolation ring to establish a parasitic transistor that conducts current between the guard ring and the pocket when the pocket voltage is driven sufficiently below the substrate voltage. The guard ring is connected to a voltage supply for the circuit which, together with its shorter current path, allows the parasitic transistor to harmlessly divert current away from unwanted inter-pocket parasitic transistors.

Abstract: In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation of the lateral PNP bipolar transistor and drop of yield in production thereof being prevented and a high performance (low cost) Bi-CMOS LSI being realized.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A transversal bipolar transistor is structured to have a single crystal semiconductor film provided on a single crystal semiconductor region which is provided on a semiconductor substrate. The semiconductor substrate is of a first conductivity type, and the single crystal semiconductor region is of a second conductivity type which is opposite to the first conductivity type. The single crystal semiconductor film is divided in the transversal direction into a central portion of the second conductivity type for a base region and left and right portions of the first conductivity type for emitter and collector regions. The transversal bipolar transistor may be integrated with a vertical bipolar transistor commonly on the semiconductor substrate.

Abstract: A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an injector of an IIL are integrated on a P-type silicon substrate. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. Since both the superhigh speed vertical NPN transistor having a reverse direction structure and the superhigh speed vertical NPN transistor are self-aligned, the superhigh speed vertical NPN transistor and the IIL device may be integrated on the same chip. In addition, the intrinsic base layer of the vertical NPN transistor having a reverse direction structure is deeper in junction than the base layer of the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type.

Abstract: A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42).

Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

Abstract: The base region of the power stage and the horizontal isolation region of the integrated control circuit or collector region of a transistor of an integrated circuit consist of portions of an epitaxial layer with a first conductivity type grown in sequence on an underlying epitaxial layer with a second conductivity type opposite the first.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon layer into the N- base region. The base region thus remains N- and the resulting transistor has improved breakdown voltage characteristics while retaining the speed advantages of polysilicon contact layers. The lateral pnp transistor is manufactured by a method which requires minimal deviation from other methods used to manufacture lateral pnp transistors.

Abstract: A lateral transistor includes a semiconductor substrate, a buried layer formed on the semiconductor substrate, an epitaxial layer formed on the buried layer in such a manner that the epitaxial layer is a p-type or n-type (first conductivity-type), a diffusion zone having a second conductivity-type opposite to the first conductivity-type and including an emitter zone and collector zone formed on the epitaxial layer, and a base zone. The base zone includes an epitaxial layer interposed between the emitter zone and the collector zone. The collector zone is formed within a well zone in such a manner that the well zone has the same type conductivity as the collector zone and a lower concentration than the collector zone.

Abstract: In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for the PNP transistor is self-aligned with the base region of the NPN transistor. All the defined regions are then doped to achieve a desired base region concentration. A next masking step forms a layer of resist over the base region, and the remainder of the previous masking pattern is retained to define the emitter and collector regions of the PNP transistor. P-type dopants are then implanted in the previously defined emitter and collector regions to form the heavily doped P++ emitter and collector regions of the PNP transistor. Thus, the P++ emitter and collector regions of the PNP transistor will be self-aligned with the P-type base region of the NPN transistor.

Abstract: An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31).The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Abstract: A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.