Abstract: A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.

Abstract: In one embodiment, an apparatus includes a first transistor where the base of the first transistor is coupled to an input node. A second transistor is provided where the emitter of the first transistor is coupled to the base of the second transistor and the emitter of the second transistor is coupled to an output node. A third transistor is provided where the base of the third transistor is coupled to the input node. A fourth transistor is provided where the emitter of the third transistor is coupled to the base of the fourth transistor and the emitter of the fourth transistor is coupled to the output node and the base of the second transistor is coupled to the base of the fourth transistor. The base of the second transistor is coupled to the base of the fourth transistor through a shorting link.

Abstract: Semiconductor devices and methods are disclosed wherein a switching element or a current path is coupled to a substrate, and wherein a further element is coupled to said substrate and a control input of said switching element or said current path. Accordingly, in at least one embodiment, a semiconductor device comprises a substrate and a switching element with a control input coupled to the substrate. The semiconductor device includes a compensation element having a control input and an output. The control input of the compensation element is coupled to the substrate and the output of the compensation element is coupled to the control input of the switching element.

Abstract: Multiple emitter-base regions arc formed on a single contiguous collector. The multiple emitter-base regions are cascoded such that the base of one emitter-base region is directly wired to the emitter of an adjacent emitter-base region. An electrostatic discharge (ESD) protection unit, comprising a single collector and multiple emitter-base regions, provides protection against an ESD event of one type, i.e., a positive or negative voltage surge. The inventive ESD protection structure comprises a parallel connection of two ESD protection units, each providing a discharge path for electrical charges of opposite types, and provides ESD protection for both types of voltage swing in the circuit.

Abstract: Semiconductor devices and methods are disclosed wherein a switching element or a current path is coupled to a substrate, and wherein a further element is coupled to said substrate and a control input of said switching element or said current path. Accordingly, in at least one embodiment, a semiconductor device comprises a substrate and a switching element with a control input coupled to the substrate. The semiconductor device includes a compensation element having a control input and an output. The control input of the compensation element is coupled to the substrate and the output of the compensation element is coupled to the control input of the switching element.

Abstract: A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to the glass substrate. The thin semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. An ultra-thin silicon layer bonded to a glass substrate, selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate, provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: The present invention is a modified darlington phototransistor wherein a phototransistor is coupled to a Bipolar Junction Transistor (BJT). This design provides a high sensitivity and a fast response and effectively increases the gain of the photocurrent. This circuit is particularly will suited for the readily available CMOS and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) processes prevalent today.

Abstract: The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.

Abstract: There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention provides the trimming pattern for use in trimming of a semiconductor integrated circuit, comprising two pads to which a voltage is applied, a thin line part interconnecting the two pads, and two connecting parts disposed away from each side of the thin line part, and connected to an adjustment circuit and the semiconductor integrated circuit, respectively. With the invention, trimming is executed by a method of turning the adjustment circuit connected to the connecting parts into the ON state by connecting fused metal of the thin line part to the connecting parts. In this case, since the fused metal can be caused to come into contact with the connecting parts nearby with greater ease than fusion cutting of the thin line part, trimming can be implemented with ease and in shorter time.

Abstract: A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

Abstract: A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a collector contact region are formed in surface portions of the lightly doped n-type single crystal silicon layer, and the single crystal silicon layer is not affected by the heat during the growth of the thick field oxide layer, and has a flat zone constant in dopant concentration regardless of the thickness thereof.

Abstract: A high gain photodetector requiring a substantially silicon area than prior art photodetectors having the same gain. The photodetector includes a light converter for converting a light signal to a current; and a first vertical transistor. The first vertical transistor includes a first well in a semiconductor substrate, the first well including a diffusion region, the semiconductor substrate and the diffusion having a first type of doping and the first well having a second type of doping. The first type of doping is either P-type or N-type, and the second type of doping is the other of the P-type or N-type doping. The light converter is connected to the first well so as to forward bias the vertical transistor thereby causing a current to flow between the diffusion region in the first well and the substrate. Additional amplification of the photocurrent from the light converter can be provided by including a second vertical transistor.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q.sub.1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q.sub.1, a second optional transistor Q.sub.2, a first inductor L.sub.E in the emitter (source) of Q.sub.1, and a second inductor L.sub.B in the base (gate) of Q1. The emitter length l.sub.E1, or correspondingly the gate width w.sub.g, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z.sub.0, which is typically 50.OMEGA.. The first inductor L.sub.E, provides matching of the real part of the input impedance and the second inductor L.sub.B cancels out the noise reactance and input impedance reactance of the structure.

Abstract: In a semiconductor protection circuit, a current fuse and a transistor are connected in series between a power supply terminal and a ground. A bias circuit is provided between the base and the emitter of the transistor. The bias circuit applies between the base and the emitter of the transistor a constant bias voltage that is lower than a normal environment temperature forward voltage of a p-n junction between the transistor's base and emitter. When a load connected to the other terminal of the current fuse is overheated, the forward voltage of the p-n junction drops, and the transistor is turned on.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A bipolar integrated circuit with N-type wells (2) formed in a P-type substrate (1) includes in first wells, first transistors (EBC), the well of which constitutes the collector. P-type base region (7a) is formed in the first well with an N+ emitter region (8) formed in the base region. In at least a second well forming a collector, a composite second transistor (E'B'C') is constituted by an elemental third transistor (E.sub.1 B.sub.1 C') comprising regions of the same doping level as the first transistor and an elemental fourth transistor (E.sub.2 B.sub.2 C') having a base region (11) with a high doping level with respect to that of the bases of the first transistor. Emitter regions (8b, 12) of the elemental transistors are of the same doping level as that of the first transistors. The emitters and bases of the third and fourth elementary transistors are interconnected and constitute the emitter and the base of the composite second transistor.

Abstract: An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.

Abstract: A Darlington transistor having improved comprehensive electric characteristic and a bipolar transistor having improved high voltage characteristic are obtained. A collector resistivity .rho.N.sup.- (F) of a collector high resistivity layer (11) in a front stage side transistor chip (TF) is set to 80 5/8cm and its collector film thickness tN.sup.- (F) is set to 120 .mu.m, and a collector resistivity .rho.N.sup.- (R) of a collector high resistivity layer (13) in a rear stage side transistor chip (TR) is set to 45 .OMEGA.cm and its collector film thickness tN.sup.- (R) is set to 160 .mu.m. Since .rho.N.sup.- (F)>.rho.N.sup.- (R) and tN.sup.- (F)<tN.sup.- (R) are satisfied, a Darlington transistor having a good comprehensive electric characteristic can be obtained, and also, since .rho.N.sup.- (R)/tN.sup.- (R)<0.6 is satisfied, a bipolar transistor having a good high voltage characteristic can be obtained (FIG. 8).