Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.

Abstract: A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin therebetween. The fin is hydrogen annealed. A dielectric material is formed in the trenches. The dielectric material in the trenches is recessed.

Abstract: Provided is a detector circuit that includes: a first transistor that has an alternating current signal input to a base thereof, and that outputs a first detection signal that depends on the alternating current signal from a collector thereof; a second transistor that has the first detection signal input to a base thereof, and that outputs a second detection signal that depends on the first detection signal from a collector thereof; and an alternating current signal path along which the alternating current signal is supplied to the base of the second transistor.

Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region.

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

Abstract: Two or more pads and are connected to a gate region, so that a pad for applying a gate voltage can be selected. In the case where, for example, the peripheral region is likely to overheat, a turn-on voltage is applied to the first pad to turn on the peripheral region later than the central region, and a turn-off voltage is applied to the second pad to turn off the peripheral region earlier than the central region. The problem that the peripheral region is likely to overheat can be addressed. In the case where the flow of an excess current raises the temperature, the turn-off voltage is applied to the second pad. The problem that the temperature is likely to rise in the peripheral region when an excess current flows can be addressed.

Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.

Abstract: An electronic oscillator of a circuit arrangement for creating microwave oscillations with two transistors as amplifier elements and with a resonator (4), wherein the resonator has two emitter impedance networks, the base impedance network and/or an emitter impedance network or both emitter impedance networks can be put out of tune and the transistors each have a parasitic base collector capacitance. The repercussion of the load on the electronic oscillator (“load-pulling”) is greatly reduced so as to be eliminated as much as possible, in that a compensation capacitance is switched between the collector of the first transistor and the base of the second transistor as well as between the collector of the second transistor and the base of the first transistor, and the compensation capacitances are implemented by reverse-biased pn-junctions.

Abstract: A semiconductor device includes an IGBT cell including a second-type doped drift zone, and a desaturation semiconductor structure for desaturating a charge carrier concentration in the IGBT cell. The desaturation structure includes a first-type doped region forming a pn-junction with the drift zone, and two portions of a trench or two trenches arranged in the first-type doped region and beside the IGBT cell in a lateral direction. Each of the two trench portions or each of the two trenches has a wide part below a narrow part. The wide parts confine a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction. The narrow parts confine a first-type doped mesa region of the first-type doped region at least in the lateral direction. The desaturation channel region has a width smaller than the mesa region in the lateral direction, and adjoins the mesa region.

Abstract: Disclosed embodiments include a direct current to direct current (DC-DC) converter including one or more charge pumps and configured to receive an input voltage and a first clock signal and a second clock signal. The first clock signal and second clock signal may be non-overlapping, and each may alternate between a ground voltage and a first voltage. The DC-DC converter may be configured to produce an output voltage over the clock cycle that has a negative polarity with a magnitude substantially equal to a sum of magnitudes of the input voltage and an integer multiple of the first voltage, the integer multiple being equal to a number of the one or more charge pumps in the DC-DC converter.

Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.

Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

Abstract: Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.

Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region.

Abstract: Structures and methods of making a heterojunction bipolar transistor (HBT) device that include: an n-type collector region disposed within a crystalline silicon layer; a p-type intrinsic base comprising a boron-doped silicon germanium crystal that is disposed on a top surface of an underlying crystalline Si layer, which is bounded by shallow trench isolators (STIs), and that forms angled facets on interfaces of the underlying crystalline Si layer with the shallow trench isolators (STIs); a Ge-rich, crystalline silicon germanium layer that is disposed on the angled facets and not on a top surface of the p-type intrinsic base; and an n-type crystalline emitter disposed on a top surface and not on the angled lateral facets of the p-type intrinsic base.

Abstract: A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.

Abstract: The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base.

Abstract: A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

Abstract: An electrostatic discharge (ESD) protection structure comprises a bipolar PNP transistor having an emitter formed by a first high voltage P type implanted region disposed underneath a first P+ region and a collector formed by a second high voltage P type implanted region disposed underneath a second P+ region. The ESD protection structure can have an adjustable threshold voltage by controlling the distance between the first high voltage P type implanted region and the second high voltage P type implanted region. Based upon a basic ESD protection structure, the ESD protection device can provide a reliable ESD protection for semiconductor devices having different voltage ratings.

Abstract: An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.

Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.

Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and t

Abstract: The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base.

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

Abstract: A power module includes a first semiconductor device having a collector terminal and an emitter terminal which extend outwardly from a molded resin, wherein at least one of the collector and emitter terminals is a bilaterally extending terminal extending outwardly from two opposite surfaces of the molded resin, and a second semiconductor device having the same construction as the first semiconductor device. The bilaterally extending terminal of the first semiconductor device is connected to a bilaterally extending terminal of the second semiconductor device.

Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.

Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.

Abstract: An internal matching transistor comprises: a conductive base material including a groove, a first region, and a second region which is located opposite to the first region across the groove; a transistor bonded onto the first region of the base material; an internal matching circuit bonded onto the second region of the base material; a wire connecting the transistor to the internal matching circuit across above the groove; and a conductive or non-conductive material located between the wire and the groove, wherein capacitance between the wire and the base material is adjusted by the material.

Abstract: Disclosed is a device structure using an inverse-mode cascoded Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) beneficial in applications requiring radiation hardened circuitry. The device comprises a forward-mode common-emitter HBT cascoded with a common-base inverse-mode HBT, sharing a common sub-collector. An exemplary device was measured to have over 20 dB of current gain, and over 30 dB of power gain at 10 GHz, thus demonstrating the use of these circuits for high-frequency circuit applications. In addition, the radiation response and voltage limits were characterized and showed to have negligible performance effects in typical operating conditions. Due to the unique topology, the disclosed device has the benefit of being a more compact cascode design and the additional benefit of providing significantly improved radiation tolerance.

Abstract: An electrostatic discharge (ESD) protection structure comprises a bipolar PNP transistor having an emitter formed by a first high voltage P type implanted region disposed underneath a first P+ region and a collector formed by a second high voltage P type implanted region disposed underneath a second P+ region. The ESD protection structure can have an adjustable threshold voltage by controlling the distance between the first high voltage P type implanted region and the second high voltage P type implanted region. Based upon a basic ESD protection structure, the ESD protection device can provide a reliable ESD protection for semiconductor devices having different voltage ratings.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: An IGBT module is provided. The IGBT module has at least a first individual IGBT with a first softness during switching-off the IGBT module, and at least a second individual IGBT connected in parallel to the at least one first IGBT. The at least one second individual IGBT has a second softness during switching-off the IGBT module which is different than the first softness. Further a circuit and an electronic power device having two individual IGBTs, which are connected in parallel, are provided.

Abstract: A bipolar transistor for semiconductor device has a collector region having a first conductivity type disposed on a surface of a semiconductor substrate having the first conductivity type. A base region having a second conductivity type is disposed in the collector region. An emitter region having the first conductivity type is disposed in the base region. A high concentration first conductivity type region for a collector electrode is disposed in the collector region. A high concentration second conductivity type region for a base electrode is disposed in the base region. The high concentration first conductivity type region for a collector electrode and the high concentration second conductivity type region for a base electrode contact directly with each other so that the collector region and the base region have a same potential.