Abstract: An image forming apparatus includes a plurality of light-emitting element array chips including a light-emitting element array and a transfer element array, and a control driver applying a signal to the plurality of light-emitting element array chips. The control driver includes a check terminal that measures signals output from the plurality of light-emitting element array chips, and the control driver determines whether any of the plurality of light-emitting element array chips are defective by analyzing the signals measured at the check terminal.

Abstract: Structures and methods of making a heterojunction bipolar transistor (HBT) device that include: an n-type collector region disposed within a crystalline silicon layer; a p-type intrinsic base comprising a boron-doped silicon germanium crystal that is disposed on a top surface of an underlying crystalline Si layer, which is bounded by shallow trench isolators (STIs), and that forms angled facets on interfaces of the underlying crystalline Si layer with the shallow trench isolators (STIs); a Ge-rich, crystalline silicon germanium layer that is disposed on the angled facets and not on a top surface of the p-type intrinsic base; and an n-type crystalline emitter disposed on a top surface and not on the angled lateral facets of the p-type intrinsic base.

Abstract: An object is to provide a manufacturing method of an SOI substrate in which a plurality of single crystal semiconductor layers uniform in quality is bonded to a substrate having a larger area than a single crystal silicon substrate. At the time of a heat treatment, uniform heat distribution in single crystal semiconductor substrates is realized by using a tray which has depression portions each with a large depth and is not in contact with the single crystal semiconductor substrate bonded to a base substrate as a tray for supporting the base substrate and holding the single crystal semiconductor substrates. Further, by providing a supporting portion for the base substrate between the depression portions of the tray, a contact area between the tray and the base substrate is reduced.

Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

Abstract: A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.

Abstract: Semiconductor devices and methods are disclosed wherein a switching element or a current path is coupled to a substrate, and wherein a further element is coupled to said substrate and a control input of said switching element or said current path. Accordingly, in at least one embodiment, a semiconductor device comprises a substrate and a switching element with a control input coupled to the substrate. The semiconductor device includes a compensation element having a control input and an output. The control input of the compensation element is coupled to the substrate and the output of the compensation element is coupled to the control input of the switching element.

Abstract: A semiconductor device includes a pair of transistors formed in a first conductive type semiconductor substrate. Each of the transistors contains a collector region of a second conductive type, opposite to the first conductive type, formed in the semiconductor substrate, a base region of the first conductive type formed in the collector region, and an emitter region of the second conductive type formed in the base region, the collector region of one transistor of the pair of transistors being separated from that of the other transistor. The semiconductor device further includes a first region of the first conductive type formed between the collector regions of the pair of transistors, and a buried layer of the second conductive type formed in the semiconductor substrate under the collector region of one transistor of the pair of transistors to connect the collector regions of the transistors therethrough.

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction.

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: The present invention is a modified darlington phototransistor wherein a phototransistor is coupled to a Bipolar Junction Transistor (BJT). This design provides a high sensitivity and a fast response and effectively increases the gain of the photocurrent. This circuit is particularly will suited for the readily available CMOS and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) processes prevalent today.

Abstract: The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.

Abstract: There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention provides the trimming pattern for use in trimming of a semiconductor integrated circuit, comprising two pads to which a voltage is applied, a thin line part interconnecting the two pads, and two connecting parts disposed away from each side of the thin line part, and connected to an adjustment circuit and the semiconductor integrated circuit, respectively. With the invention, trimming is executed by a method of turning the adjustment circuit connected to the connecting parts into the ON state by connecting fused metal of the thin line part to the connecting parts. In this case, since the fused metal can be caused to come into contact with the connecting parts nearby with greater ease than fusion cutting of the thin line part, trimming can be implemented with ease and in shorter time.

Abstract: The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.

Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: This disclosure describes a structure for transistor devices formed from compound semiconductor materials; and particularly for heterojuntion bipolar transistors (HBTs); and more particularly for the collector structure of a double HBT (DHBT). The invention enables high output power at high frequency operation, of high frequency operation at high output power.

Abstract: A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

Abstract: This disclosure describes a structure for transistor devices formed from compound semiconductor materials; and particularly for heterojunction bipolar transistors (HBTs); and more particularly for the collector structure of a double HBT (DHBT). The invention enables high output power at high frequency operation, or high frequency operation at high output power.

Abstract: The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.

Abstract: A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: The invention relates to a bipolar ESD protection comprising a protection transistor with a short-circuited base emitter (18, 19). Due to the snap-back effect, the transistor can switch from the normal high-ohmic condition to a low-ohmic condition in the case of ESD. To improve the protection performance, the protection structure is provided with a trigger element comprising a second transistor (26, 27, 28) with a lower breakdown voltage. The base (26) and the emitter (28) of the second transistor are connected to the base of the protection transistor. To increase the current carrying capability of the protection device, the trigger transistor is designed so as to be a vertical transistor.

Abstract: An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.

Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.

Abstract: A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal.

Abstract: The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-type Si substrate between a second p-type base layer selectively formed on the surface of the Si substrate and a channel stop layer formed to surround the second p-type base layer at a predetermined interval. The dangling bond density of the semiconductive film is set at 1.25.times.1018 cm.sup.-3. With this structure, the discrete level in the band gap approach a continuum, and the time required to populate the trapping level in the semiconductive film with carriers is shortened.

Abstract: A semiconductor temperature sensor comprises independent current sources and bipolar transistors connected to form a Darlington circuit. The bipolar transistors have electrodes each connected to one of the current sources. An output voltage of the semiconductor temperature sensor is adjusted by trimming a current value of at least one of the current sources.

Abstract: A high gain photodetector requiring a substantially silicon area than prior art photodetectors having the same gain. The photodetector includes a light converter for converting a light signal to a current; and a first vertical transistor. The first vertical transistor includes a first well in a semiconductor substrate, the first well including a diffusion region, the semiconductor substrate and the diffusion having a first type of doping and the first well having a second type of doping. The first type of doping is either P-type or N-type, and the second type of doping is the other of the P-type or N-type doping. The light converter is connected to the first well so as to forward bias the vertical transistor thereby causing a current to flow between the diffusion region in the first well and the substrate. Additional amplification of the photocurrent from the light converter can be provided by including a second vertical transistor.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q.sub.1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q.sub.1, a second optional transistor Q.sub.2, a first inductor L.sub.E in the emitter (source) of Q.sub.1, and a second inductor L.sub.B in the base (gate) of Q1. The emitter length l.sub.E1, or correspondingly the gate width w.sub.g, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z.sub.0, which is typically 50.OMEGA.. The first inductor L.sub.E, provides matching of the real part of the input impedance and the second inductor L.sub.B cancels out the noise reactance and input impedance reactance of the structure.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A semiconductor device includes on a semiconductor substrate an output transistor which is composed of a collector region, a first base region and a first emitter region, and a temperature detection transistor composed of the collector region, a second base region and a second emitter region. The output transistor is provided at a center of the collector region of the semiconductor substrate. A vacant region is formed on a center of the output transistor, and the temperature detection transistor is provided in the vacant region.

Abstract: There is disclosed a layout of a high voltage Darlington pair in which a circular field plate is utilized for both high voltage transistors in order to reduce the layout area. In this layout, both transistors of a Darlington pair are circular transistors and they both have a common center. This enables both high voltage transistors to share one field plate ring and one collector ring.

Abstract: An integrated structure is described, that comprises a vertical bipolar transistor and a vertical MOSFET transistor, where, in order to reduce the series resistance of the MOSFET transistor, the collector region of the bipolar transistor and the drain region of the MOSFET transistor are both parts of a common zone and are contiguous each other, so that the high charge injection in the collector region when the bipolar transistor is in conduction state, causes a simultaneous increase in the conductivity of the drain region of the MOSFET transistor.Both transistors are formed by cells each containing an elementary bipolar transistor and an elementary MOSFET transistor.

Abstract: A semiconductor device includes on a semiconductor substrate an output transistor which is composed of a collector region, a first base region and a first emitter region, and a temperature detection transistor composed of the collector region, a second base region and a second emitter region. The output transistor is provided at a center of the collector region of the semiconductor substrate. A vacant region is formed on a center of the output transistor, and the temperature detection transistor is provided in the vacant region.

Abstract: A monolithic integrated semiconductor is proposed, in which on the main surface of a monolithically integrated n-p-n transistor or p-n-p transistor, a cover electrode (D1) is mounted for internal voltage limitation, covering only a single junction region between a highly doped zone (5) and the weakly doped substrate (1). An adjacent highly doped zone (4) is not covered by the cover electrode (D1). By connecting the metal cover electrode (D1) to the pickup (12) for a voltage divider (R1, R2), a breakdown voltage can be adjusted that is higher than the sum of the depletion breakdown voltage and the enhancement breakdown voltage.

Abstract: A planar semiconductor device having a heavily doped channel stopper region of the first conductivity type and at least the following components: a Zener diode having the following regions, seen from an upper surface of the device, an upper diode region of the second conductivity type, a lightly doped first upper component region, of the first conductivity type, in which the upper diode region and the channel stopper region are formed at the upper surface, and a heavily doped lower component region of the first conductivity type; and a component having a second upper component region formed with the upper diode region in the first upper component region at the upper surface and having the same conductivity type as the upper diode region, the first upper component region, the lower component region, and a third upper component region of the first conductivity type and formed in the second upper component region at the upper surface of the device.

Abstract: A Darlington transistor having improved comprehensive electric characteristic and a bipolar transistor having improved high voltage characteristic are obtained. A collector resistivity .rho.N.sup.- (F) of a collector high resistivity layer (11) in a front stage side transistor chip (TF) is set to 80 5/8cm and its collector film thickness tN.sup.- (F) is set to 120 .mu.m, and a collector resistivity .rho.N.sup.- (R) of a collector high resistivity layer (13) in a rear stage side transistor chip (TR) is set to 45 .OMEGA.cm and its collector film thickness tN.sup.- (R) is set to 160 .mu.m. Since .rho.N.sup.- (F)>.rho.N.sup.- (R) and tN.sup.- (F)<tN.sup.- (R) are satisfied, a Darlington transistor having a good comprehensive electric characteristic can be obtained, and also, since .rho.N.sup.- (R)/tN.sup.- (R)<0.6 is satisfied, a bipolar transistor having a good high voltage characteristic can be obtained (FIG. 8).

Abstract: Emitter-base protection for a first bipolar transistor formed as part of a BiCMOS circuit. A second bipolar transistor is formed in the same well as the first bipolar transistor with both transistors using the well as their collectors. A current path through the collector-emitter of the second transistor provides current to the base of the first transistor maintaining the emitter-to-base voltage of the first transistor at a relatively low reverse potential.

Abstract: An integral Bi-CMOS logic circuit includes a pair of first transistors and a pair of second transistors. The pair of the first transistors includes a P-type MOS transistor receiving an input signal through its gate, and an NPN-type bipolar transistor with its base connected to the drain of the P-type MOS transistor outputting a first output signal. The pair of the second transistors includes an N-type MOS transistor receiving the input signal through its gate, and a PNP bipolar transistor with its base connected to the drain of the N-type MOS transistor outputting the first output signal. A final output signal is outputted through a common emitter of the bipolar transistors.

Abstract: An input protection structure for integrated circuits is connected in a semiconductor substrate between an input and an output for a reference potential. The input protection structure includes a first transistor acting as an input transistor and a second transistor acting as a trigger transistor. The input transistor and the trigger transistor are connected in a cascade. The input transistor and the trigger transistor have a common collector forming the input of the protection structure. The input transistor has an emitter connected to the output for the reference potential. An oxide isolation is provided for adjacent components.