Abstract: A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

Abstract: A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.

Abstract: The present invention is a modified darlington phototransistor wherein a phototransistor is coupled to a Bipolar Junction Transistor (BJT). This design provides a high sensitivity and a fast response and effectively increases the gain of the photocurrent. This circuit is particularly will suited for the readily available CMOS and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) processes prevalent today.

Abstract: There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention provides the trimming pattern for use in trimming of a semiconductor integrated circuit, comprising two pads to which a voltage is applied, a thin line part interconnecting the two pads, and two connecting parts disposed away from each side of the thin line part, and connected to an adjustment circuit and the semiconductor integrated circuit, respectively. With the invention, trimming is executed by a method of turning the adjustment circuit connected to the connecting parts into the ON state by connecting fused metal of the thin line part to the connecting parts. In this case, since the fused metal can be caused to come into contact with the connecting parts nearby with greater ease than fusion cutting of the thin line part, trimming can be implemented with ease and in shorter time.

Abstract: A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.

Abstract: A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

Abstract: A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g.

Abstract: A transmission type encoder is disclosed, which comprises a main scale, a light source that radiates collimated light to the main scale, and a photodiode array that also functions as an index scale. The main scale has a rectangular grating in which light transmitting portions and light non-transmitting portions are arranged at pitch P, and each width of the light transmitting portions is set to 2p/3, whereby a third harmonic distortion in an output signal can be removed.

Abstract: An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q.sub.1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q.sub.1, a second optional transistor Q.sub.2, a first inductor L.sub.E in the emitter (source) of Q.sub.1, and a second inductor L.sub.B in the base (gate) of Q1. The emitter length l.sub.E1, or correspondingly the gate width w.sub.g, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z.sub.0, which is typically 50.OMEGA.. The first inductor L.sub.E, provides matching of the real part of the input impedance and the second inductor L.sub.B cancels out the noise reactance and input impedance reactance of the structure.

Abstract: The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.

Abstract: A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.