Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.

Abstract: The present invention provides a thin-film transistor and a fabrication method thereof, and an array substrate. The thin-film transistor includes a separation layer (5) arranged between the source electrode (4) and the drain electrode (6). An oxide semiconductor channel layer (7) is arranged on one side of the separation layer (5) and the drain electrode (6) to contact a portion of an upper surface of the drain electrode (6), a side surface of the drain electrode (6) and the organic separation layer (5), and a portion of an upper surface of the source electrode (4) to serve as a vertical channel, of which a channel length corresponds to a thickness of the separation layer (5). Varying the thickness of the separation layer to reduce the length of the vertical channel to a sub-micrometer order would greatly reduce the size of the thin-film transistor and reduce the area of a pixel. The vertical channel does not cause a short channel effect so as to improve electrical performance of the thin-film transistor.

Abstract: A thin film transistor, a manufacturing method for an array substrate, the array substrate, and a display device are provided. The manufacturing method for a thin film transistor includes: forming a semiconductor layer; performing a modification treatment on a surface layer of a region of the semiconductor layer, so that the region of the semiconductor layer has a portion in a first direction perpendicular to the semiconductor layer formed as an etching blocking layer, portions of the semiconductor layer on both sides of the etching blocking layer in a second direction parallel to a surface of the semiconductor layer remaining unmodified; and forming a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode being formed on both sides of a center line of the region perpendicular to the second direction, and spaced from each other in the second direction.

Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

Abstract: An electronic device includes a vertical-support-element with first and second edges having first and second reentrant profiles, respectively. The first reentrant profile includes first conformal semiconductor and dielectric layers, and a conformal conductive top-gate. A first electrode contacts a first portion of the first conformal semiconductor layer over the top of the vertical-support-element. A second electrode, adjacent to the first edge, contacts a second portion of the first conformal semiconductor layer not over the vertical-support-element. The second reentrant profile includes a conformal conductive bottom-gate, and second conformal dielectric and semiconductor layers. A third electrode, adjacent to the second edge, contacts the second semiconductor layer not over the vertical-support-element. A fourth electrode, over the vertical-support-element, contacts the second semiconductor layer.

Abstract: The present invention provides a TFT substrate structure and a manufacturing method thereof. The TFT substrate structure of the present invention includes an N-type lightly-doped amorphous silicon layer and an N-type heavily-doped amorphous silicon layer arranged between an amorphous silicon layer and a metal layer to form a gradient of doping concentration so as to reduce the potential barrier between the metal layer and the amorphous silicon layer, making injection of electrons easy and reducing the leakage current without lowering an operation current, thereby improving the electrical property of the TFT.

Abstract: Accuracy of photodetection is improved. A method for driving an input-output device which includes a light unit, a display circuit, and Y (Y is a natural number of 2 or more) photodetectors is provided. The same photodetection control signal is input to the Y photodetectors. The light unit is lit while the Z light-emitting diodes are sequentially switched and emit light in a frame period set by the display selection signal. In a cycle that is longer than a cycle of switching the lighting states of the light unit, Y pieces of data based on the illuminance of light incident on the Y photodetectors are generated in a period during which the light unit is lit.

Abstract: An array substrate comprises a substrate, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being provided in different areas on the substrate and the vertical projections of the source electrode and the drain electrode on the substrate having an overlapping area; a semiconductor layer formed between the source electrode and the drain electrode, a vertical projection of the semiconductor layer on the substrate having overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate; a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode; a pixel electrode, a gate line, and a data line. A manufacturing method for the array substrate is also disclosed.

Abstract: A method for manufacturing a thin-film transistor includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode which are opposed to each other and each of which has at least a portion located above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; and performing, in a hydrogen atmosphere, plasma treatment on an altered layer which (i) is a surface layer of the protective layer exposed from the source electrode and the drain electrode and altered by the dry etching, and (ii) has at least a portion contacting a surface of the semiconductor layer.

Abstract: There is provided an active matrix EL display device that can display a clear multi gray-scale color display to reduce the shift in the potential caused by the potential drop due to the wiring resistance of a power source supply line, in order to decrease the unevenness in a display region. A plurality of drawing out ports of the power source supply line are arranged. Further, in the wiring resistance between the external input terminal and the pixel portion power source supply line, potential compensation is performed by supplying potential to the power source supply line by a feedback amplifier. Further, in addition to above structure, the power source supply line may be arranged in a matrix.

Abstract: A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.

Abstract: Generally, the devices provided herein comprise at least a hole-transport layer, two light-emitting layers, and an electron-transport layer, each having a highest occupied molecular orbital (HOMO) energy level and a lowest unoccupied molecular orbital (LUMO) energy level, wherein at least one of the HOMO energy levels and/or the LUMO energy levels of at least one of the light-emitting layers does not decrease in a stepwise fashion.

Abstract: A thin-film transistor with a fluorinated channel and fluorinated source and drain regions and methods of fabrication are provided. The thin-film transistor includes: a substrate; a semiconductor active layer of fluorine-doped metal-oxide formed on the substrate; fluorine-doped source and drain regions disposed adjacent to the semiconductor active layer; a gate electrode disposed over the semiconductor active layer, configured to induce a continuous conduction channel between the source and drain regions; and a gate dielectric material separating the gate electrode and the channel.

Abstract: Disclosed is a bonding system which efficiently performs a bonding of a substrate to a support substrate, thereby improving the throughput in a bonding processing. The disclosed bonding system includes a loading/unloading station and a processing station. The processing station includes: an adhesive applying device configured to apply an adhesive to the wafer; a protective agent applying device configured to apply a protective agent to the wafer, a remover applying device configured to apply a remover to the support wafer, a heat processing device configured to heat the wafer or the support wafer which is applied with at least the adhesive, the protective agent or the remover, at a predetermined temperature, a bonding device configured to bond the wafer to the support wafer through the adhesive, the protective agent and the remover, and a wafer transfer area configured to transfer the wafer, the support wafer or the bonded wafer.

Abstract: The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized.

Abstract: A first thin film diode (100A) has a first semiconductor layer (10A) and a first light blocking layer (12A) disposed on the substrate side of the first semiconductor layer. A second thin film diode (100B) has a second semiconductor layer (10B) and a second light blocking layer (12B) disposed on the substrate side of the second semiconductor layer. An insulating film (14) is formed between the first semiconductor layer (10A) and the first light blocking layer (12A) and between the second semiconductor layer (10B) and the second light blocking layer (12B). A thickness D1 of a portion of the insulating film (14) positioned between the first semiconductor layer (10A) and the first light blocking layer (12A) is different from a thickness D2 of a portion of the insulating film (14) positioned between the second semiconductor layer (10B) and the second light blocking layer (12B).

Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.

Abstract: An object is to increase the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion includes a channel-etched thin film transistor for a driver circuit, in which a source electrode and a drain electrode are formed using a metal and a channel layer is formed using an oxide semiconductor, and a driver circuit wiring formed using a metal. The display portion includes a channel protection thin film transistor for a pixel, in which a source electrode and a drain electrode are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor, and a display portion wiring formed using an oxide conductor. The thin film transistors provided in the semiconductor device are formed with a resist mask formed using a multi-tone mask.

Abstract: There is provided an active matrix EL display device that can display a clear multi gray-scale color display to reduce the shift in the potential caused by the potential drop due to the wiring resistance of a power source supply line, in order to decrease the unevenness in a display region. A plurality of drawing out ports of the power source supply line are arranged. Further, in the wiring resistance between the external input terminal and the pixel portion power source supply line, potential compensation is performed by supplying potential to the power source supply line by a feedback amplifier. Further, in addition to above structure, the power source supply line may be arranged in a matrix.

Abstract: An image sensor pixel includes a photosensitive element having a first doping type disposed in semiconductor material. A deep extension having the first doping type is disposed beneath and overlapping the photosensitive element in the semiconductor material. A floating diffusion is disposed in the semiconductor material. A transfer gate is disposed over a gate oxide that is disposed over the semiconductor material. The transfer gate is disposed between the photosensitive element and the floating diffusion. The photosensitive element and the deep extension are stacked in the semiconductor material in a “U” shape extending from under the transfer gate.

Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.

Abstract: A semiconductor device 101 includes: a substrate 1; an active layer 4 provided on the substrate 1 and including a channel region 4c, and a first region 4a and a second region 4b that are respectively located on opposite sides of the channel region 4c; first and second contact layers 6a and 6b respectively in contact with the first and second regions 4a and 4b of the active layer 4; a first electrode 7 electrically coupled to the first region 4a via the first contact layer 6a; a second electrode 8 electrically coupled to the second region 4b via the second contact layer 6b; and a gate electrode 2 provided such that a gate insulating layer 3 is interposed between the gate electrode 2 and the active layer 4, the gate electrode 2 being configured to control a conductivity of the channel region 4c. The active layer 4 contains silicon. The semiconductor device further includes an oxygen-containing silicon layer 5 between the active layer 4 and the first and second contact layers 6a, 6b.

Abstract: Provided is a method of manufacturing a photovoltaic device using a Joule heating-induced crystallization method. The method includes: forming a first conductive pattern on a substrate; forming a photoelectric conversion layer on the substrate having the first conductive pattern; and crystallizing at least part of the photoelectric conversion layer by applying an electric field to the photoelectric conversion layer, wherein the photoelectric conversion layer includes a first amorphous semiconductor layer containing first impurities, a second intrinsic, amorphous semiconductor layer, and a third amorphous semiconductor layer containing second impurities.

Abstract: A liquid crystal display device and a method for fabricating the same are provided. The method includes forming a gate line and a data line on a first substrate crossing each other to define a pixel region; forming a gate electrode, a source electrode and a drain electrode of a transistor on the first substrate; forming an active layer below the data line and between the gate electrode and each of the source electrode and the drain electrode, wherein the active layer below the data line has an exposed portion exposed by the data line; removing the exposed portion of the active layer below the data line; and forming a pixel electrode connected to the drain electrode.

Abstract: A thin film transistor (TFT) and a pixel structure having the TFT are provided. The TFT is configured on a substrate. Besides, the TFT includes a gate, a gate insulation layer, a source, a channel layer, and a drain. The gate insulation layer covers the gate and the substrate. The source is configured on a portion of the gate insulation layer. The channel layer is configured on the gate insulation layer and covers a portion of the source located above the gate. The drain is configured on and electrically connected to the channel layer.

Abstract: A headset is able to be coupled via a cable to an intercom system, is able to be wirelessly coupled to a wireless device via a wireless transceiver of the headset, and is able to be connected to a wired device via another cable. A controller of the headset separately monitors the microphone conductors and audio conductors by which the headset may be coupled to the intercom system to detect whether or not one or both of a communications microphone and an acoustic driver of the headset are coupled to the intercom system, and monitors the operating state of the wireless transceiver to detect whether or not the wireless transceiver is inactive, on standby or in use; and selectively couples a system ground conductor to one of the microphone conductors, selectively provides a local sidetone, and/or selectively provides a local microphone bias voltage in response to what is observed through such monitoring.

Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.

Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.

Abstract: A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.

Abstract: There is provided an active matrix EL display device that can display a clear multi gray-scale color display to reduce the shift in the potential caused by the potential drop due to the wiring resistance of a power source supply line, in order to decrease the unevenness in a display region. A plurality of drawing out ports of the power source supply line are arranged. Further, in the wiring resistance between the external input terminal and the pixel portion power source supply line, potential compensation is performed by supplying potential to the power source supply line by a feedback amplifier. Further, in addition to above structure, the power source supply line may be arranged in a matrix.

Abstract: Provided is a display device including a p-type thin film transistor formed on a substrate, in which the p-type thin film transistor includes: a gate electrode; a drain electrode; a source electrode; an insulating film; a semiconductor layer formed on a top surface of the gate electrode through the insulating film; and diffusion layers of p-type impurities formed at each of an interface between the drain electrode and the semiconductor layer and an interface between the source electrode and the semiconductor layer, the drain electrode and the source electrode being formed so as to be opposed to each other with a clearance formed therebetween on a top surface of the semiconductor layer.

Abstract: A display device includes a substrate having a display region and a driver region; a gate line and a data line crossing each other to define a pixel region in the display region, the pixel region having a pixel electrode; an insulation layer between the gate line and the data line; a first thin film transistor in the display region; and a second thin film transistor having a first polarity and a third thin film transistor having a second polarity in the driver region, wherein the pixel electrode, the gate line and the gate electrodes of the first to third thin film transistors have a double-layer structure in which a metal layer is formed on a transparent conductive layer, and the transparent conductive layer of the pixel electrode is exposed through a transmission hole passing through the insulation layer and the metal layer in the pixel region.

Abstract: A method of forming a passivation layer comprises contacting at least one surface of a wide band-gap semiconductor material with a passivating agent comprising an alkali hypochloride to form the passivation layer on said at least one surface. The passivation layer may be encapsulated with a layer of encapsulation material.

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.

Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.

Abstract: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.

Abstract: The present invention provides an optoelectronic device comprising a heat source and a heat transfer fluid. The present invention also provides a method of preparing an optoelectronic device, which comprises (i) providing a heat source, and (ii) filling a space in the vicinity of the heat source with a heat transfer liquid. The optoelectronic device has gained technical merits such as improved heat removing efficiency, lower chip/junction temperature, increased lumen output, longer operational lifetime, and better reliability, among others.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: An exemplary thin film transistor (TFT) array substrate (200) includes: a substrate (210), a gate electrode (220) disposed on the substrate, a gate insulating layer (230) disposed on the substrate having the gate electrode, a lightly doped amorphous silicon (a-Si) layer (241) disposed on the gate insulating layer, a first a-Si layer (242) disposed on the lightly doped a-Si layer, a source electrode (251) and a drain electrode (252) disposed on the gate insulating layer and the a-Si layer. The thin film transistor array substrate has a low leakage current.

Abstract: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive layer. The width change part is formed away from a region of at least one of the conductive layers that crosses a neighboring conductive layer. The present invention also provides a flat panel display device that includes the electronic device described above and manufactured in accordance with the principles of the present invention. The electronic device of the present invention may comprise a thin film transistor.

Abstract: A TFT, in which source and drain electrodes having concentric circular shapes are formed, reduces an OFF current caused by a leakage current and optimizes an ON current and a stray capacitance between gate and source electrodes. The TFT includes a gate electrode formed on a substrate; and source and drain electrodes obtained by sequentially forming a gate insulating film, an intrinsic amorphous silicon layer, and an n+ amorphous silicon layer on the gate electrode, wherein the source and drain electrodes have circular shapes. One of the source and drain electrodes is disposed at the center, and the other one of the source and drain electrodes having a concentric circular shape surrounds the former. A channel region may be formed between the source and drain electrodes; and an area of an effective stray capacitance may be less than 150 ?m2. A ratio of a width of a channel to a length of the channel may be more than 4.5 and a filling capacity index to the effective stray capacitance may be less than 50.

Abstract: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by a thin-film transistor formed on a substrate 1 with a finely processed concavoconvex surface 2, in which a source electrode and a drain electrode are formed on adjacent convex portions of the concavoconvex surface 2, with a channel and a gate being formed on a concave area between the convex portions. A gate electrode 5, a gate insulating film 6 and a semiconductor channel layer 7 are laminated in this order on the concave area from the bottom surface of the concave portion toward the top surface.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.

Abstract: The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer.

Abstract: A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate insulator electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1 MV/cm to 2 MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cm3 to 1E+20/cm3.

Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.

Abstract: A low K dielectric composite layer is formed of a low k barrier layer and a low K dielectric layer on the barrier layer. The barrier layer, which is deposited with the result of having a hydrophobic top surface, is treated with an oxygen plasma to convert the surface from hydrophobic to hydrophilic. A subsequent water-based clean is very effective in removing yield-reducing defects on the barrier layer due to the conversion of the surface of the barrier layer. After the water-based clean, the low K dielectric layer is formed on the surface of the barrier layer to achieve the composite layer that has a low K.

Abstract: A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive, an insulating layer that covers the core, and a semiconductor layer that covers the insulating layer. Each of the function lines contacts with, and crosses, the conductor lines. Each of the transistors includes a first ohmic contact region, which is defined by a region where one of the conductor lines crosses one of the function lines and which makes an ohmic contact with the semiconductor layer, a second ohmic contact region, which also makes an ohmic contact with the semiconductor layer, and a channel region, which is defined in the semiconductor layer between the first and second ohmic contact regions.