Field Effect Device In Amorphous Semiconductor Material Patents (Class 257/57)
  • Patent number: 11437519
    Abstract: A TFT device and a manufacturing method of the same, a TFT array substrate and a display device is provided by this disclosure. A light-shielding layer is configured under the active layer, and one of the source doping member and the drain doping member is attached to the buffer layer and the light-shielding layer to generate a stable voltage on the light-shielding layer. At the same time, forming holes in the light-shielding layer and the buffer layer is avoided and connecting a source electrode, the active layer and the light-shielding layer with conductive lines is no more needed, which decreases one mask, and corresponding exposure and etching process, thus decreases manufacturing cost of the TFT.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 6, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wenbo Zhang
  • Patent number: 11411120
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer including an oxide semiconductor as a main component and forming an insulator layer on a surface of the semiconductor layer. The insulator layer includes silicon oside as a main component and has a hydrogen atom concentration that is less than or equal to 1×1021 atoms/cm3.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 9, 2022
    Assignee: ULVAC, INC.
    Inventors: Tadamasa Kobayashi, Hideaki Zama
  • Patent number: 11387366
    Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey, Shriram Shivaraman, Inanc Meric, Benjamin Chu-Kung
  • Patent number: 11355645
    Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: June 7, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Keisuke Murayama
  • Patent number: 11329075
    Abstract: An array substrate, its fabricating method, a display panel and a display device are disclosed. The method includes forming an active layer on a substrate, forming a gate layer on a side of the active layer facing or away from the substrate; forming an interlayer dielectric layer on a side of the active layer away from the substrate, which includes a first, second, third and fourth film stacked in this order in a direction away from the substrate; forming a via hole extending from the interlayer dielectric layer to the active layer; forming a source and drain layer on a side of the interlayer dielectric layer away from the substrate, and in a region not covered by the source and drain layer, removing the fourth film in the interlayer dielectric layer at a same time as forming the source and drain layer.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 10, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lulu Ye, Lei Yao, Kai Zhang, Dawei Shi, Nana Gao, Panpan Zhang
  • Patent number: 11329139
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Yu-Ming Lin, Clement Hsingjen Wann
  • Patent number: 11315961
    Abstract: (Object) To miniaturize a field-effect transistor. (Means of Achieving the Object) A field-effect transistor includes a semiconductor film formed on a base, a gate insulating film formed on a part of the semiconductor film, a gate electrode formed on the gate insulating film, and a source electrode and a drain electrode formed in contact with the semiconductor film, wherein a thickness of the source electrode and the drain electrode is smaller than a thickness of the gate insulating film, and the gate insulating film includes a region that is not in contact with the source electrode or the drain electrode.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 26, 2022
    Assignee: Ricoh Company, Ltd.
    Inventors: Sadanori Arae, Yuichi Ando, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Naoyuki Ueda, Ryoichi Saotome, Minehide Kusayanagi
  • Patent number: 11295985
    Abstract: Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can include a first field effect transistor (FET). The semiconductor structure can also include a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Tenko Yamashita, Kangguo Cheng, Lawrence A. Clevenger
  • Patent number: 11289513
    Abstract: A thin film transistor and a method for fabricating the same, an array substrate and a display device are provided. The thin film transistor includes an active layer and a protective layer being provided on and in direct contact with the active layer, the protective layer is provided corresponding to a channel region of the thin film transistor; the protective layer is made of an oxygen-enriched metallic oxide insulation material which will not introduce any new element into the active layer. In the thin film transistor and the method for fabricating the same, the array substrate and the display device provided by the present disclosure, the active layer can be protected from being damaged by the etchant for forming the source/drain, and no new element will be introduced into the active layer; thus the characteristics and the stability of the thin film transistor is improved.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: March 29, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ke Wang, Hehe Hu, Xinhong Lu
  • Patent number: 11257886
    Abstract: An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joon Woo Bae, So Young Koo, Han Bit Kim, Thanh Tien Nguyen, Kyoung Won Lee, Yong Su Lee, Jae Seob Lee, Gyoo Chul Jo
  • Patent number: 11251216
    Abstract: An imaging device includes: a semiconductor layer including a first region of a first conductivity, a second region of a second conductivity opposite to the first conductivity, and a third region of the second conductivity; a photoelectric converter electrically connected to the first region and converting light into charge; a first transistor including a first source, a first drain, and a first gate above the second region, the first region corresponding to the first source or drain; and a second transistor including a second source, a second drain, and a second gate of the second conductivity above the third region, the first region corresponding to the second source or drain, and the second gate being electrically connected to the first region. The concentration of an impurity of the second conductivity in the third region is higher than that of an impurity of the second conductivity in the second region.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 15, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Hirase, Yoshinori Takami, Yoshihiro Sato
  • Patent number: 11239262
    Abstract: An embodiment of the present invention discloses an array substrate, a method of fabricating the same, and a display panel. Compared with the conventional technology, the present invention combines a sensing material with thin film transistors to prepare a sensing layer on the thin film transistors, and since the thin film transistors can be formed by a large-area preparation, the sensors can be formed by a large-area preparation accordingly, thereby improving a performance of the sensors and reducing the production cost of the sensors.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: February 1, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Juncheng Xiao, Chao Tian
  • Patent number: 11227920
    Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a memory transistor. The memory transistor includes a conductor including an opening, a first insulator provided in contact with an inner side of the opening, a second insulator provided in contact with an inner side of the first insulator, a third insulator provided in contact with an inner side of the second insulator, a first oxide provided in contact with an inner side of the third insulator, and a second oxide provided in contact with an inner side of the first oxide. An energy gap of the second oxide is narrower than an energy gap of the first oxide.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: January 18, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11227882
    Abstract: A thin film transistor, a method for fabricating the same, a display substrate, and a display device are disclosed. The thin film transistor includes a gate, a source, a drain, and an active layer. Forming the active layer includes: forming a pattern comprising a thermal insulation layer; forming a pattern comprising an amorphous silicon layer on the thermal insulation layer, wherein the pattern comprising the amorphous silicon layer includes a first portion on the thermal insulation layer and a second portion extending beyond the thermal insulation layer; and treating the pattern comprising the amorphous silicon layer with a laser annealing process, so that the amorphous silicon layer grows grain in a direction from the second portion to the first portion to form the active layer from polycrystalline silicon.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 18, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaolong Li, Dong Li, Huijuan Zhang, Zheng Liu
  • Patent number: 11201306
    Abstract: The present invention relates to a display device comprising—a plurality of OLED pixels comprising at least two OLED pixels, the OLED pixels comprising an anode, a cathode, and a stack of organic layers, wherein the stack of organic layers—is arranged between and in contact with the cathode and the anode, and—comprises a first electron transport layer, a first hole transport layer, and a first light emitting layer provided between the first hole transport layer and the first electron transport layer, and—a driving circuit configured to separately driving the pixels of the plurality of OLED pixels, wherein, for the plurality of OLED pixels, the first hole transport layer is provided in the stack of organic layers as a common hole transport layer shared by the plurality of OLED pixels, and the first hole transport layer comprises (i) at least one first hole transport matrix compound consisting of covalently bound atoms and (ii) at least one electrical p-dopant selected from metal salts and from electrically neu
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 14, 2021
    Assignee: Novaled GmbH
    Inventors: Ulrich Heggemann, Markus Hummert
  • Patent number: 11145703
    Abstract: A display device may include a substrate, a first layer on the substrate, the first layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a second layer on the first layer, an active pattern on the second layer, the active pattern overlapping only the first portion of the first layer, a gate electrode on the active pattern, a source electrode and a drain electrode on the gate electrode and connected to the active pattern, a first electrode connected to one of the source electrode and the drain electrode, a pixel defining layer on the first electrode, the pixel defining layer having an opening portion exposing at least a portion of the first electrode, an emission layer in the opening portion on the first electrode, and a second electrode on the emission layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jongoh Seo, In Cheol Ko, Byung Soo So, Dong-min Lee, Dong-Sung Lee
  • Patent number: 11114449
    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j?1th sub memory cell.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 7, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Tamae Moriwaka, Yuta Endo
  • Patent number: 11107930
    Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi
  • Patent number: 11088171
    Abstract: The present application relates to an array substrate, a display panel and a method of manufacturing the same, the array substrate comprising a substrate, a plurality of active switches, a color filter layer, a spacer unit layer, and an electrode layer formed on the color filter layer and the spacer unit layer.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 10, 2021
    Assignee: HKC Corporation Limited
    Inventor: Beizhou Huang
  • Patent number: 11075303
    Abstract: An oxide semiconductor compound includes gallium; and oxygen. An optical band gap is 3.4 eV or more. An electron Hall mobility obtained by performing a Hall measurement at a temperature of 300 K is 3 cm2/Vs or more.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 27, 2021
    Assignees: TOKYO INSTITUTE OF TECHNOLOGY, AGC Inc.
    Inventors: Hideo Hosono, Toshio Kamiya, Hideya Kumomi, Junghwan Kim, Nobuhiro Nakamura, Satoru Watanabe, Naomichi Miyakawa
  • Patent number: 11063103
    Abstract: A display device includes a substrate, a pixel driver on the substrate, and a display element connected to the pixel driver. The pixel driver includes a conductive layer on the substrate, a buffer layer on the conductive layer, a semiconductor layer on the buffer layer, a gate electrode, the gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer. The buffer layer includes a flattened portion overlapping the conductive layer, and a stepped portion overlapping the periphery of the conductive layer. The semiconductor layer includes a first oxide semiconductor layer on the buffer layer, and a second oxide semiconductor layer on the first oxide semiconductor layer. A width of the first oxide semiconductor layer is larger than a width of the second oxide semiconductor layer, and the first oxide semiconductor layer is on the stepped portion of the buffer layer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 13, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: JungSeok Seo, PilSang Yun, SeHee Park, Jiyong Noh
  • Patent number: 11056552
    Abstract: A display panel and a method of manufacturing of the same are provided. The display panel includes a storage capacitor and a light emitting structure. The light emitting structure is disposed above the storage capacitor, and a light emitting surface of the light emitting structure faces the storage capacitor. A first plate of the storage capacitor includes an anode and an active area electrically connected with each other, and a second plate of the storage capacitor includes a source/drain electrode layer, and the source/drain electrode layer is a transparent electrode.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: July 6, 2021
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Zhenfei Cai
  • Patent number: 11043571
    Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 22, 2021
    Assignee: ACORN SEMI, LLC
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 11004875
    Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 11, 2021
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Catherine Ramsdale, Brian Hardy Cobb, Feras Alkhalil
  • Patent number: 10991827
    Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 27, 2021
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yutong Hu, Chihyuan Tseng, Chihyu Su, Wenhui Li, Xiaowen Lv, Longqiang Shi, Hejing Zhang
  • Patent number: 10968522
    Abstract: The disclosure provides a method for fabricating a metallic optical metasurface having an array of hologram elements. The method includes forming a first copper layer protected with a conducting or dielectric barrier layer over a backplane structure by a damascene process. The first copper layer comprises a plurality of nano-gaps vertically extending from the backplane structure. The plurality of nano-gaps is filled with a dielectric material. The method also includes removing the dielectric material and a portion of the conducting or dielectric barrier layer to expose the portions in the nano-gaps of the first copper layer. The method may further include depositing a dielectric coating layer over the top portion and exposed side portions of the first copper layer to form a protected first copper layer, and filling the gaps with an electrically-tunable dielectric material that has an electrically-tunable refractive index.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 6, 2021
    Assignee: Elwha LLC
    Inventors: Gleb M. Akselrod, Erik Edward Josberger, Mark C. Weidman
  • Patent number: 10971491
    Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Yutaka Okazaki
  • Patent number: 10964838
    Abstract: The present disclosure discloses a display substrate, a manufacturing method thereof, a display panel, and a display device. The display substrate includes a base substrate, a black matrix disposed on the base substrate, and a switching unit and an optical detection unit that are disposed at a side of the black matrix away from the base substrate. The optical detection unit is electrically connected to the switching unit, and an orthographic projection of at least one of the switching unit and the optical detection unit on the base substrate is located in an orthographic projection of the black matrix on the base substrate. Since the orthographic projection of at least one of the switching unit and the optical detection unit on the base substrate is located in the orthographic projection of the black matrix on the base substrate, the aperture ratio of the display substrate may increase.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 10930788
    Abstract: A display panel includes a base substrate, and thin film transistors positioned on the base substrate. Each thin film transistor includes a polysilicon layer. The display panel further includes a light-shielding layer for blocking ultraviolet (UV) light that is located at a side of the polysilicon layer away from the base substrate. An orthographic projection of the polysilicon layer on the substrate is in a range of an orthographic projection of the light-shielding layer on the substrate.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 23, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qi Yao, Zhanfeng Cao, Feng Zhang, Haixu Li, Shengguang Ban, Zhiyong Liu
  • Patent number: 10930723
    Abstract: A display device is disclosed. The display device according to an exemplary embodiment of the present disclosure includes: a substrate including an active area and a non-active area; an active layer, a thin film transistor including a gate electrode, a source electrode, and a drain electrode disposed on the substrate; and an organic light emitting diode including an anode which is electrically connected to the thin film transistor, in which the gate electrode, the source electrode, and the drain electrode are formed of a first conductive layer and a second conductive layer on the first conductive layer and the anode is formed of the same material as the first conductive layer. Therefore, the anode and the first conductive layer of the drain electrode are integrally connected so that a separate contact hole for electrically connecting the anode and the drain electrode is not necessary and the structure may be simplified.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 23, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: JongSik Shim, SeongHwan Hwang, KilHwan Oh
  • Patent number: 10930792
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10910413
    Abstract: The present disclosure provides a method of manufacturing array substrate, including: providing a substrate; and forming a metal layer, a gate layer, an insulation layer, and a protective layer on the substrate sequentially. Wherein, the metal layer is formed on a drive line on the substrate, and the metal layer is arranged in at least one of a position between the substrate and the insulation layer and a position between the insulation layer and the protective layer. In the present disclosure, an electrostatic discharge path is increased through the floating metal layer. Even though the floating metal layer is burned down, a display quality would not be affected, the product yield is improved. Besides, it only needs to adjust a photomask pattern. Therefore, a production procedure needs not to be adjusted.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 2, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chuan Wu
  • Patent number: 10908444
    Abstract: [Object] To provide a display device, a method for producing a display device, and a display apparatus of projection type, which are capable of suppressing deterioration of image quality attributable to a depressed space between pixel electrodes. [Solving Means] A display device of the present disclosure includes pixel electrodes formed for individual pixels and an insulating film for insulation between the pixel electrodes. The insulating film is so formed as to protrude from an electrode surface between the pixel electrodes. A display apparatus of projection type of the present disclosure uses the display device of the present disclosure as a light modulator to module light from a light source. A method for producing a display device of the present disclosure having pixel electrodes formed for individual pixels and an insulating film for insulation between the pixel electrodes includes forming the insulating film as to protrude between the pixel electrodes.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 2, 2021
    Assignee: SONY CORPORATION
    Inventors: Takashi Sakairi, Koichi Amari, Chiho Araki, Hitori Tanigawa, Katsumi Kouno, Keiichi Maeda, Takayoshi Masaki, Seiya Haraguchi
  • Patent number: 10903206
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Patent number: 10879328
    Abstract: The present disclosure relates to a thin film transistor (TFT) substrate, a manufacturing method thereof, and an organic light-emitting (OLED) substrate. The interlayer dielectric layer manufactured by the manufacturing method may be configured in the structure of two silicon oxide layers sandwiching one silicon nitride layer. As such, the bonding force between the interlayer dielectric layer and the gate, and the bonding force between the interlayer dielectric layer, and the source and the drain may be improved. The source and the drain may be prevented from falling off from the interlayer dielectric layer during the annealing process. Production yield of the TFT substrate may be improved. The OLED substrate adopting the manufactured of the OLED substrate of the present disclosure may have a better production yield and quality.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: December 29, 2020
    Assignees: WUHAN CHINA STAR OPTOELECTRONICS, SEMICONDUCTOR DISPLAY TECHNOLOGY CO.. LTD.
    Inventors: Lei Yu, Songshan Li
  • Patent number: 10854704
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10826481
    Abstract: A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Masashi Hayashiguchi, Kazuhide Ino
  • Patent number: 10811631
    Abstract: The thin film transistor element substrate of the present disclosure includes a first moisture barrier layer covering the gate insulating layer and the gate electrode, covering the contact regions of the oxide semiconductor layer other than the connecting portion of the contact region connected to the source electrode and the connecting portion of the contact region connected to the drain electrode, and covering an surface of the substrate on which the oxide semiconductor layer is not disposed. The first moisture barrier layer includes a metal oxide and is formed by atomic layer deposition. The first moisture barrier layer formed by atomic layer deposition is in contact with a pair of contact regions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 20, 2020
    Assignee: PANASONIC CORPORATION
    Inventor: Arinobu Kanegae
  • Patent number: 10802630
    Abstract: The disclosure discloses an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: a base substrate, a pressure-sensitive component, a plurality of dual-gate transistors, and a plurality of pixel transistors, where the pressure-sensitive component includes a first electrode layer, a pressure-sensitive layer, and a second electrode layer which are arranged on the base substrate in that order, and the second electrode layer includes a plurality of second electrodes arranged corresponding to the respective dual-gate transistors in a one-to-one manner; and the dual-gate transistors and the pixel transistors are arranged above the second electrode layer, and each of the plurality of second electrodes is electrically connected with a bottom-gate electrode in a corresponding dual-gate transistor, so that a pressure can be detected.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: October 13, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Yuzhen Guo, Xue Dong, Haisheng Wang, Chun-wei Wu, Xueyou Cao, Yingming Liu, Xiaoliang Ding, Chih-Jen Cheng
  • Patent number: 10782580
    Abstract: An array substrate includes a first substrate, a source electrode disposed on the first substrate, a semiconductor pattern layer disposed on the source electrode, a drain electrode disposed on the semiconductor pattern layer, a pixel electrode disposed on the drain electrode and a gate electrode disposed on at least one side surface of the semiconductor pattern layer. A method of making the solar panel is provided. A method of making the array substrate is provided.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: September 22, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Hun Noh, Keun Kyu Song, Hyun Sup Lee
  • Patent number: 10783966
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
  • Patent number: 10777662
    Abstract: The present disclosure provides a manufacturing method of a thin film transistor, including: selecting a substrate, and forming a bottom gate, a gate insulating layer and a source-drain above the selected substrate, wherein the bottom gate and the source-drain adopts a conductive metal oxide with an adjustable work function as a metal conducting electrode; rinsing and drying the source-drain of the selected substrate, and ozone cleaning dried source-drain for a predetermined time under a predetermined illumination condition, bombarding the source-drain with oxygen plasma for a period of time, forming an active layer made of a carbon material over the source-drain; forming a passivation layer over the active layer. The implementation of the disclosure can reduce the contact resistance and improve the performance of the carbon-based thin film transistor device by adjusting the work function of the contact surface between the conductive metal and the active layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 15, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 10770274
    Abstract: A copper alloy sputtering target is formed by a copper alloy including the content of Ca being 0.3 to 1.7% by mass, the total content of Mg and Al being 5 ppm or less by mass, the content of oxygen being 20 ppm or less by mass, and the remainder is Cu and inevitable impurities. A manufacturing method of a copper alloy sputtering target comprises steps of: preparing a copper having purity of 99.99% or more by mass; melting the copper so as to obtain a molten copper; controlling components so as to obtain a molten metal having a predetermined component composition by the addition of Ca having a purity of 98.5% or more by mass into the molten copper and by melting the Ca; casting the molten metal so as to obtain an ingot; and performing stress relieving annealing after performing hot rolling to the ingot.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 8, 2020
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Satoru Mori, Toshio Sakamoto, Kiyoyuki Ookubo
  • Patent number: 10756444
    Abstract: A liquid crystal panel included in a scanning antenna includes: a TFT substrate including a first dielectric substrate, a TFT supported by the first dielectric substrate, a gate bus line, a source bus line, a patch electrode, and a first alignment film covering the patch electrode; a slot substrate including a second dielectric substrate, a slot electrode formed on a first main surface of the second dielectric substrate and including a slot disposed corresponding to the patch electrode, and a second alignment film covering the slot electrode; and a liquid crystal layer provided between the TFT substrate and the slot substrate and containing a liquid crystal molecule including an isothiocyanate group. The first alignment film and the second alignment film are each independently formed of a polyimide-based alignment film material.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masanobu Mizusaki, Jumpei Takahashi, Hiroshi Tsuchiya
  • Patent number: 10755945
    Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 10749000
    Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Seunghan Seo, Yeohyun Sung
  • Patent number: 10749015
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 10741693
    Abstract: A thin film transistor includes a gate electrode, an active layer formed of oxide semiconductor material on a substrate, and a gate insulation layer therebetween. The active layer includes a channel region corresponding to the gate electrode, a source region at one side of the channel region, and a drain region at the other side of the channel region. The source region includes a first upper portion and the drain region includes a second upper portion that includes the oxide semiconductor material and Si.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Ju-Heyuck Baeck
  • Patent number: 10741697
    Abstract: A thin film transistor is provided. The thin film transistor includes an oxide semiconductor layer on a substrate, a gate electrode insulated from the oxide semiconductor layer to overlap at least a portion of the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first oxide semiconductor layer on the substrate and a second oxide semiconductor layer on the first oxide semiconductor layer, the first oxide semiconductor layer includes nitrogen of 1 at % to 5 at % concentration with respect to number of atoms, and the second oxide semiconductor layer has a nitrogen concentration which is lower than a nitrogen concentration of the first oxide semiconductor layer and a gradient of the nitrogen concentration such that the nitrogen concentration is lowered in a direction closer to the gate electrode.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jiyong Noh, Jaeman Jang, JuHeyuck Baeck, PilSang Yun
  • Patent number: 10734529
    Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi