Field Effect Device In Amorphous Semiconductor Material Patents (Class 257/57)
  • Patent number: 10381600
    Abstract: An organic electroluminescence device includes a base material including a recessed portion on one face side, and a light emitting element. The light emitting layer including a reflective layer disposed at least on a surface of the recessed portion, a filling layer that has optical transparency and is filled and disposed in the recessed portion with the reflective layer interposed between the recessed portion and the filling layer, a first electrode that has optical transparency and is disposed at least on an upper-layer side of the filling layer, an organic layer that includes at least a light emitting layer and is disposed on an upper layer of the first electrode, and a second electrode that has optical transparency and is disposed on an upper-layer side of the organic layer. The organic electroluminescence device includes a display region divided into a plurality of unit regions separated from each other. The unit regions each has a light emitting area and a non emissive area that are partitioned.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Uchida, Katsuhiro Kikuchi, Yoshiyuki Isomura, Eiji Koike, Satoshi Inoue, Yuto Tsukamoto, Masanori Ohara, Asae Ito
  • Patent number: 10373980
    Abstract: To provide a display device including a transistor that includes an oxide semiconductor and has favorable characteristics, a pixel electrode electrically connected to the transistor, and a capacitor electrically connected to the pixel electrode. To provide a display device that can be manufactured at low cost. The display device includes a display element including a pixel electrode, a transistor that performs switching of the display element and includes a first oxide semiconductor layer serving as a channel formation region, a capacitor that is electrically connected to the display element and includes a dielectric layer between a pair of electrodes. The pixel electrode is a second oxide semiconductor layer formed on the same surface as that on which the first oxide semiconductor layer is formed, and also serves as one electrode of the capacitor.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Shunpei Yamazaki
  • Patent number: 10361242
    Abstract: A solid-state imaging device includes a sensor including an impurity diffusion layer provided in a surface layer of a semiconductor substrate; and an oxide insulating film containing carbon, the oxide insulating film being provided on the sensor.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Sony Corporation
    Inventors: Itaru Oshiyama, Yuki Miyanami, Susumu Hiyama, Kazuki Tanaka
  • Patent number: 10324050
    Abstract: Methods and systems for optimizing measurement system parameter settings of an x-ray based metrology system are presented. X-ray based metrology systems employing an optimized set of measurement system parameters are used to measure structural, material, and process characteristics associated with different semiconductor fabrication processes with greater precision and accuracy. In one aspect, a set of values of one or more machine parameters that specify a measurement scenario is refined based at least in part on a sensitivity of measurement data to a previous set of values of the one or more machine parameters. The refinement of the values of the machine parameters is performed to maximize precision, maximize accuracy, minimize correlation between parameters of interest, or any combination thereof. Refinement of the machine parameter values that specify a measurement scenario can be used to optimize the measurement recipe to reduce measurement time and increase measurement precision and accuracy.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 18, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: John J. Hench, Andrei V. Shchegrov, Michael S. Bakeman
  • Patent number: 10319883
    Abstract: A semiconductor device includes a substrate, a gate electrode, an oxide semiconductor film, a first electrode, a second electrode, and a third electrode. The gate electrode is provided on the substrate. The oxide semiconductor film is provided on the substrate with the gate electrode interposed therebetween. The oxide semiconductor film includes a channel region facing the gate electrode and a low-resistance region adjacent to the channel region. The first electrode contains a constituent material same as that of the gate electrode, and has same thickness as that of the gate electrode. The second electrode has at least a portion facing the first electrode, and contains a constituent material same as that of the oxide semiconductor film. The third electrode has at least a portion provided at a position facing the first electrode with the second electrode interposed therebetween. The third electrode is electrically coupled to the first electrode.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: June 11, 2019
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Motohiro Toyota
  • Patent number: 10312388
    Abstract: Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 4, 2019
    Assignees: Micron Technology, Inc., Massachusetts Institute of Technology
    Inventors: Roy Meade, Karan Mehta, Efraim Megged, Jason Orcutt, Milos Popovic, Rajeev Ram, Jeffrey Shainline, Zvi Sternberg, Vladimir Stojanovic, Ofer Tehar-Zahav
  • Patent number: 10303277
    Abstract: There is provided a flat panel display device and a method of manufacturing the same. A flexible and transparent material is coated on a supporting substrate to a small thickness so that film substrates are easily formed. Step differences are formed in the film substrates so that a distance between pads of the two film substrates is reduced. Since conductive balls with reduced diameters are used so that the pads may be electrically connected, the distance between pads is reduced so that it is possible to easily miniaturize a high resolution flat panel display device, to prevent electrical connection defect between the pads, and to reduce manufacturing expenses.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung Ho Choi
  • Patent number: 10304984
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10297651
    Abstract: A drive circuit, an organic light-emitting diode display, and methods for fabricating the same are provided. The drive circuit includes: a driving transistor, including a first gate, a first semiconductor layer disposed above the first gate, an etch stopping layer disposed on the first semiconductor layer, and a first source and a first drain which are disposed on the two sides of the first semiconductor layer, the first semiconductor layer being made of oxide semiconductor material; and a switching transistor, including a second gate, a second semiconductor layer disposed above the second gate, and a second source and a second drain which are disposed on two sides of the second semiconductor layer, the second semiconductor layer being made of oxide semiconductor material. In the drive circuit, reliability and uniformity of the drive transistors are improved, and parasitic capacitance of the switching transistor decreases.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 21, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yingteng Zhai, Yong Wu
  • Patent number: 10290720
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Hiroshi Fujiki, Hiromichi Godo, Yasumasa Yamane
  • Patent number: 10283579
    Abstract: There is provided a semiconductor device that includes a substrate, an electric field shielding layer, and a semiconductor element. The electric field shielding layer is provided on the substrate. The semiconductor element includes an electrode, and is provided on the electric field shielding layer with an insulating film in between.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 7, 2019
    Assignee: JOLED, Inc.
    Inventors: Yuichiro Ishiyama, Yuichi Kato, Tomoatsu Kinoshita, Takashige Fujimori, Kenta Masuda, Keiichi Akamatsu
  • Patent number: 10268093
    Abstract: The present invention discloses an array substrate, which comprises a substrate; a gate line and a gate connected to the gate line on the substrate; a first insulating layer covering the gate line and the gate; an active layer on the first insulating layer; an organic layer on the first insulating layer, which exposes the active layer; a source, a drain, and a data line connected with the source on the organic layer, the source and the drain being respectively connected with the active layer, the data line and the gate line being overlapped; a second insulating layer covering the source, the drain, the data line, and the active layer; a contact hole in the second insulating layer, the contact hole exposing the drain; and a pixel electrode on the second insulating layer, the pixel electrode being contacted with the drain through the contact hole.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Liang Xu
  • Patent number: 10263118
    Abstract: A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10262871
    Abstract: A method includes depositing a layer of silicon oxide onto a layer of silicon carbide; ion implanting the layer of silicon carbide, annealing the ion implanted layer of silicon carbide to produce defects within the layer of silicon carbide, performing photolithography using a mask layer on regions of the layer of silicon carbide to define regions for electrode deposition, removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition, forming one or more electrodes by depositing indium tin oxide (ITO) in each of the regions for electrode deposition, performing a first lift-off operation to remove the mask layer surrounding the electrodes, depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes, and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 16, 2019
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Osama Nayfeh, Anna Leese De Escobar, Brad Liu, Patrick Sims, Sam Carter, David Kurt Gaskill, Tom Reinecke
  • Patent number: 10255865
    Abstract: The present invention provides a data processing device connected with an intermission driving. The data processing device achieves a satisfactory power saving while ensuring a high level of display quality of the display device. Upon detection of non-data update in a frame buffer, the host calculates a next refreshing timing based on driving information obtained from a liquid crystal display device (LCD), sets a timer for a timeout after a length of time representing the calculated result, and then the host and the LCD shift to Intermission State 1. Thereafter, when the timer times out to bring the host back to Normal State and a data update at the frame buffer is detected, data for refreshing an display image in the LCD is transferred from the host to the LCD. If the amount of time representing the calculated result is longer than a predetermined baseline, a shift is made to Intermission State 2 which provides greater power saving than Intermission State 1.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: April 9, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Teruhisa Masui, Yousuke Nakamura, Noriyuki Tanaka, Tatsuhiko Suyama
  • Patent number: 10249763
    Abstract: A semiconductor device, an array substrate, and a display device, and their fabrication methods are provided. An exemplary semiconductor device includes a first electrode, an insulating layer, and a second electrode, over a substrate. A conductive layer is on the insulating layer. A semiconductor layer is on the first electrode, on a first sidewall of the insulating layer, on the conductive layer, on the second sidewall of the insulating layer, and on the second electrode. A first gate electrode is over a portion of the semiconductor layer that is on the first sidewall of the insulating layer. A second gate electrode is over a portion of the semiconductor layer that is on the second sidewall of the insulating layer.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng Liu, Xiaolong Li, Yueping Zuo, Lujiang Huangfu
  • Patent number: 10243064
    Abstract: To provide a highly reliable semiconductor device by giving stable electrical characteristics to a transistor including an oxide semiconductor film. A gate electrode layer is formed over a substrate, a gate insulating film is formed over the gate electrode layer, an oxide semiconductor film is formed over the gate insulating film, a conductive film is formed over the oxide semiconductor film, so that a region in vicinity of an interface with the oxide semiconductor film in contact with the conductive film is made amorphous, heat treatment is performed, the conductive film is then processed to form a source electrode layer and a drain electrode layer, and a part of the amorphous region in the oxide semiconductor film which is exposed by formation of the source electrode layer and the drain electrode layer is removed.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10224382
    Abstract: A method for manufacturing an OLED display screen integrated with a touch function is provided, which includes steps of providing a glass substrate, forming an insulating layer and a wiring circuit layer, forming an OLED light-emitting layer, forming a first insulating ceramic layer, forming a first insulating organic layer, forming a first touch electrode layer, forming a touch insulating ceramic layer, forming a wire through hole in the wiring region of the glass substrate, forming a second touch electrode layer; and forming a wire in the wiring region of the glass substrate, wherein the wire is to the wiring circuit layer through the wiring through hole.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: March 5, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xuwen Cao
  • Patent number: 10217752
    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j?1th sub memory cell.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Tamae Moriwaka, Yuta Endo
  • Patent number: 10211096
    Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Abbas Ali, Yaping Chen, Chao Zuo, Seetharaman Sridhar, Yunlong Liu
  • Patent number: 10211346
    Abstract: Disclosed is a liquid crystal display panel and a method for manufacturing the same. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 19, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 10203577
    Abstract: An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 12, 2019
    Assignee: Innolux Corporation
    Inventors: Te-Yi Chen, Han-Tsung Su, Hsin-Hung Lin, Ker-Yih Kao
  • Patent number: 10205003
    Abstract: A method for use in forming a fin of a field-effect transistor includes: patterning a mandrel into a substrate at least by recessing portions of the substrate; forming dielectric material at least on the recessed portions of the substrate, wherein the dielectric material partially covers exterior sidewalls of the mandrel; forming a first buffer at least on a portion of the exterior sidewalls of the mandrel not covered by the dielectric material; forming a second buffer at least on exterior sidewalls of the first buffer; forming a semiconductor channel at least on the dielectric material, wherein at least the second buffer is between the channel and the mandrel; exposing interior sidewalls of at least the first buffer at least by removing the mandrel; and removing the first buffer and the second buffer without removing the channel.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung, Renee T. Mo
  • Patent number: 10205029
    Abstract: A TFT, a manufacturing method thereof, and a display device are provided. The TFT includes a semiconductor layer and an etch-stop layer merely covering a channel region of the semiconductor layer. The semiconductor layer and the etch-stop layer are formed through a single patterning process.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiushi Wang, Dalin Cui
  • Patent number: 10192957
    Abstract: a thin-film transistor according to an exemplary embodiment of the present invention comprises an active layer; an intermediate layer; a gate insulating film; a gate electrode; an interlayer insulating film; and source and drain electrodes. The active layer is positioned on a substrate, and the gate insulating film is positioned on the active layer. The gate electrode is positioned on the gate insulating film, and the interlayer insulating film is positioned on the gate electrode. The source and drain electrodes are positioned on the interlayer insulating film and connected to the active layer. The intermediate layer is positioned between the active layer and the gate insulating film, and made of an oxide semiconductor comprising a Group IV element.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 29, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Juheyuck Baeck, Jonguk Bae, Saeroonter Oh, Dohyung Lee, Taeuk Park
  • Patent number: 10181531
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 10181506
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10164118
    Abstract: A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 25, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisao Ochi, Tohru Daitoh, Hajime Imai, Tetsuo Fujita, Hideki Kitagawa, Tetsuo Kikuchi, Masahiko Suzuki, Shingo Kawashima
  • Patent number: 10153346
    Abstract: To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target. In that case, partial pressure of water in a deposition chamber before or in the deposition is set to be lower than or equal to 10?3 Pa, preferably lower than or equal to 10?4 Pa, more preferably lower than or equal to 10?5 Pa. Thus, a dense oxide semiconductor film is obtained. The density of the oxide semiconductor film is higher than 6.0 g/cm3 and lower than 6.375 g/cm3.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Yusuke Nonaka, Hiroshi Kanemura
  • Patent number: 10147896
    Abstract: An organic thin film transistor and a method of manufacturing the same, the transistor including a gate electrode; an organic semiconductor layer overlapping the gate electrode; and an insulating layer between the gate electrode and the organic semiconductor layer, the insulating layer having an organic/inorganic hybrid region, wherein the organic/inorganic hybrid region includes a polymer and an inorganic material that is chemically bonded to the polymer through a reactive group on the polymer, and the insulating layer includes a space adjacent to the polymer, the inorganic material being positioned in the space.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Hun Kim, Hyo Jeong Kwon, Il Hwa Hong, Seung Yong Song, Sang Hwan Cho
  • Patent number: 10141346
    Abstract: The present invention discloses a thin film transistor, a liquid crystal display and the manufacturing method of a thin film transistor. The thin film transistor includes a substrate, a gate electrode formed on the surface of the substrate; a gate insulting layer covered on the gate electrode; a semiconductor layer disposed on the surface of the gate insulating layer and corresponding to the gate electrode; an etching stop layer covered the semiconductor layer and having a first through hole and a second through hole; a passivation layer covered the etching stop layer having a third through hole and a fourth through hole; a source electrode disposed on the passivation layer and connected to the semiconductor layer via the first and the third through hole; and a drain electrode disposed on the passivation layer and connected to the semiconductor layer via the second and the fourth through hole.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: November 27, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xun Liu
  • Patent number: 10134914
    Abstract: To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first to third oxide semiconductor films contain the same element. The second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masami Jintyou, Yukinori Shima
  • Patent number: 10134812
    Abstract: An electronic device includes a control electrode 11 formed on a substrate 10, an insulating layer 12 covering the control electrode 11, an active layer 13 including an organic semiconductor material, which is formed on the insulating layer 12, and a first electrode 14A and a second electrode 14B formed on the active layer 13, and portions 15 of the first electrode and second electrode in contact with the active layer 13 are modified with an electrode modification material.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 20, 2018
    Assignee: SONY CORPORATION
    Inventors: Mao Katsuhara, Hideki Ono, Shinichi Ushikura, Yui Ishii
  • Patent number: 10127426
    Abstract: A fingerprint detector includes a driving circuit, a sensing array, a gate driving circuit, a reading circuit, a first light emitting structure and a second light emitting structure. The first and the second light emitting structures are isolated from one another. The driving circuit provides power to the first and the second light emitting structures. The sensing array includes a plurality of first light sensing elements disposed under the first light emitting structure and a plurality of second light sensing elements disposed under the second light emitting structure. Each of the light sensing elements generates a light sensing voltage according to scanning light received. The gate driving circuit drives a plurality of rows of the light sensing elements sequentially through a plurality of gate lines. The reading circuit sequentially or synchronously reads the light sensing voltages generated by light sensing elements in different columns of a same row driven by the gate driving circuit.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 13, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Tsung-Hsien Hsieh, Jeng-Yi Huang
  • Patent number: 10118028
    Abstract: Systems and methods are disclosed for insertion of implantable medical devices, and more particularly to insertion of implantable devices with a vibrating insertion tool. More specifically, a vibrating insertion tool is described, the insertion tool comprising an insertion tool controllable by a user to support and guide movement of an object, the insertion tool comprising an elongate arm having a proximal end region and a distal end region, the distal end region having a receiving region, a user-controllable vibration source for generating vibrations in accordance with a selected vibration profile, and an elongate rigid spine, connected to the vibration source and the receiving region, configured to deliver the vibrations to the receiving region.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 6, 2018
    Assignee: Cochlear Limited
    Inventors: James G. E. Smith, John Thomas Roland, Jr., Frank Risi, Ben Johnston
  • Patent number: 10096720
    Abstract: To provide a semiconductor device with high design flexibility. A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. A semiconductor layer where a channel of the first transistor is formed and a semiconductor layer where a channel of the second transistor is formed are formed using semiconductor materials having different electron affinities. When an oxide semiconductor is used for the semiconductor layer, an insulating layer containing excess oxygen is used as an insulating layer below the semiconductor layer. By increasing the thickness of the insulating layer, a large amount of oxygen can be supplied to the semiconductor layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinori Ando
  • Patent number: 10095078
    Abstract: According to an aspect, a liquid crystal display panel includes an extending portion. The extending portion is metal wiring provided on the same plane as a plane parallel to a surface of a TFT substrate on which a scan line extends in the X-direction, and is electrically conductive metal extending from the scan line. The extending portion partially overlaps a space, but does not overlap an opening area, in the Z-direction.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 9, 2018
    Assignee: Japan Display Inc.
    Inventor: Gen Koide
  • Patent number: 10083907
    Abstract: A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10084013
    Abstract: A thin-film transistor includes a substrate, a gate electrode formed on a surface of the substrate, a gate protection layer and a semiconductor layer stacked on the gate electrode, and an etch stop layer, source terminal metal, and drain terminal metal formed on a surface of the semiconductor layer in such a way that the source terminal metal and the drain terminal metal are respectively located on two opposite sides of the etch stop layer. The thin-film transistor further includes a light shielding layer, an insulation medium layer, and a pixel electrode. The light shielding layer is stacked on the etch stop layer to prevent light from irradiating the semiconductor layer. The insulation medium layer covers the source terminal metal, the drain terminal metal, and the light shielding layer. The pixel electrode is formed on a surface of the insulation medium layer and electrically connected to the drain terminal metal.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: September 25, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Qiuping Huang
  • Patent number: 10068951
    Abstract: A display apparatus including a substrate, a display portion disposed on an active area defined at the substrate, a buffer layer disposed on the active area and a pad area defined at the substrate, a touch sensing portion disposed on the buffer layer, and a pad portion disposed between the pad area and the buffer layer. The touch sensing portion includes a first pad pattern, a middle layer disposed on the first pad pattern, and a second pad pattern disposed on the middle layer. The first pad pattern is connected to the pad portion through a first contact hole defined on the pad portion in the buffer layer. The second pad pattern is connected to the first pad pattern through a second contact hole defined on the first contact hole in the middle layer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangkyu Choi, Sungkyun Park, Jungha Son, Jae-Wook Kang
  • Patent number: 10056492
    Abstract: A semiconductor device including a transistor is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a third insulating film over the source electrode, and a fourth insulating film over the drain electrode. A fifth insulating film including oxygen is provided over the transistor. The third insulating film includes a first portion, the fourth insulating film includes a second portion, and the fifth insulating film includes a third portion. The amount of oxygen molecules released from each of the first portion and the second portion is smaller than the amount of oxygen molecules released from the third portion when the amounts are measured by thermal desorption spectroscopy.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: August 21, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Daisuke Kurosaki
  • Patent number: 10032803
    Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Zhu Xun, Jae Woo Park, Jae Won Song, Keum Hee Lee, June Whan Choi
  • Patent number: 10032888
    Abstract: To provide a semiconductor device including an oxide semiconductor layer with high and stable electrical characteristics, the semiconductor device is manufactured by forming a first insulating layer, forming oxide over the first insulating layer and then removing the oxide n times (n is a natural number), forming an oxide semiconductor layer over the first insulating layer, forming a second insulating layer over the oxide semiconductor layer, and forming a conductive layer over the second insulating layer. Alternatively, the semiconductor device is manufactured by forming the oxide semiconductor layer over the first insulating layer, forming the second insulating layer over the oxide semiconductor layer, forming the oxide over the second insulating layer and then removing the oxide n times (n is a natural number), and forming the conductive layer over the second insulating layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Ryo Tokumaru, Yasumasa Yamane, Akihisa Shimomura, Naoki Okuno
  • Patent number: 10032801
    Abstract: A load related to a scanning line is decreased and a load related to a common electrode is decreased without decrease in an aperture ratio of each pixel. A display apparatus has a red sub-pixel and a green sub-pixel. A distance in the Y-axis direction between a pedestal electrode and a scanning line that drives a transistor in a plan view in the red sub-pixel is longer than a distance in the Y-axis direction between a pedestal electrode and a scanning line that drives a transistor in a plan view in the green sub-pixel. Furthermore, a superposed width of a light shielding film with a red pixel region in the Y-axis direction is larger than a superposed width of the light shielding film with a green pixel region in the Y-axis direction.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 24, 2018
    Assignee: Japan Display Inc.
    Inventor: Tadayoshi Katsuta
  • Patent number: 10026623
    Abstract: A thin film transistor substrate includes a plurality of thin film transistors arranged in columns and rows respectively on a substrate. Each of the thin film transistors includes a laser annealed part in which an amorphous silicon layer that forms a channel region is laser annealed to be a polysilicon layer, each laser annealed part is disposed with a designed pitch in a scanning direction in which a laser light for laser annealing and the substrate move relatively to each other, and the laser annealed part is provided within a channel width formed in a direction orthogonal to the scanning direction and being narrower than the channel width.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: July 17, 2018
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10013921
    Abstract: A display apparatus and a display control circuit which may contain an occurrence of the inappropriate brightness, such as flickering, at the time of pausing driving are provided. A scan period (St1, St2) during which a display panel drive device scans a display panel device and a retention period (Vt1) during which the display panel drive device does not scan the display panel device alternate and a timing control device causes the display panel drive device to scan the display panel device a plurality of times in the scan period when at least the brightness (Lb1) of the backlight device is changed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: July 3, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Asahi Yamato, Fumiyuki Kobayashi, Hikaru Kuki
  • Patent number: 10008607
    Abstract: According to one embodiment, a thin-film transistor includes a polycrystalline semiconductor layer, a gate electrode opposing the polycrystalline semiconductor layer, a gate insulating film provided between the gate electrode and the polycrystalline semiconductor layer and in contact with the gate electrode, and an amorphous layer provided between the gate insulating film and the polycrystalline semiconductor layer, and in contact with the gate insulating film and the polycrystalline semiconductor layer.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 26, 2018
    Assignee: Japan Display Inc.
    Inventor: Takashi Okada
  • Patent number: 10008609
    Abstract: To suppress a change in electrical characteristics and improve reliability in a transistor including an oxide semiconductor film. Provided is a semiconductor device including a transistor including a first gate electrode, a first insulating film over the first gate electrode, a first oxide semiconductor film over the first insulating film, a source electrode electrically connected to the first oxide semiconductor film, a drain electrode electrically connected to the first oxide semiconductor film, a second insulating film over the first oxide semiconductor film, a second oxide semiconductor film as a second gate electrode over the second insulating film, and a third insulating film over the second oxide semiconductor film. The second insulating film includes an excess oxygen region having a concentration gradient.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Masami Jintyou, Daisuke Kurosaki, Takahiro Iguchi, Naoto Goto, Shunpei Yamazaki
  • Patent number: 10002886
    Abstract: Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinori Ando
  • Patent number: 9991352
    Abstract: A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ali Razavieh, Ruilong Xie, Steven Bentley