Field Effect Device In Amorphous Semiconductor Material Patents (Class 257/57)
  • Patent number: 10734529
    Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi
  • Patent number: 10727356
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator. The top surface of the fourth insulator is substantially aligned with the top surface of the third insulator.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10727284
    Abstract: A method of fabricating an organic light-emitting diode (OLED) touch display screen is provided and has steps of forming a thin film transistor (TFT) layer, an OLED layer, and a touch layer on a base substrate sequentially. Compared with prior art, upon fabricating a touch layer, a first insulating layer is not etched after depositing the first insulating layer and before depositing a bridging point layer. After depositing and forming a second insulating layer, the first and second insulating layers are dry-etched together using combination of two etching gases to achieve fabricating two different depths contact holes in the touch layer in a same process, which effectively reduces erosion of the OLED by a wet-etching process, simplifies a producing process, improves device-producing capacity, and simultaneously achieves a pre-protection effect on touch lines and bonding pads in a source-drain electrode layer to avoid functional failure caused by over-etching or oxidation.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 28, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xiaoliang Feng
  • Patent number: 10707210
    Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Fredrick D. Fishburn
  • Patent number: 10692975
    Abstract: A thin-film transistor according to an exemplary embodiment of the present invention comprises an active layer; an intermediate layer; a gate insulating film; a gate electrode; an interlayer insulating film; and source and drain electrodes. The active layer is positioned on a substrate, and the gate insulating film is positioned on the active layer. The gate electrode is positioned on the gate insulating film, and the interlayer insulating film is positioned on the gate electrode. The source and drain electrodes are positioned on the interlayer insulating film and connected to the active layer. The intermediate layer is positioned between the active layer and the gate insulating film, and made of an oxide semiconductor comprising a Group IV element.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 23, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Juheyuck Baeck, Jonguk Bae, Saeroonter Oh, Dohyung Lee, Taeuk Park
  • Patent number: 10690983
    Abstract: A reflective display and a preparation method thereof are disclosed. The reflective display includes: a first substrate and a second substrate, a first electrode provided on the first substrate a transparent dielectric layer provided on a side of the first substrate, which side faces the second substrate, a second electrode provided on the second substrate, and liquid crystal located between the first substrate and the second substrate; a refractive index of the liquid crystal changes under action of an electric field formed by the first electrode and the second electrode so that the refractive index of the liquid crystal is the same as or substantially the same as a refractive index of the transparent dielectric layer, or less than the refractive index of the transparent dielectric layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 23, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pengxia Liang, Xiao Zhang, Xin Gu
  • Patent number: 10692901
    Abstract: An array substrate and a manufacturing method thereof are provided. The manufacturing method includes steps of: providing a first substrate; providing a first mask and arranging active switches on the first substrate; providing a second mask, forming a photoresist layer on the active switches and sequentially performing following steps of: performing a first wet etching on the active switches, performing a first ashing treatment on the photoresist layer, performing a first dry etching on the active switches, performing a second wet etching on the active switches, performing a second ashing treatment on the photoresist layer and performing a second dry etching on the active switches; providing a third mask and forming a protective layer on a metal layer of the active switches; and providing a fourth mask and forming a pixel electrode layer on the protective layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 23, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: En-Tsung Cho
  • Patent number: 10692961
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10685838
    Abstract: Disclosed are a semiconductor structure and a method for forming the same.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Ji Shiliang, Zhang Yiying, Zhang Haiyang
  • Patent number: 10658389
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 10651294
    Abstract: The present invention provides a laser annealing method for irradiating laser light L to an amorphous silicon thin film deposited on a substrate to obtain polysilicon, the method including: multiply irradiating the laser light L while changing an irradiation area of the laser light L on the amorphous silicon thin film to achieve such a grain size distribution that a crystal grain size of the polysilicon decreases from a central portion to a side edge portion at least along a center line C of the irradiation area of the laser light L. The above laser annealing method can reduce a leak current through a simple process.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 12, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10644133
    Abstract: The present invention provides a laser annealing method for irradiating laser light L to an amorphous silicon thin film deposited on a substrate to obtain polysilicon, the method including: multiply irradiating the laser light L while changing an irradiation area of the laser light L on the amorphous silicon thin film to achieve such a grain size distribution that a crystal grain size of the polysilicon decreases from a central portion to a side edge portion at least along a center line C of the irradiation area of the laser light L. The above laser annealing method can reduce a leak current through a simple process.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 5, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10636888
    Abstract: A thin film transistor includes a gate electrode on a substrate. The gate electrode includes a flat portion and an inclined portion at a side of the flat portion. A ratio of a height to a width (height/width) of the inclined portion is 1.192 or less. The thin film transistor also includes a gate insulating layer disposed on the substrate to cover the gate electrode and a polysilicon active layer on the gate insulating layer and over the gate electrode. The thin film transistor further includes a source electrode and a drain electrode respectively connected to two opposite end portions of the polysilicon active layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: April 28, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Kum-Mi Oh, Hye-Seon Eom, Shun-Young Yang, Jeoung-In Lee
  • Patent number: 10629746
    Abstract: The present disclosure discloses an array substrate and manufacturing method thereof. The method includes: forming a gate layer on the surface of a substrate; forming an insulating layer on the surface of the gate layer; forming a polysilicon layer having a separating portion on the surface of the insulating layer; and forming a source drain layer on the surface the polysilicon layer having the separating portion, such that the source drain layer is not directly in contact with the polysilicon layer. Through the above-mentioned method, the contact resistance of the source drain layer and the amorphous silicon layer is effectively improved, thereby effectively reducing the leakage current, and the characteristic of TFT device is greatly improved.
    Type: Grant
    Filed: October 21, 2017
    Date of Patent: April 21, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY Co., LTD.
    Inventor: Wei Yu
  • Patent number: 10622435
    Abstract: A display device of the present disclosure includes: a circuit unit including a semiconductor substrate and a capacitative element, in which the capacitative element includes, a dielectric layer which is formed in the semiconductor substrate, and extends in a substrate depth direction, a first electrode formed on one surface side of the dielectric layer to face the dielectric layer, and a second electrode formed on the other surface side of the dielectric layer to face the dielectric layer. An electronic device of the present disclosure includes the display device having the configuration described above.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 14, 2020
    Assignee: Sony Corporation
    Inventor: Kazuhiro Tamura
  • Patent number: 10600816
    Abstract: The present disclosure provides an array substrate including a substrate, an active layer disposed on the substrate, a conductive layer, a source and a drain. The conductive layer is disposed on two opposite sides of the active layer and is in contact with the active layer, the conductive layer forms a gap on the active layer to expose the partial surface of the active layer, the source and the drain are respectively disposed on the conductive layer on two opposite sides of the active layer. The material of the conductive layer is graphene. A conductive layer of graphene is added between the active layer, the source and the drain form a good conductive between the source and the drain to effectively reduce the contact resistance between the active layer and the source and the drain, thereby effectively improving the on-state current of the electronic device and the carrier mobility.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 24, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 10586842
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10586871
    Abstract: The present disclosure provides a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a gate layer, a source and a drain located on the gate layer, and an active layer located on the source and the drain. The active layer is electrically connected to the source and the drain. The active layer comprises two sides arranged in parallel, and each side forms an acute angle of 45° with a face of the drain facing the source.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 10, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhenhua Lv, Zhiying Bao, Shijun Wang, Yong Zhang, Wenjun Xiao, Jingbo Xu
  • Patent number: 10573553
    Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Abbas Ali, Yaping Chen, Chao Zuo, Seetharaman Sridhar, Yunlong Liu
  • Patent number: 10559782
    Abstract: An organic light emitting display apparatus and a method of manufacturing an organic light emitting display apparatus, the apparatus including a first substrate; an organic light emitting diode on the first substrate, the organic light emitting diode including an emitting area that generates light, and a non-emitting area which generates no light; a second substrate facing the organic light emitting diode; a black matrix layer on a surface of the second substrate that faces the organic light emitting diode, the black matrix layer including an open area aligned with the emitting area of the organic light emitting diode, and a closed area aligned with the non-emitting area of the organic light emitting diode; and a photoresist member, at least a portion of the photoresist member being on the open area of the black matrix layer and protruding toward the organic light emitting diode.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Soyoung Lee
  • Patent number: 10559695
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10541290
    Abstract: A drive circuit, an organic light-emitting diode display, and methods for fabricating the same are provided. The drive circuit includes: a driving transistor, including a first gate, a first semiconductor layer disposed above the first gate, an etch stopping layer disposed on the first semiconductor layer, and a first source and a first drain which are disposed on the two sides of the first semiconductor layer, the first semiconductor layer being made of oxide semiconductor material; and a switching transistor, including a second gate, a second semiconductor layer disposed above the second gate, and a second source and a second drain which are disposed on two sides of the second semiconductor layer, the second semiconductor layer being made of oxide semiconductor material. In the drive circuit, reliability and uniformity of the drive transistors are improved, and parasitic capacitance of the switching transistor decreases.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 21, 2020
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yingteng Zhai, Yong Wu
  • Patent number: 10529864
    Abstract: A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masami Jintyou
  • Patent number: 10522791
    Abstract: This presently disclosed technology relates Organic Light Emitting Diodes (OLEDs), more particularly it relates to OLED display light extraction and nanocomposite formulations that can be used for the light extraction structure.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: PIXELLIGENT TECHNOLOGIES, LLC
    Inventors: Zhiyun Chen, Gregory D. Cooper
  • Patent number: 10515987
    Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 24, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 10504898
    Abstract: A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yin Wang, Chien-Chih Lin, Chien-Tai Chan, Wei-Ken Lin, Chun-Te Li
  • Patent number: 10497572
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming an insulating layer having a first plane in contact with a nitride semiconductor layer and a second plane opposite to the first plane and containing at least one of an oxide and an oxynitride; and performing first heat treatment at 600° C. or more and 1100° C. or less in a state where a voltage making a first plane side positive relative to a second plane side is applied to the insulating layer.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yasutaka Nishida, Toshiya Yonehara
  • Patent number: 10497813
    Abstract: An array substrate, preparation method thereof, display panel and display device are provided. The array substrate includes a base substrate and a plurality of thin film transistors distributed on the base substrate in an array. Each thin film transistor includes: a light-shielding block formed on the base substrate and provided with a first groove of which an opening direction is away from the base substrate; a buffer layer formed on one side of the light-shielding block away from the base substrate, a region of the buffer layer corresponding to the first groove being disposed with a second groove of which an opening direction is away from the base substrate; and a channel layer formed in the second groove. The structure uses bulges on two sides of the first groove to shield the light rays in regions without the thin film transistor, thereby improving the stability of the thin film transistor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 3, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun Liu, Wei Li, Bin Zhou, Tongshang Su, Jingang Fang, Yang Zhang
  • Patent number: 10473990
    Abstract: A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 12, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Si Deng, Yuan Guo
  • Patent number: 10475931
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator. The top surface of the fourth insulator is substantially aligned with the top surface of the third insulator.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10468537
    Abstract: A metal oxide thin-film transistor and manufacturing for the same are provided. The thin-film transistor includes a substrate; a source electrode, a barrier layer and a drain electrode which are sequentially formed on the substrate; and a semiconductor active layer formed on side surfaces of the source electrode and the drain electrode. The semiconductor active layer is connected with the source electrode and the drain electrode. The metal oxide thin-film transistor has a new structure, in which the source and drain electrodes are parallel to the substrate, and the semiconductor active layer is contacted with the source electrode and the drain electrode by a vertical covering or a step covering way. The channel length does not depend on the photolithography process, but depends on the side length of the source and drain electrodes contacted with the semiconductor active layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 5, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yang Liu
  • Patent number: 10451909
    Abstract: A liquid crystal display panel including a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate includes a first base substrate, a thin film transistor disposed on the first base substrate, a color filter disposed on the first base substrate, and a first alignment layer disposed on the thin film transistor and the color filter. The second substrate includes a second base substrate, a second alignment layer disposed on a first surface of the second base substrate, a touch electrode disposed on a second surface of the second base substrate, a connecting electrode disposed on the second surface, and a connecting line disposed on the second surface. The first surface faces the first substrate, and the second surface is opposite to the first surface. The touch electrode includes a crystallized indium tin oxide.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: October 22, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seong Mo Hwang, Jin Woo Park
  • Patent number: 10446668
    Abstract: To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first to a third oxide semiconductor layers are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first and the third oxide semiconductor layers are each an amorphous semiconductor film. The second oxide semiconductor layer is a crystalline semiconductor film.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: October 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10435506
    Abstract: The present invention relates to thiadiazolopyridine polymers, their synthesis and their use. The present invention further relates to organic electronic devices comprising such thiadiazolopyridine polymers.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 8, 2019
    Assignee: MERCK PATENT GMBH
    Inventors: William Mitchell, Mansoor D'Lavari
  • Patent number: 10439072
    Abstract: Stable electrical characteristics and high reliability are provided for a semiconductor device including an oxide semiconductor. In a transistor including an oxide semiconductor layer, a buffer layer containing a constituent similar to that of the oxide semiconductor layer is provided in contact with a top surface and a bottom surface of the oxide semiconductor layer. Such a transistor and a semiconductor device including the transistor are provided. As the buffer layer in contact with the oxide semiconductor layer, a film containing an oxide of one or more elements selected from aluminum, gallium, zirconium, hafnium, and a rare earth element can be used.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10411102
    Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Daisuke Kawae
  • Patent number: 10396096
    Abstract: A transistor array panel includes a transistor which includes a gate electrode, a semiconductor layer on the gate electrode, and a source electrode and a drain electrode on the semiconductor layer. The semiconductor layer includes a first portion overlapping the source electrode, a second portion overlapping the drain electrode, and a third portion between the first portion and the second portion. The first portion, the second portion, and the third portion have different minimum thicknesses.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae Gyun Kim, Jae-Yong Ka, Pil Soon Hong
  • Patent number: 10381600
    Abstract: An organic electroluminescence device includes a base material including a recessed portion on one face side, and a light emitting element. The light emitting layer including a reflective layer disposed at least on a surface of the recessed portion, a filling layer that has optical transparency and is filled and disposed in the recessed portion with the reflective layer interposed between the recessed portion and the filling layer, a first electrode that has optical transparency and is disposed at least on an upper-layer side of the filling layer, an organic layer that includes at least a light emitting layer and is disposed on an upper layer of the first electrode, and a second electrode that has optical transparency and is disposed on an upper-layer side of the organic layer. The organic electroluminescence device includes a display region divided into a plurality of unit regions separated from each other. The unit regions each has a light emitting area and a non emissive area that are partitioned.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Uchida, Katsuhiro Kikuchi, Yoshiyuki Isomura, Eiji Koike, Satoshi Inoue, Yuto Tsukamoto, Masanori Ohara, Asae Ito
  • Patent number: 10373980
    Abstract: To provide a display device including a transistor that includes an oxide semiconductor and has favorable characteristics, a pixel electrode electrically connected to the transistor, and a capacitor electrically connected to the pixel electrode. To provide a display device that can be manufactured at low cost. The display device includes a display element including a pixel electrode, a transistor that performs switching of the display element and includes a first oxide semiconductor layer serving as a channel formation region, a capacitor that is electrically connected to the display element and includes a dielectric layer between a pair of electrodes. The pixel electrode is a second oxide semiconductor layer formed on the same surface as that on which the first oxide semiconductor layer is formed, and also serves as one electrode of the capacitor.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Shunpei Yamazaki
  • Patent number: 10361242
    Abstract: A solid-state imaging device includes a sensor including an impurity diffusion layer provided in a surface layer of a semiconductor substrate; and an oxide insulating film containing carbon, the oxide insulating film being provided on the sensor.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Sony Corporation
    Inventors: Itaru Oshiyama, Yuki Miyanami, Susumu Hiyama, Kazuki Tanaka
  • Patent number: 10324050
    Abstract: Methods and systems for optimizing measurement system parameter settings of an x-ray based metrology system are presented. X-ray based metrology systems employing an optimized set of measurement system parameters are used to measure structural, material, and process characteristics associated with different semiconductor fabrication processes with greater precision and accuracy. In one aspect, a set of values of one or more machine parameters that specify a measurement scenario is refined based at least in part on a sensitivity of measurement data to a previous set of values of the one or more machine parameters. The refinement of the values of the machine parameters is performed to maximize precision, maximize accuracy, minimize correlation between parameters of interest, or any combination thereof. Refinement of the machine parameter values that specify a measurement scenario can be used to optimize the measurement recipe to reduce measurement time and increase measurement precision and accuracy.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 18, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: John J. Hench, Andrei V. Shchegrov, Michael S. Bakeman
  • Patent number: 10319883
    Abstract: A semiconductor device includes a substrate, a gate electrode, an oxide semiconductor film, a first electrode, a second electrode, and a third electrode. The gate electrode is provided on the substrate. The oxide semiconductor film is provided on the substrate with the gate electrode interposed therebetween. The oxide semiconductor film includes a channel region facing the gate electrode and a low-resistance region adjacent to the channel region. The first electrode contains a constituent material same as that of the gate electrode, and has same thickness as that of the gate electrode. The second electrode has at least a portion facing the first electrode, and contains a constituent material same as that of the oxide semiconductor film. The third electrode has at least a portion provided at a position facing the first electrode with the second electrode interposed therebetween. The third electrode is electrically coupled to the first electrode.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: June 11, 2019
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Motohiro Toyota
  • Patent number: 10312388
    Abstract: Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 4, 2019
    Assignees: Micron Technology, Inc., Massachusetts Institute of Technology
    Inventors: Roy Meade, Karan Mehta, Efraim Megged, Jason Orcutt, Milos Popovic, Rajeev Ram, Jeffrey Shainline, Zvi Sternberg, Vladimir Stojanovic, Ofer Tehar-Zahav
  • Patent number: 10303277
    Abstract: There is provided a flat panel display device and a method of manufacturing the same. A flexible and transparent material is coated on a supporting substrate to a small thickness so that film substrates are easily formed. Step differences are formed in the film substrates so that a distance between pads of the two film substrates is reduced. Since conductive balls with reduced diameters are used so that the pads may be electrically connected, the distance between pads is reduced so that it is possible to easily miniaturize a high resolution flat panel display device, to prevent electrical connection defect between the pads, and to reduce manufacturing expenses.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung Ho Choi
  • Patent number: 10304984
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10297651
    Abstract: A drive circuit, an organic light-emitting diode display, and methods for fabricating the same are provided. The drive circuit includes: a driving transistor, including a first gate, a first semiconductor layer disposed above the first gate, an etch stopping layer disposed on the first semiconductor layer, and a first source and a first drain which are disposed on the two sides of the first semiconductor layer, the first semiconductor layer being made of oxide semiconductor material; and a switching transistor, including a second gate, a second semiconductor layer disposed above the second gate, and a second source and a second drain which are disposed on two sides of the second semiconductor layer, the second semiconductor layer being made of oxide semiconductor material. In the drive circuit, reliability and uniformity of the drive transistors are improved, and parasitic capacitance of the switching transistor decreases.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 21, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yingteng Zhai, Yong Wu
  • Patent number: 10290720
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Hiroshi Fujiki, Hiromichi Godo, Yasumasa Yamane
  • Patent number: 10283579
    Abstract: There is provided a semiconductor device that includes a substrate, an electric field shielding layer, and a semiconductor element. The electric field shielding layer is provided on the substrate. The semiconductor element includes an electrode, and is provided on the electric field shielding layer with an insulating film in between.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 7, 2019
    Assignee: JOLED, Inc.
    Inventors: Yuichiro Ishiyama, Yuichi Kato, Tomoatsu Kinoshita, Takashige Fujimori, Kenta Masuda, Keiichi Akamatsu
  • Patent number: 10268093
    Abstract: The present invention discloses an array substrate, which comprises a substrate; a gate line and a gate connected to the gate line on the substrate; a first insulating layer covering the gate line and the gate; an active layer on the first insulating layer; an organic layer on the first insulating layer, which exposes the active layer; a source, a drain, and a data line connected with the source on the organic layer, the source and the drain being respectively connected with the active layer, the data line and the gate line being overlapped; a second insulating layer covering the source, the drain, the data line, and the active layer; a contact hole in the second insulating layer, the contact hole exposing the drain; and a pixel electrode on the second insulating layer, the pixel electrode being contacted with the drain through the contact hole.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Liang Xu
  • Patent number: 10263118
    Abstract: A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki