Field Effect Device In Amorphous Semiconductor Material Patents (Class 257/57)
  • Patent number: 11004875
    Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 11, 2021
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Catherine Ramsdale, Brian Hardy Cobb, Feras Alkhalil
  • Patent number: 10991827
    Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 27, 2021
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yutong Hu, Chihyuan Tseng, Chihyu Su, Wenhui Li, Xiaowen Lv, Longqiang Shi, Hejing Zhang
  • Patent number: 10968522
    Abstract: The disclosure provides a method for fabricating a metallic optical metasurface having an array of hologram elements. The method includes forming a first copper layer protected with a conducting or dielectric barrier layer over a backplane structure by a damascene process. The first copper layer comprises a plurality of nano-gaps vertically extending from the backplane structure. The plurality of nano-gaps is filled with a dielectric material. The method also includes removing the dielectric material and a portion of the conducting or dielectric barrier layer to expose the portions in the nano-gaps of the first copper layer. The method may further include depositing a dielectric coating layer over the top portion and exposed side portions of the first copper layer to form a protected first copper layer, and filling the gaps with an electrically-tunable dielectric material that has an electrically-tunable refractive index.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 6, 2021
    Assignee: Elwha LLC
    Inventors: Gleb M. Akselrod, Erik Edward Josberger, Mark C. Weidman
  • Patent number: 10971491
    Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Yutaka Okazaki
  • Patent number: 10964838
    Abstract: The present disclosure discloses a display substrate, a manufacturing method thereof, a display panel, and a display device. The display substrate includes a base substrate, a black matrix disposed on the base substrate, and a switching unit and an optical detection unit that are disposed at a side of the black matrix away from the base substrate. The optical detection unit is electrically connected to the switching unit, and an orthographic projection of at least one of the switching unit and the optical detection unit on the base substrate is located in an orthographic projection of the black matrix on the base substrate. Since the orthographic projection of at least one of the switching unit and the optical detection unit on the base substrate is located in the orthographic projection of the black matrix on the base substrate, the aperture ratio of the display substrate may increase.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 10930792
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10930723
    Abstract: A display device is disclosed. The display device according to an exemplary embodiment of the present disclosure includes: a substrate including an active area and a non-active area; an active layer, a thin film transistor including a gate electrode, a source electrode, and a drain electrode disposed on the substrate; and an organic light emitting diode including an anode which is electrically connected to the thin film transistor, in which the gate electrode, the source electrode, and the drain electrode are formed of a first conductive layer and a second conductive layer on the first conductive layer and the anode is formed of the same material as the first conductive layer. Therefore, the anode and the first conductive layer of the drain electrode are integrally connected so that a separate contact hole for electrically connecting the anode and the drain electrode is not necessary and the structure may be simplified.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 23, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: JongSik Shim, SeongHwan Hwang, KilHwan Oh
  • Patent number: 10930788
    Abstract: A display panel includes a base substrate, and thin film transistors positioned on the base substrate. Each thin film transistor includes a polysilicon layer. The display panel further includes a light-shielding layer for blocking ultraviolet (UV) light that is located at a side of the polysilicon layer away from the base substrate. An orthographic projection of the polysilicon layer on the substrate is in a range of an orthographic projection of the light-shielding layer on the substrate.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 23, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qi Yao, Zhanfeng Cao, Feng Zhang, Haixu Li, Shengguang Ban, Zhiyong Liu
  • Patent number: 10908444
    Abstract: [Object] To provide a display device, a method for producing a display device, and a display apparatus of projection type, which are capable of suppressing deterioration of image quality attributable to a depressed space between pixel electrodes. [Solving Means] A display device of the present disclosure includes pixel electrodes formed for individual pixels and an insulating film for insulation between the pixel electrodes. The insulating film is so formed as to protrude from an electrode surface between the pixel electrodes. A display apparatus of projection type of the present disclosure uses the display device of the present disclosure as a light modulator to module light from a light source. A method for producing a display device of the present disclosure having pixel electrodes formed for individual pixels and an insulating film for insulation between the pixel electrodes includes forming the insulating film as to protrude between the pixel electrodes.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 2, 2021
    Assignee: SONY CORPORATION
    Inventors: Takashi Sakairi, Koichi Amari, Chiho Araki, Hitori Tanigawa, Katsumi Kouno, Keiichi Maeda, Takayoshi Masaki, Seiya Haraguchi
  • Patent number: 10910413
    Abstract: The present disclosure provides a method of manufacturing array substrate, including: providing a substrate; and forming a metal layer, a gate layer, an insulation layer, and a protective layer on the substrate sequentially. Wherein, the metal layer is formed on a drive line on the substrate, and the metal layer is arranged in at least one of a position between the substrate and the insulation layer and a position between the insulation layer and the protective layer. In the present disclosure, an electrostatic discharge path is increased through the floating metal layer. Even though the floating metal layer is burned down, a display quality would not be affected, the product yield is improved. Besides, it only needs to adjust a photomask pattern. Therefore, a production procedure needs not to be adjusted.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 2, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chuan Wu
  • Patent number: 10903206
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Patent number: 10879328
    Abstract: The present disclosure relates to a thin film transistor (TFT) substrate, a manufacturing method thereof, and an organic light-emitting (OLED) substrate. The interlayer dielectric layer manufactured by the manufacturing method may be configured in the structure of two silicon oxide layers sandwiching one silicon nitride layer. As such, the bonding force between the interlayer dielectric layer and the gate, and the bonding force between the interlayer dielectric layer, and the source and the drain may be improved. The source and the drain may be prevented from falling off from the interlayer dielectric layer during the annealing process. Production yield of the TFT substrate may be improved. The OLED substrate adopting the manufactured of the OLED substrate of the present disclosure may have a better production yield and quality.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: December 29, 2020
    Assignees: WUHAN CHINA STAR OPTOELECTRONICS, SEMICONDUCTOR DISPLAY TECHNOLOGY CO.. LTD.
    Inventors: Lei Yu, Songshan Li
  • Patent number: 10854704
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10826481
    Abstract: A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Masashi Hayashiguchi, Kazuhide Ino
  • Patent number: 10811631
    Abstract: The thin film transistor element substrate of the present disclosure includes a first moisture barrier layer covering the gate insulating layer and the gate electrode, covering the contact regions of the oxide semiconductor layer other than the connecting portion of the contact region connected to the source electrode and the connecting portion of the contact region connected to the drain electrode, and covering an surface of the substrate on which the oxide semiconductor layer is not disposed. The first moisture barrier layer includes a metal oxide and is formed by atomic layer deposition. The first moisture barrier layer formed by atomic layer deposition is in contact with a pair of contact regions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 20, 2020
    Assignee: PANASONIC CORPORATION
    Inventor: Arinobu Kanegae
  • Patent number: 10802630
    Abstract: The disclosure discloses an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: a base substrate, a pressure-sensitive component, a plurality of dual-gate transistors, and a plurality of pixel transistors, where the pressure-sensitive component includes a first electrode layer, a pressure-sensitive layer, and a second electrode layer which are arranged on the base substrate in that order, and the second electrode layer includes a plurality of second electrodes arranged corresponding to the respective dual-gate transistors in a one-to-one manner; and the dual-gate transistors and the pixel transistors are arranged above the second electrode layer, and each of the plurality of second electrodes is electrically connected with a bottom-gate electrode in a corresponding dual-gate transistor, so that a pressure can be detected.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: October 13, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Yuzhen Guo, Xue Dong, Haisheng Wang, Chun-wei Wu, Xueyou Cao, Yingming Liu, Xiaoliang Ding, Chih-Jen Cheng
  • Patent number: 10783966
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
  • Patent number: 10782580
    Abstract: An array substrate includes a first substrate, a source electrode disposed on the first substrate, a semiconductor pattern layer disposed on the source electrode, a drain electrode disposed on the semiconductor pattern layer, a pixel electrode disposed on the drain electrode and a gate electrode disposed on at least one side surface of the semiconductor pattern layer. A method of making the solar panel is provided. A method of making the array substrate is provided.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: September 22, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Hun Noh, Keun Kyu Song, Hyun Sup Lee
  • Patent number: 10777662
    Abstract: The present disclosure provides a manufacturing method of a thin film transistor, including: selecting a substrate, and forming a bottom gate, a gate insulating layer and a source-drain above the selected substrate, wherein the bottom gate and the source-drain adopts a conductive metal oxide with an adjustable work function as a metal conducting electrode; rinsing and drying the source-drain of the selected substrate, and ozone cleaning dried source-drain for a predetermined time under a predetermined illumination condition, bombarding the source-drain with oxygen plasma for a period of time, forming an active layer made of a carbon material over the source-drain; forming a passivation layer over the active layer. The implementation of the disclosure can reduce the contact resistance and improve the performance of the carbon-based thin film transistor device by adjusting the work function of the contact surface between the conductive metal and the active layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: September 15, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 10770274
    Abstract: A copper alloy sputtering target is formed by a copper alloy including the content of Ca being 0.3 to 1.7% by mass, the total content of Mg and Al being 5 ppm or less by mass, the content of oxygen being 20 ppm or less by mass, and the remainder is Cu and inevitable impurities. A manufacturing method of a copper alloy sputtering target comprises steps of: preparing a copper having purity of 99.99% or more by mass; melting the copper so as to obtain a molten copper; controlling components so as to obtain a molten metal having a predetermined component composition by the addition of Ca having a purity of 98.5% or more by mass into the molten copper and by melting the Ca; casting the molten metal so as to obtain an ingot; and performing stress relieving annealing after performing hot rolling to the ingot.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 8, 2020
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Satoru Mori, Toshio Sakamoto, Kiyoyuki Ookubo
  • Patent number: 10756444
    Abstract: A liquid crystal panel included in a scanning antenna includes: a TFT substrate including a first dielectric substrate, a TFT supported by the first dielectric substrate, a gate bus line, a source bus line, a patch electrode, and a first alignment film covering the patch electrode; a slot substrate including a second dielectric substrate, a slot electrode formed on a first main surface of the second dielectric substrate and including a slot disposed corresponding to the patch electrode, and a second alignment film covering the slot electrode; and a liquid crystal layer provided between the TFT substrate and the slot substrate and containing a liquid crystal molecule including an isothiocyanate group. The first alignment film and the second alignment film are each independently formed of a polyimide-based alignment film material.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masanobu Mizusaki, Jumpei Takahashi, Hiroshi Tsuchiya
  • Patent number: 10755945
    Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 10749000
    Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Seunghan Seo, Yeohyun Sung
  • Patent number: 10749015
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 10741697
    Abstract: A thin film transistor is provided. The thin film transistor includes an oxide semiconductor layer on a substrate, a gate electrode insulated from the oxide semiconductor layer to overlap at least a portion of the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode spaced apart from the source electrode and connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first oxide semiconductor layer on the substrate and a second oxide semiconductor layer on the first oxide semiconductor layer, the first oxide semiconductor layer includes nitrogen of 1 at % to 5 at % concentration with respect to number of atoms, and the second oxide semiconductor layer has a nitrogen concentration which is lower than a nitrogen concentration of the first oxide semiconductor layer and a gradient of the nitrogen concentration such that the nitrogen concentration is lowered in a direction closer to the gate electrode.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jiyong Noh, Jaeman Jang, JuHeyuck Baeck, PilSang Yun
  • Patent number: 10741693
    Abstract: A thin film transistor includes a gate electrode, an active layer formed of oxide semiconductor material on a substrate, and a gate insulation layer therebetween. The active layer includes a channel region corresponding to the gate electrode, a source region at one side of the channel region, and a drain region at the other side of the channel region. The source region includes a first upper portion and the drain region includes a second upper portion that includes the oxide semiconductor material and Si.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Ju-Heyuck Baeck
  • Patent number: 10734529
    Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi
  • Patent number: 10727284
    Abstract: A method of fabricating an organic light-emitting diode (OLED) touch display screen is provided and has steps of forming a thin film transistor (TFT) layer, an OLED layer, and a touch layer on a base substrate sequentially. Compared with prior art, upon fabricating a touch layer, a first insulating layer is not etched after depositing the first insulating layer and before depositing a bridging point layer. After depositing and forming a second insulating layer, the first and second insulating layers are dry-etched together using combination of two etching gases to achieve fabricating two different depths contact holes in the touch layer in a same process, which effectively reduces erosion of the OLED by a wet-etching process, simplifies a producing process, improves device-producing capacity, and simultaneously achieves a pre-protection effect on touch lines and bonding pads in a source-drain electrode layer to avoid functional failure caused by over-etching or oxidation.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 28, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xiaoliang Feng
  • Patent number: 10727356
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator. The top surface of the fourth insulator is substantially aligned with the top surface of the third insulator.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10707210
    Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Fredrick D. Fishburn
  • Patent number: 10692975
    Abstract: A thin-film transistor according to an exemplary embodiment of the present invention comprises an active layer; an intermediate layer; a gate insulating film; a gate electrode; an interlayer insulating film; and source and drain electrodes. The active layer is positioned on a substrate, and the gate insulating film is positioned on the active layer. The gate electrode is positioned on the gate insulating film, and the interlayer insulating film is positioned on the gate electrode. The source and drain electrodes are positioned on the interlayer insulating film and connected to the active layer. The intermediate layer is positioned between the active layer and the gate insulating film, and made of an oxide semiconductor comprising a Group IV element.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 23, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Juheyuck Baeck, Jonguk Bae, Saeroonter Oh, Dohyung Lee, Taeuk Park
  • Patent number: 10692961
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10692901
    Abstract: An array substrate and a manufacturing method thereof are provided. The manufacturing method includes steps of: providing a first substrate; providing a first mask and arranging active switches on the first substrate; providing a second mask, forming a photoresist layer on the active switches and sequentially performing following steps of: performing a first wet etching on the active switches, performing a first ashing treatment on the photoresist layer, performing a first dry etching on the active switches, performing a second wet etching on the active switches, performing a second ashing treatment on the photoresist layer and performing a second dry etching on the active switches; providing a third mask and forming a protective layer on a metal layer of the active switches; and providing a fourth mask and forming a pixel electrode layer on the protective layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 23, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: En-Tsung Cho
  • Patent number: 10690983
    Abstract: A reflective display and a preparation method thereof are disclosed. The reflective display includes: a first substrate and a second substrate, a first electrode provided on the first substrate a transparent dielectric layer provided on a side of the first substrate, which side faces the second substrate, a second electrode provided on the second substrate, and liquid crystal located between the first substrate and the second substrate; a refractive index of the liquid crystal changes under action of an electric field formed by the first electrode and the second electrode so that the refractive index of the liquid crystal is the same as or substantially the same as a refractive index of the transparent dielectric layer, or less than the refractive index of the transparent dielectric layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 23, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pengxia Liang, Xiao Zhang, Xin Gu
  • Patent number: 10685838
    Abstract: Disclosed are a semiconductor structure and a method for forming the same.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Ji Shiliang, Zhang Yiying, Zhang Haiyang
  • Patent number: 10658389
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 10651294
    Abstract: The present invention provides a laser annealing method for irradiating laser light L to an amorphous silicon thin film deposited on a substrate to obtain polysilicon, the method including: multiply irradiating the laser light L while changing an irradiation area of the laser light L on the amorphous silicon thin film to achieve such a grain size distribution that a crystal grain size of the polysilicon decreases from a central portion to a side edge portion at least along a center line C of the irradiation area of the laser light L. The above laser annealing method can reduce a leak current through a simple process.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 12, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10644133
    Abstract: The present invention provides a laser annealing method for irradiating laser light L to an amorphous silicon thin film deposited on a substrate to obtain polysilicon, the method including: multiply irradiating the laser light L while changing an irradiation area of the laser light L on the amorphous silicon thin film to achieve such a grain size distribution that a crystal grain size of the polysilicon decreases from a central portion to a side edge portion at least along a center line C of the irradiation area of the laser light L. The above laser annealing method can reduce a leak current through a simple process.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 5, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10636888
    Abstract: A thin film transistor includes a gate electrode on a substrate. The gate electrode includes a flat portion and an inclined portion at a side of the flat portion. A ratio of a height to a width (height/width) of the inclined portion is 1.192 or less. The thin film transistor also includes a gate insulating layer disposed on the substrate to cover the gate electrode and a polysilicon active layer on the gate insulating layer and over the gate electrode. The thin film transistor further includes a source electrode and a drain electrode respectively connected to two opposite end portions of the polysilicon active layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: April 28, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Kum-Mi Oh, Hye-Seon Eom, Shun-Young Yang, Jeoung-In Lee
  • Patent number: 10629746
    Abstract: The present disclosure discloses an array substrate and manufacturing method thereof. The method includes: forming a gate layer on the surface of a substrate; forming an insulating layer on the surface of the gate layer; forming a polysilicon layer having a separating portion on the surface of the insulating layer; and forming a source drain layer on the surface the polysilicon layer having the separating portion, such that the source drain layer is not directly in contact with the polysilicon layer. Through the above-mentioned method, the contact resistance of the source drain layer and the amorphous silicon layer is effectively improved, thereby effectively reducing the leakage current, and the characteristic of TFT device is greatly improved.
    Type: Grant
    Filed: October 21, 2017
    Date of Patent: April 21, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY Co., LTD.
    Inventor: Wei Yu
  • Patent number: 10622435
    Abstract: A display device of the present disclosure includes: a circuit unit including a semiconductor substrate and a capacitative element, in which the capacitative element includes, a dielectric layer which is formed in the semiconductor substrate, and extends in a substrate depth direction, a first electrode formed on one surface side of the dielectric layer to face the dielectric layer, and a second electrode formed on the other surface side of the dielectric layer to face the dielectric layer. An electronic device of the present disclosure includes the display device having the configuration described above.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 14, 2020
    Assignee: Sony Corporation
    Inventor: Kazuhiro Tamura
  • Patent number: 10600816
    Abstract: The present disclosure provides an array substrate including a substrate, an active layer disposed on the substrate, a conductive layer, a source and a drain. The conductive layer is disposed on two opposite sides of the active layer and is in contact with the active layer, the conductive layer forms a gap on the active layer to expose the partial surface of the active layer, the source and the drain are respectively disposed on the conductive layer on two opposite sides of the active layer. The material of the conductive layer is graphene. A conductive layer of graphene is added between the active layer, the source and the drain form a good conductive between the source and the drain to effectively reduce the contact resistance between the active layer and the source and the drain, thereby effectively improving the on-state current of the electronic device and the carrier mobility.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 24, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 10586871
    Abstract: The present disclosure provides a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a gate layer, a source and a drain located on the gate layer, and an active layer located on the source and the drain. The active layer is electrically connected to the source and the drain. The active layer comprises two sides arranged in parallel, and each side forms an acute angle of 45° with a face of the drain facing the source.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 10, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhenhua Lv, Zhiying Bao, Shijun Wang, Yong Zhang, Wenjun Xiao, Jingbo Xu
  • Patent number: 10586842
    Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mizuki Sato
  • Patent number: 10573553
    Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Abbas Ali, Yaping Chen, Chao Zuo, Seetharaman Sridhar, Yunlong Liu
  • Patent number: 10559782
    Abstract: An organic light emitting display apparatus and a method of manufacturing an organic light emitting display apparatus, the apparatus including a first substrate; an organic light emitting diode on the first substrate, the organic light emitting diode including an emitting area that generates light, and a non-emitting area which generates no light; a second substrate facing the organic light emitting diode; a black matrix layer on a surface of the second substrate that faces the organic light emitting diode, the black matrix layer including an open area aligned with the emitting area of the organic light emitting diode, and a closed area aligned with the non-emitting area of the organic light emitting diode; and a photoresist member, at least a portion of the photoresist member being on the open area of the black matrix layer and protruding toward the organic light emitting diode.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Soyoung Lee
  • Patent number: 10559695
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10541290
    Abstract: A drive circuit, an organic light-emitting diode display, and methods for fabricating the same are provided. The drive circuit includes: a driving transistor, including a first gate, a first semiconductor layer disposed above the first gate, an etch stopping layer disposed on the first semiconductor layer, and a first source and a first drain which are disposed on the two sides of the first semiconductor layer, the first semiconductor layer being made of oxide semiconductor material; and a switching transistor, including a second gate, a second semiconductor layer disposed above the second gate, and a second source and a second drain which are disposed on two sides of the second semiconductor layer, the second semiconductor layer being made of oxide semiconductor material. In the drive circuit, reliability and uniformity of the drive transistors are improved, and parasitic capacitance of the switching transistor decreases.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 21, 2020
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yingteng Zhai, Yong Wu
  • Patent number: 10529864
    Abstract: A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masami Jintyou
  • Patent number: 10522791
    Abstract: This presently disclosed technology relates Organic Light Emitting Diodes (OLEDs), more particularly it relates to OLED display light extraction and nanocomposite formulations that can be used for the light extraction structure.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: PIXELLIGENT TECHNOLOGIES, LLC
    Inventors: Zhiyun Chen, Gregory D. Cooper