Amorphous Semiconductor Material Patents (Class 257/52)
  • Patent number: 10685967
    Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
  • Patent number: 10651079
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING CO., LTD.
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10644231
    Abstract: A method for fabricating a memory device includes forming a resistance switching element over a bottom electrode; forming a top electrode over the resistance switching element; forming a first spacer covering a sidewall of the resistance switching element; forming a second spacer surrounding the first spacer and exposing the top electrode; and forming a metallization pattern connected with the top electrode and the second spacer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 10622351
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 10566196
    Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 18, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Osamu Ishikawa, Kenji Meguro, Taishi Wakabayashi, Hiroyuki Oonishi
  • Patent number: 10468295
    Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 5, 2019
    Assignee: GLOBALWAFERS CO. LTD.
    Inventors: Jeffery L. Libbert, Qingmin Liu, Gang Wang, Andrew M. Jones
  • Patent number: 10453944
    Abstract: Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, a display panel including the oxide TFT, and a display device including the display panel, in which a crystalline oxide semiconductor is provided on a metal insulation layer including metal through a metal organic chemical vapor deposition (MOCVD) process. The oxide TFT includes a metal insulation layer including metal, a crystalline oxide semiconductor adjacent to the metal insulation layer, a gate including metal, a gate insulation layer between the crystalline oxide semiconductor and the gate, a first conductor in one end of the crystalline oxide semiconductor, and a second conductor in another end of the crystalline oxide semiconductor.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 22, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Jaeyoon Park, SeHee Park, HyungJoon Koo, Kwanghwan Ji, PilSang Yun
  • Patent number: 10446635
    Abstract: A display device includes a substrate which includes a display area and a non-display area, a pixel unit which is provided in the display area and includes a plurality of pixel columns, and data lines which are respectively connected to the pixel columns and apply data signals to the pixel columns. The non-display area includes a fanout area, a bent area, and a pad area which are sequentially arranged. The respective data lines are disposed on different layers in the fanout area and the pad area. A resulting display device can reduce resistance deviation between data signals in a first data line and a second data line, thereby reducing vertical line defects.
    Type: Grant
    Filed: September 24, 2017
    Date of Patent: October 15, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joong Soo Moon, Sun Ja Kwon, Min Woo Byun, Seung Yeon Cho
  • Patent number: 10388538
    Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideyuki Kishida
  • Patent number: 10224215
    Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideyuki Kishida
  • Patent number: 10177276
    Abstract: There is provided a Group III nitride semiconductor light-emitting device exhibiting improved crystallinity while suppressing abnormal growth of semiconductor layer due to pits and a production method therefor. In forming an n-side electrostatic breakdown preventing layer, pits are generated from the n-side electrostatic breakdown preventing layer. In forming an n-side superlattice layer, the layer is formed by alternately depositing a first InGaN layer and a GaN layer having an In composition ratio lower than that of the first InGaN layer, so that the In composition ratio and the total thickness of the first InGaN layers satisfy the following equation: 0<Y?180X+22, 0<X?0.1, X: In composition ratio of InGaN layers, and Y: Total thickness of InGaN layers (nm).
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: January 8, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Kengo Nagata, Taiji Yamamoto
  • Patent number: 10074816
    Abstract: The present disclosure provides a substrate structure for an electronic element, which includes a supporting carrier; a release layer having a first microstructure on a surface thereof, and the release layer having first adhesion to the supporting carrier; and a flexible substrate for disposing the supporting carrier and the release layer thereon, wherein the flexible substrate has second adhesion to the release layer, the first adhesion is greater than the second adhesion, and the surface of the flexible substrate in contact with the surface of the release layer has a second microstructure opposing to the first microstructure. The present disclosure further provides a method for fabricating the substrate structure.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 11, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Yueh-Chuan Huang, Chyi-Ming Leu
  • Patent number: 10026846
    Abstract: A display substrate and a fabrication method thereof and a display device. The display substrate includes: a plurality of pixels disposed on a lower substrate; and a pixel defining layer disposed between adjacent pixels of the plurality of pixels, the pixel defining layer contacting with an upper substrate of the plurality of pixels, the pixel defining layer configured for defining each pixel and supporting a gap between the upper substrate and the lower substrate.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 17, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yuedong Shang, Wenbin Yang
  • Patent number: 9911757
    Abstract: Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a first source electrode and a first drain electrode over the first oxide semiconductor film; a second insulating film over the first oxide semiconductor film, the first source electrode, and the first drain electrode; and a second gate electrode over the second insulating film.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Kenichi Okazaki, Yasuharu Hosaka, Yukinori Shima
  • Patent number: 9899227
    Abstract: A system and method of ion milling performed in a plasma etch system including a plasma etch chamber, multiple process gas sources coupled to the plasma etch chamber, a radio frequency bias source and a controller. The plasma etch chamber including a substrate support. The substrate support being a non-pivoting and non-rotating substrate support. The substrate support capable of supporting a substrate to be processed on a top surface of the substrate support without use of a mechanical clamp device. The plasma etch chamber also including an upper electrode disposed opposite from the top surface of the substrate support. The radio frequency bias source is coupled to the substrate support. The controller is coupled to the plasma etch chamber, the multiple process gas sources and the radio frequency bias source. The controller including logic stored on computer readable media for performing an ion milling process in the plasma etch chamber.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: February 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Butsurin Jinnai, Jun Hee Han, Aaron Eppler
  • Patent number: 9842893
    Abstract: An organic light emitting display apparatus includes a base substrate, an active pattern disposed on the base substrate, a data line disposed on the base substrate, and a driving voltage line disposed on the base substrate. The active pattern includes a first transistor including a source area, a drain area and a channel. The active pattern also includes a first capacitor area and a second capacitor area. The data line extends in a first direction. The data line is overlapped with the first capacitor area. The driving voltage line extends in a second direction substantially perpendicular to the first direction. The driving voltage line is overlapped with the second capacitor area.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: December 12, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-Ja Kwon, Ji-Eun Lee
  • Patent number: 9837441
    Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Toshinari Sasaki, Miyuki Hosoba
  • Patent number: 9780103
    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer
  • Patent number: 9773588
    Abstract: A chip part is provided that includes a substrate 2 in which an element region 5 and an electrode region 16 are set, an insulating film (a first insulating film 9 and a second insulating film 3) which is formed on the substrate 2 and which selectively includes an internal concave/convex structure 18 in the electrode region 16 on a surface, a first connection electrode 3 and a second connection electrode 4 which include, at a bottom portion, an anchor portion 24 entering the concave portion 17 of the internal concave/convex structure 18 and which include an external concave/convex structure 6, 7 on a surface on the opposite side and a circuit element which is disposed in the element region 5 and which is electrically connected to the first connection electrode 3 and the second connection electrode 4.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 26, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Takuma Shimoichi, Yasuhiro Kondo, Keishi Watanabe, Takamichi Torii, Katsuya Matsuura
  • Patent number: 9761529
    Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9711654
    Abstract: A display device including: a first base substrate including a display area and a non-display area adjacent to the display area; a plurality of signal lines disposed in the display area; a plurality of pixels disposed in the display area and connected to the signal lines; and a driving circuit disposed in the non-display area and configured to provide driving signals to the signal lines. Each of the pixels includes a switching transistor connected to a corresponding signal line, and a display element connected to the switching transistor.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: July 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Moojong Kim
  • Patent number: 9685460
    Abstract: The present disclosure provides an array substrate, its manufacturing method and a display device. The method includes forming a source electrode and a drain electrode of a thin film transistor, an active layer and a first transparent electrode in the array substrate by a masking step. The active layer and the first transparent electrode are formed by an identical metal oxide layer, and the source electrode and the drain electrode are arranged above the active layer. The first transparent electrode corresponds to a first semi-transparent region of a mask, a channel region of the thin film transistor corresponds to a second semi-transparent region of the mask, the source electrode and drain electrode of the thin film transistor correspond to a non-transparent region of the mask, and the first semi-transparent region of the mask is of transmittance greater than that of the second semi-transparent region of the mask.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: June 20, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seungjin Choi, Heecheol Kim, Youngsuk Song, Seongyeol Yoo
  • Patent number: 9487397
    Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 8, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: William Robert Morrison, Mark Christopher Fisher, Murali Hanabe, Ganapathy Subramaniam Sivakumar, Simon Joshua Jacobs
  • Patent number: 9449990
    Abstract: Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 20, 2016
    Assignees: KOBE STEEL, LTD., Samsung Display Co., Ltd.
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Hiroaki Tao, Toshihiro Kugimiya, Byung Du Ahn, Gun Hee Kim, Jin Hyun Park, Yeon Hong Kim
  • Patent number: 9391186
    Abstract: A semiconductor device may include: a first semiconductor layer having a first band gap; a second semiconductor layer including first and second regions separately disposed on an upper surface of the first semiconductor layer and having a second band gap wider than the first band gap; and a third semiconductor layer disposed between the first and second regions of the second semiconductor layer, extending up to at least a portion of the first semiconductor layer. The third semiconductor layer may have a channel region doped with an impurity.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Lee, Chan Ho Park
  • Patent number: 9385022
    Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 9337372
    Abstract: A photovoltaic device may be provided having a semiconductor substrate, an i-type amorphous layer or an i-type amorphous layer formed over a front surface or a back surface of the semiconductor substrate, and a p-type amorphous layer or an n-type amorphous layer formed over the i-type amorphous layer or the i-type amorphous layer. The i-type amorphous layer or the i-type amorphous layer has an oxygen concentration profile in which a concentration is reduced in a step-shape from a region near an interface with the semiconductor substrate and along a thickness direction.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 10, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akiyoshi Ogane, Yasufumi Tsunomura
  • Patent number: 9331226
    Abstract: A photovoltaic device is provided having a semiconductor substrate, an i-type amorphous layer formed over a front surface of the semiconductor substrate, a p-type amorphous layer formed over the i-type amorphous layer, an i-type amorphous layer formed over a back surface of the semiconductor substrate, and an n-type amorphous layer formed over the i-type amorphous layer. The i-type amorphous layer and the i-type amorphous layer have oxygen concentration profiles in which concentrations are reduced in a step-shape from regions near interfaces with the semiconductor substrate and along a thickness direction, and an oxygen concentration in the step-shape portion of the i-type amorphous layer is higher than an oxygen concentration in the step-shape portion of the i-type amorphous layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 3, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ayumu Yano, Akiyoshi Ogane
  • Patent number: 9246132
    Abstract: A flexible organic light-emitting display apparatus includes a flexible substrate, a barrier layer on the flexible substrate, a display portion on the barrier layer, an encapsulation layer covering the display portion, and a moisture absorption layer between the flexible substrate and the display portion.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: January 26, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hun Kang, Young-Seo Choi, Dong-Won Han, Oh-June Kwon
  • Patent number: 9231065
    Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: January 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jae Bum Kim
  • Patent number: 9130046
    Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: September 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Toshinari Sasaki, Miyuki Hosoba
  • Patent number: 9041202
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9035314
    Abstract: An object of the present invention is to provide an electrooptical device having high operation performance and reliability, and a method of manufacturing the electrooptical device. Lov region 207 is disposed in n-channel TFT 302 that comprises a driver circuit, and a TFT structure which is resistant to hot carriers is realized. Loff regions 217 to 220 are disposed in n-channel TFT 304 that comprises a pixel section, and a TFT structure of low off current is realized. An input-output signal wiring 305 and gate wiring 306 are formed by laminating a first wiring and a second wiring having lower resistivity than the first wiring, and wiring resistivity is steeply reduced.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Publication number: 20150129876
    Abstract: Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Inventors: Ilyas Mohammed, Liang Wang
  • Patent number: 9018629
    Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sachiaki Tezuka, Atsuo Isobe, Takehisa Hatano, Kazuya Hanaoka
  • Patent number: 9013011
    Abstract: A staggered die MEMS package includes a substrate having a converter cavity formed therein. A converter electronic component is mounted within the converter cavity. Further, a MEMS electronic component is mounted to both the substrate and the converter electronic component in a staggered die arrangement. By staggering the MEMS electronic component directly on the converter electronic component instead of locating the MEMS electronic component in a side by side arrangement with the converter electronic component, the total package width of the staggered die MEMS package is minimized. Further, by locating the converter electronic component within the converter cavity and staggering the MEMS electronic component directly on the converter electronic component, the total package height, sometimes called Z-height, of the staggered die MEMS package is minimized.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 21, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Bob Shih-Wei Kuo, Brett Arnold Dunlap, Louis B. Troche, Jr., Ahmer Syed, Russell Shumway
  • Patent number: 9012912
    Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Patent number: 9013008
    Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Xi Li, Viorel C. Ontalus
  • Publication number: 20150097187
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 9, 2015
    Inventors: Bogdan GOVOREANU, Christoph ADELMANN, Leqi ZHANG, Malgorzata JURCZAK
  • Patent number: 8999105
    Abstract: An etch mask is formed on a substrate. The substrate is positioned in an enclosure configured to shield an interior of the enclosure from electromagnetic fields exterior to the enclosure; and the substrate is etched in the enclosure, including removing a portion of the substrate to form a structure having at least a portion that is isolated and/or suspended over the substrate.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 7, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Marko Loncar, Mikhail D. Lukin, Michael J. Burek, Nathalie de Leon, Brendan Shields
  • Patent number: 8994623
    Abstract: A pixel circuit includes: a switching transistor whose conduction is controlled by a drive signal supplied to the control terminal; a drive wiring adapted to propagate the drive signal; and a data wiring adapted to propagate a data signal. The drive wiring is formed on a first wiring layer and connected to the control terminal of the switching transistor. The data wiring is formed on a second wiring layer and connected to a first terminal of the switching transistor. A multi-layered wiring structure is used so that the second wiring layer is formed on a layer different from that on which the first wiring layer is formed.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Tetsuo Minami, Yukihito Iida, Katsuhide Uchino
  • Patent number: 8987730
    Abstract: An object of one embodiment of the present invention is to provide a highly reliable semiconductor device by giving stable electric characteristics to a transistor including an oxide semiconductor film. The semiconductor device includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, an oxide semiconductor film over the gate insulating film, a drain electrode layer provided over the oxide semiconductor film to overlap with the gate electrode layer, and a source electrode layer provided to cover an outer edge portion of the oxide semiconductor film. The outer edge portion of the drain electrode layer is positioned on the inner side than the outer edge portion of the gate electrode layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Satoru Saito, Terumasa Ikeyama
  • Patent number: 8980657
    Abstract: The present invention is a method for producing a light-emitting device whose p contact layer has a p-type conduction and a reduced contact resistance with an electrode. On a p cladding layer, by MOCVD, a first p contact layer of GaN doped with Mg is formed. Subsequently, after lowering the temperature to a growth temperature of a second p contact layer being formed in the subsequent process, which is 700° C., the supply of ammonia is stopped and the carrier gas is switched from hydrogen to nitrogen. Thereby, Mg is activated in the first p contact layer, and the first p contact layer has a p-type conduction. Next, the second p contact layer of InGaN doped with Mg is formed on the first p contact layer by MOCVD using nitrogen as a carrier gas while maintaining the temperature at 700° C. which is the temperature of the previous process.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: March 17, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shinya Boyama, Yasuhisa Ushida
  • Patent number: 8981367
    Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Takuro Ohmaru
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8969182
    Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Naoto Yamade, Yuhei Sato, Yutaka Okazaki, Shunpei Yamazaki
  • Publication number: 20150053983
    Abstract: Systems and methods are provided for dopant activation in a semiconductor structure for fabricating semiconductor devices. For example, a substrate is provided. A semiconductor structure is formed on the substrate. Pre-amorphization implantation is performed on the semiconductor structure. Microwave radiation is applied to the semiconductor structure to activate dopants in the semiconductor structure for fabricating semiconductor devices. Microwave-radiation absorption of the semiconductor structure is increased after the pre-amorphization implantation.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHUN-HSIUNG TSAI, CHEN-FENG HSU, YI-TANG LIN, Clement HSINGJEN WANN
  • Patent number: 8952243
    Abstract: A stacked structure may include semiconductors or semiconductor layers grown on an amorphous substrate. A light-emitting device and a solar cell may include the stacked structure including the semiconductors grown on the amorphous substrate. A method of manufacturing the stacked structure, and the light-emitting device and the solar cell including the stacked structure may involve growing a crystalline semiconductor layer on an amorphous substrate.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jun-hee Choi
  • Publication number: 20150034953
    Abstract: Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-?/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-? dielectric layer on the STI region, forming a metal gate on the high-? dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: Andreas KURZ, Maciej WIATR