With Current Ballasting Means (e.g., Emitter Ballasting Resistors Or Base Current Ballasting Means) Patents (Class 257/580)
  • Patent number: 8735989
    Abstract: According to one embodiment, a semiconductor device includes a main element and a sense element. The main element is connected between a collector terminal and an emitter terminal. The main element has an insulated gate bipolar transistor structure. The sense element is connected in parallel with the main element via a sense resistor between the collector terminal and the emitter terminal. The sense element has an insulated gate bipolar transistor structure with a feedback capacitance larger than a feedback capacitance of the main element.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Matsushita
  • Patent number: 8193609
    Abstract: A heterojunction bipolar transistor (HBT) device and system having electrostatic discharge ruggedness, and methods for making the same, are disclosed. An HBT device having electrostatic discharge ruggedness may include one or more emitter fingers including an emitter layer, a transition layer formed over the emitter layer, and an emitter cap layer formed over the transition layer.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: June 5, 2012
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Timothy Henderson, Jeremy Middleton, John Hitt
  • Patent number: 7919830
    Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Kimball M. Watson
  • Patent number: 7732896
    Abstract: A semiconductor apparatus comprises a plurality of transistor devices including a control terminal being inputted with a control signal and a first and a second terminals that a current flows therein according to the control signal, and a plurality of substrate conductive portions each formed in a region different from a region where the plurality of transistor devices are formed therein, wherein the transistor devices are connected to the substrate conductive portions, and each of the substrate conductive portion includes a semiconductor layer separated from other substrate conductive portions.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kouzi Hayasi
  • Patent number: 7675120
    Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: March 9, 2010
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Keiichi Sekiguchi, Kazuya Aizawa
  • Publication number: 20090140388
    Abstract: A semiconductor emitter structure for emitting charge carriers of a first conductivity type in a base volume of a second conductivity type material neighbored to the emitter structure in a vertical direction, includes multiple emitter volumes of first conductivity tape material having a predetermined lateral dimension in a lateral direction perpendicular to the vertical direction. The emitter volumes are, in the lateral direction, neighbored by semiconductor volumes of second conductivity type material, wherein the predetermined lateral dimension is such that space charges created by second conductivity type carriers laterally diffusing into the emitter volumes from the semiconductor volumes limit a maximum density of first conductivity type carriers within the emitter volumes by more than 20% as compared to emitter volumes of the same lateral dimension not neighbored by semiconductor volumes of the second conductivity type material.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: Infineon Technologies Austria AG
    Inventors: Joachim Joos, Matthias Stecher
  • Patent number: 7491982
    Abstract: A semiconductor device, including: a semiconductor substrate of the first conductivity type having a first surface and a second surface; a base region of the second conductivity type formed on the first surface of the semiconductor substrate; a guard ring region of the second conductivity type formed around the base region, and having the second type impurity of which concentration is lower than that of the base region; a first electrode formed on the base region; and a second electrode formed on the second surface of the semiconductor substrate, further including a base peripheral region formed around the base region and being connected to the base region, wherein the base peripheral region is deeper than the base region and has the substantially constant depth, and the concentration of the second conductivity type impurity included in the base peripheral region is lower than that included in the base region.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: February 17, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi
  • Patent number: 7319254
    Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: January 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hwa Kwak, Byung-Seo Kim
  • Patent number: 7303968
    Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Louis D. Lanzerotti, Steven H. Voldman
  • Patent number: 7064416
    Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 20, 2006
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Louis D. Lanzerotti, Steven H. Voldman
  • Patent number: 6946720
    Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: September 20, 2005
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6858917
    Abstract: A metal oxide semiconductor (MOS) bandgap voltage reference circuit with a plurality of dummy bipolar junction transistors (BJTs) coupled to the mismatched parasitic substrate BJTs for improving parasitic capacitance matching, thereby improving startup behavior of the bandgap reference circuitry.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: February 22, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Paul David Ranucci
  • Patent number: 6803643
    Abstract: HBTs in an HBT array are configured non-linearly, i.e., staggered, thus reducing the impact of thermal coupling between adjacent HBTs in the array and bypassing the minimum collector-to-collector spacing design rules required for a linear HBT array. Using this non-linear configuration, adjacent HBTs are misaligned with respect to each other. In a preferred embodiment, adjacent HBTs in the array are configured in a corner-to-corner arrangement, and in a more preferred embodiment, the collectors of the adjacent HBTs are aligned or are common, i.e., the collector of one HBT is shared with the collector of an adjacent HBT. In a most preferred embodiment, the HBTs are ballasted in an emitter-ballast/base-ballast pattern (referred to as “mixed ballasting” or “dual-ballasting”).
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: October 12, 2004
    Assignee: M/A-Com, Inc.
    Inventor: Thomas A. Winslow
  • Patent number: 6798019
    Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: September 28, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Jack E. Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange
  • Publication number: 20040159912
    Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 19, 2004
    Applicant: INTERSIL AMERICAS INC.
    Inventor: James D. Beasom
  • Patent number: 6762479
    Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Groves, Dale K. Jadus, Dominique L. Nguyen-Ngoc, Keith M. Walter
  • Patent number: 6656812
    Abstract: A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: December 2, 2003
    Assignee: STMicroelectronics SA
    Inventors: Michel Marty, Didier Dutartre, Alain Chantre, S├ębastien Jouan, Pierre Llinares
  • Patent number: 6642553
    Abstract: The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide the most conductive connections possible between the metal contacts and the active (internal) transistor region as well as a minimized passive transistor surface, while at the same time avoiding greater process complexity and increased contact resistances. To this end a surface relief is produced in the active emitter region by a wet-chemical process. A single-process poly-silicon bipolar transistor having a base produced by epitaxis in accordance with the invention permits a reduction in external base resistance without causing a deterioration in emitter properties.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: November 4, 2003
    Assignee: Institut fuer Halbleiterphysik Frankfurt (Oder) GmbH.
    Inventors: Juergen Drews, Bernd Tillack, Bernd Heinemann, Dieter Knoll
  • Patent number: 6627925
    Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector contact for coupling to the collector terminal is deposited in a trench that is formed in the collector layer and the sub-collector layer.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: September 30, 2003
    Assignee: Skyworks Solutions, Inc.
    Inventor: Hugh J. Finlay
  • Patent number: 6483170
    Abstract: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor is arranged along at least one side of a silicon bipolar transistor on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor. The added integrated resistor is a diffused p+ resistor on said semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added- resistor or resistors (20) will be manufactured in a step simultaneously as producing the ballast resistors.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: November 19, 2002
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Ted Johansson
  • Patent number: 6455919
    Abstract: A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate, a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor, an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region. the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ciaran J. Brennan, Steven H. Voldman
  • Patent number: 6437419
    Abstract: A power semiconductor device has an integral source/emitter ballast resistor. The gate has partial gate structures spaced apart from each other. Emitter resistors are provided beneath sidewall spacers on the ends of the gate structures. The emitter resistors have little effect on the threshold voltage under normal operating conditions, but rapidly saturate the device during short circuit conditions. This in turn increases the short circuit withstand capability o the device.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: August 20, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Anup Bhalla, Praveen Muraleedharan Shenoy
  • Publication number: 20020000567
    Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.
    Type: Application
    Filed: November 6, 1998
    Publication date: January 3, 2002
    Inventors: ROBERT A. GROVES, DALE K. JADUS, DOMINIQUE L. NGUYEN-NGOC, KEITH M. WALTER
  • Patent number: 6303973
    Abstract: A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: October 16, 2001
    Assignee: Rohm Co., Ltd.
    Inventors: Eiji Nakagawa, Seiichi Yamamoto
  • Patent number: 6236071
    Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector terminal for coupling to the collector contact is deposited in a trench that is formed in the collector layer and the sub-collector layer.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: May 22, 2001
    Assignee: Conexant Systems, Inc.
    Inventor: Hugh J. Finlay
  • Patent number: 6236072
    Abstract: A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitter regions are directly connected in parallel to the high current carrying metal layer of the transistor through vias or metal contact studs. The size of the emitter regions should be made as small as the process design rules will allow in order to allow an increase in the perimeter to area ratio of the emitter region which, for a given current, decreases the peak current density.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: May 22, 2001
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Lars Tilly, Per-Olof Magnus Brandt
  • Patent number: 6130471
    Abstract: A ballasted transistor structure reduces thermal runaway. A heterojunction bipolar junction transistor array includes a plurality of transistors, each having an emitter, a base and a collector. Each of the bases is an alloy of silicon and germanium and each of the collectors and emitters is silicon. A ballast resistor, of doped silicon, that prevents thermal runaway, is electrically connected to each of the collectors.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: October 10, 2000
    Assignee: The Whitaker Corporation
    Inventor: Timothy Edward Boles
  • Patent number: 6043520
    Abstract: A hetero-junction bipolar transistor having high reliability wherein a ballast resistance is exactly controlled and deterioration in current stability is eliminated. A GaAs ballast resistor layer is provided in a hetero-junction bipolar transistor having a GaAs emitter layer, an InGaP spacer layer, and a GaAs base layer, preventing a notch from being formed in the conduction band at the interface of the emitter layer and the ballast resistor layer, exactly controlling the ballast resistance. The AlGaAs layer is prevented from trapping impurities and the current stability is prevented from deteriorating.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 28, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Ryo Hattori
  • Patent number: 6013942
    Abstract: In order to avoid thermal runaway bipolar transistors, emitters are provided with ballast resistors. Elongate ballast resistors may be used, part of the lengths being connected for obtaining suitable resistance and design variability. The emitters are split up into a plurality of emitter portions, each with a separate emitter ballast resistor. The collector and base are correspondingly split up. The transistor is split up into unit cells, each comprising an emitter, a ballast resistor, a base, and a collector, which are respectively connected via respective common leads. This structure may advantageously be realized in a SOI technique, the galvanic isolation enabling unproblematic mixing of digital and analog and power devices in the same chip.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: January 11, 2000
    Assignee: Telefonakteibolaget LM Ericsson
    Inventors: Anders Soderbarg, Nils Ola Ogren, H.ang.kan Sjodin
  • Patent number: 6013941
    Abstract: A semiconductor device provided with a planar bipolar transistor and a built-in ingredient acting as an element to protect the bipolar transistor from an external surge voltage e.g. an electrostatic surge voltage and the like, is provided with a planar bipolar transistor further provided with a doped region having a conductivity opposite to that of a semiconductor substrate in which the foregoing planar bipolar transistor is produced, the doped region being produced along the top surface of the semiconductor substrate at a location close to the bipolar transistor, and the emitter of the bipolar transistor being connected the doped region and a fixed potential (V.sub.EE) or the ground potential, whereby the operation speed of a circuit including the transistor is not reduced by potential parasitic capacitors which otherwise accompany the built-in ingredients produced to protect the transistor from an external surge voltage e.g. an electrostatic surge voltage and the like.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: January 11, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takayuki Shimizu
  • Patent number: 5998855
    Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: December 7, 1999
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Davide Patti
  • Patent number: 5990539
    Abstract: A transistor component is suited for controlling large currents, even given high frequencies. The transistor component includes integrated emitter resistors which are arranged between partial-emitter regions and emitter-metal contacts. The integrated emitter resistors cause a stabilized, uniform current distribution both over the various partial-emitter regions, and within the partial-emitter regions, and bring about an improved current carrying capacity, as well as improved high-frequency properties, particularly in view of the finite magnitude of the extrinsic base resistance.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: November 23, 1999
    Assignee: Robert Bosch GmbH
    Inventors: Gerhard Conzelmann, Heinz Pfizenmaier, Wolfgang Appel, Volker Dudek, Helmut Schneider
  • Patent number: 5939739
    Abstract: The present invention relates to a heterojunction bipolar transistor structure having a device mesa 401 with a collector region 402, a base region 403 and an emitter region 404. An emitter metal layer 405 is connected to a ballast resistor 406 which in turn is connected to an emitter bump 407 by way of the air bridge 408. The thermal bump 409 is connected to the emitter metallization by way of a layer of heat dissipation material 410, preferably silicon nitride. The present structure enables dissipation of heat at the emitter contact as well as a ballast resistor connected to the emitter by way of metallization 405. This arrangement enables the dissipation of joule heat to avoid higher temperature of operation which results increased current at the collector which increases the temperature thereby further increasing the current, as well as provides a ballast resistor to reduce the collector current back to an acceptable value to avoid thermal runaway.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 17, 1999
    Assignee: The Whitaker Corporation
    Inventor: Matthew Francis O'Keefe
  • Patent number: 5907180
    Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: May 25, 1999
    Assignee: Telefonaktiebolaget L.M. Ericsson
    Inventors: Ted Johansson, Larry Leighton
  • Patent number: 5841184
    Abstract: A silicon bipolar junction transistor in integrated form is disclosed having a ballast resistance integrated onto a silicon chip. This resistance is for the purpose of thermal stability. In addition, a bypass capacitance circuit is placed in parallel with the ballast resistance again in integrated form. The silicon BJT is flip-chip mounted on a heterolithic microwave integrated circuit glass substrate having the integrated bypass capacitor circuit fabricated directly thereon. This bypass capacitor circuit is electrically in contact with the emitter fingers of the bipolar junction transistor.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: November 24, 1998
    Assignee: The Whitaker Corporation
    Inventor: Ping Li
  • Patent number: 5821602
    Abstract: Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: October 13, 1998
    Assignee: Spectrian, Inc.
    Inventors: Francois Hebert, William McCalpin
  • Patent number: 5804867
    Abstract: An RF power transistor having improved thermal balance characteristics includes a first emitter electrode and a base electrode formed on a silicon die, each having a multiplicity of parallel electrode fingers. A second emitter electrode is formed over the base electrode, and is electrically connected to the first emitter electrode. Ballast resistors are formed in a substantially evenly spaced manner on each side the silicon die, in series with at least some of the electrode fingers of the first emitter electrode and in series of at least some of the electrode fingers of the second emitter electrode.
    Type: Grant
    Filed: October 2, 1996
    Date of Patent: September 8, 1998
    Assignee: Ericsson Inc.
    Inventors: Larry Leighton, Ted Johansson, Bertil Skoglund
  • Patent number: 5798561
    Abstract: A semiconductor device including a bipolar transistor is provided, which can reduce the base resistance of the transistor. This device includes a semiconductor base region having a first semiconductor active region of a first conductivity type in its inside. A first insulating layer is formed on the main surface of the substructure to cover the first active region. The first insulating layer has a first penetrating window exposing the first active region. A semiconductor contact region of a second conductivity type is formed on the first insulating layer. The contact region has an overhanging part which overhangs the first window. The second window is defined by the inner end of the overhanging part to be entirely overlapped with the first window. The contact region is made of a polycrystalline semiconductor. A second semiconductor active region of the second conductivity type is formed on the first active region in the first window.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: August 25, 1998
    Assignee: NEC Corporation
    Inventor: Fumihiko Sato
  • Patent number: 5760457
    Abstract: A bipolar transistor circuit element includes a semiconductor substrate; successively disposed on the substrate, a base layer, an emitter layer, and a collector layer; a bipolar transistor formed from parts of the collector, base, and emitter layers and including a base electrode electrically connected to the base layer and a base electrode pad for making an external connection to the base layer; a base ballasting resistor formed from a part of the base layer isolated from the bipolar transistor and electrically connecting the base electrode to the base electrode pad; and a base parallel capacitor connected in parallel with the base ballasting resistor wherein the base parallel capacitor includes part of the base input pad, a dielectric film disposed on part of the base electrode pad, and a second electrode disposed on the dielectric layer opposite the base electrode pad and electrically connected to the emitter electrode of the bipolar transistor.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: June 2, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Mitsui, Takuji Sonoda, Teruyuki Shimura, Saburo Takamiya
  • Patent number: 5736755
    Abstract: Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: April 7, 1998
    Assignee: Delco Electronics Corporation
    Inventors: John Rothgeb Fruth, John Kevin Kaszyca, Mark Wendell Gose
  • Patent number: 5654562
    Abstract: An insulated gate semiconductor device (10) is fabricated by providing at least one ballast resistor (40) having a sheet resistance of at least one square. The ballast resistor (40) is formed in the emitter region (17) between two adjacent portions of the base region (26) at the top surface of the semiconductor body in which the device (10) is fabricated. The ballast resistor (40) improves the latch resistance of the device (10) in overload conditions.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: August 5, 1997
    Assignee: Motorola, Inc.
    Inventors: William L. Fragale, Paul J. Groenig, Vasudev Venkatesan
  • Patent number: 5557131
    Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: September 17, 1996
    Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
    Inventor: Steven Lee
  • Patent number: 5557139
    Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: September 17, 1996
    Assignee: Consorzio per la Ricerca Sulla Microelettronica nel Mezzogiorno
    Inventor: Sergio Palara
  • Patent number: 5498892
    Abstract: A field effect transistor with improved electrostatic discharge (ESD) protection has a source, a channel underlying a gate electrode and a drain. The drain includes a lightly doped ballast resistor extending across the width of the drain and separating two other drain sub-regions. One drain sub-region is located between the ballast resistor and the channel, the other drain sub-region is opposite the resistor and connected to an exterior device. The ballast resistor laterally distributes current along the width of the drain during an ESD pulse, which reduces local peak current density and reduces damage.
    Type: Grant
    Filed: September 29, 1993
    Date of Patent: March 12, 1996
    Assignee: NCR Corporation
    Inventors: John D. Walker, Samuel C. Gioia
  • Patent number: 5444292
    Abstract: The ballast resistance of a semiconductor device is increased without decreasing the figure of merit of the device. The semiconductor device includes an emitter feeder, a first contact coupled to the emitter feeder, a second contact, a resistive medium connected between the first contact and the second contact, an emitter, and a further resistive medium connected between the second contact and the emitter. The ballast resistance of the semiconductor device is increased without decreasing the figure of merit of the device by increasing the distance between the first contact and the second contact.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: August 22, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: William P. Imhauser
  • Patent number: 5408124
    Abstract: A finger-emitter power transistor including a substrate suitable for operating as the collector of the power transistor, an epitaxial layer superimposed over the substrate (and providing a base region for the transistor), and at least one buried emitter region (for each finger of the device) below the surface of the epitaxial layer. Each buried emitter region is provided with at least one connection area to an emitter surface metallization. The connection areas between the emitter regions and their emitter surface metallization are made in various widths to provide a ballast resistance of an adequate value.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: April 18, 1995
    Assignee: Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno
    Inventor: Sergio Palara
  • Patent number: 5387813
    Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: February 7, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Ali A. Iranmanesh, David E. Bien, Michael J. Grubisich
  • Patent number: 5321279
    Abstract: Generally, and in one form of the invention a semiconductor device is presented comprising: a transistor comprising an emitter finger and a base finger; and a ballast impedance connected to the base finger. Other devices and methods are also disclosed.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: June 14, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: M. Ali Khatibzadeh, Wiliam U. Liu