With Separate Emitter Areas Connected In Parallel Patents (Class 257/579)
  • Patent number: 10636877
    Abstract: A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10103708
    Abstract: An IC for heating includes a semiconductor, substrate on which a diffusion layer is formed; a first pad that applies a power source voltage to the diffusion layer; and a second pad that applies a ground voltage to the diffusion layer. A semiconductor substrate includes slits such that the slits intersect a virtual straight line connecting the pads when the semiconductor substrate is seen in a plan view.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: October 16, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kenji Hayashi, Akihiro Fukuzawa
  • Patent number: 9666607
    Abstract: A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hong-Kyu Kim, Bong-Jun Lee, Ju Hee Lee, Sun-Kwun Son, Jae Yoon Jung, Seung Han Jo
  • Patent number: 9179568
    Abstract: An electronic device includes: a housing having a concave portion in the first surface of the housing; a lid made of a semiconductor material containing an impurity material; a first metal film formed in a metal film formation region on the first surface of the housing, wherein the metal film formation region is defined as a region surrounding the concave portion on the first surface of the housing; a second metal film formed on the first surface of the lid to overlap with the metal film formation region in a top view of the electronic device; a third metal film formed on the second surface of the lid to overlap with the metal film formation region in the top view; and an electronic component disposed in the concave portion. The lid is bonded onto the housing via the first and second metal films to cover the electronic component.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 3, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Murayama
  • Patent number: 9118126
    Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: August 25, 2015
    Assignee: International Rectifier Corporation
    Inventor: Hsueh-Rong Chang
  • Patent number: 9076811
    Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: July 7, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: In Hyuk Song, Jae Hoon Park, Dong Soo Seo
  • Patent number: 8994147
    Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Khalid Hassan Hussein, Shoji Saito
  • Patent number: 8952553
    Abstract: The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: February 10, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaru Senoo, Tomohiko Sato
  • Patent number: 8866263
    Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Marie Denison
  • Patent number: 8766427
    Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 1, 2014
    Assignee: NXP, B.V.
    Inventor: Marnix Bernard Willemsen
  • Patent number: 8691684
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 8, 2014
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: Guo Hua Zhong, Mei Yang
  • Patent number: 8653628
    Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: In Hyuk Song, Jae Hoon Park, Dong Soo Seo
  • Patent number: 8513774
    Abstract: An electrostatic discharge (ESD) protected device may include a substrate, an N+ doped buried layer, an N-type well region and a P-type well region. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may be disposed proximate to a portion of the N+ doped buried layer to form a collector region. The P-type well region may be disposed proximate to remaining portions of the N+ doped buried layer and having at least a P+ doped plate corresponding to a base region and distributed segments of N+ doped plates corresponding to an emitter region.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 20, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Chan Wing Chor
  • Patent number: 8502347
    Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: August 6, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8384193
    Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8354733
    Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: January 15, 2013
    Assignee: International Rectifier Corporation
    Inventor: Hsueh-Rong Chang
  • Patent number: 8334179
    Abstract: A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 18, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8299579
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 30, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 8294244
    Abstract: A semiconductor device comprises: a semiconductor substrate; a plurality of IGBT cells on the semiconductor substrate, each of the IGBT cells including a gate electrode and a first emitter electrode; a first gate wiring on the substrate and being connected to the gate electrode; an interlayer insulating film covering the first emitter electrode and the first gate wiring; and a second emitter electrode on the interlayer insulating film and being connected to the first emitter electrode through an opening of the interlayer insulating film, wherein the second emitter electrode extends above the first gate wiring via the interlayer insulating film.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 23, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Yoshifumi Tomomatsu
  • Publication number: 20120223415
    Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 6, 2012
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventor: Hsueh-Rong Chang
  • Patent number: 8212292
    Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kia Zuo
  • Patent number: 8178947
    Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: May 15, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Yoshifumi Tomomatsu
  • Patent number: 8013423
    Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 6, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Dong-Yeal Keum
  • Patent number: 8008723
    Abstract: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: August 30, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Nagai
  • Patent number: 8008746
    Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 30, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunari Hatade
  • Patent number: 7989921
    Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 2, 2011
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 7943959
    Abstract: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: May 17, 2011
    Assignee: Littelfuse, Inc.
    Inventor: Richard A Rodrigues
  • Patent number: 7932582
    Abstract: In a dual direction BJT clamp, multiple emitter and base fingers are alternatingly connected to ground and pad and share a common sub-collector.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: April 26, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Patent number: 7911032
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: March 22, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 7666787
    Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Shom Ponoth
  • Patent number: 7652350
    Abstract: A semiconductor device including a horizontal unit semiconductor element, the horizontal unit semiconductor element including: a) a semiconductor substrate of a first conductivity type; b) a semiconductor region of a second conductivity type formed on the semiconductor substrate; c) a collector layer of the first conductivity type formed within the semiconductor region; d) a base layer of the first conductivity type having an endless shape and formed within the semiconductor region such that the base layer is off the collector layer but surrounds the collector layer; and e) a first emitter layer of the second conductivity type formed in the base layer, the horizontal unit semiconductor element controlling, within a channel region formed in the base layer, movement of carriers between the first emitter layer and the collector layer, wherein the first emitter layer is formed by plural unit emitter layers which are formed along the base layer.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: January 26, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunari Hatade
  • Patent number: 7638816
    Abstract: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: December 29, 2009
    Assignee: Littelfuse, Inc.
    Inventor: Richard A. Rodrigues
  • Publication number: 20090315146
    Abstract: In a dual direction BJT clamp, multiple emitter and base fingers are alternatingly connected to ground and pad and share a common sub-collector.
    Type: Application
    Filed: June 18, 2008
    Publication date: December 24, 2009
    Inventor: Vladislav Vashchenko
  • Patent number: 7626267
    Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: December 1, 2009
    Assignee: Renesas Technology Corporation
    Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
  • Patent number: 7622796
    Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 24, 2009
    Assignee: Alpha and Omega Semiconductor Limited
    Inventors: Lei Shi, Ming Sun, Kai Liu
  • Patent number: 7615846
    Abstract: An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: November 10, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tatsuo Harada
  • Patent number: 7560771
    Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Publication number: 20090020852
    Abstract: An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved.
    Type: Application
    Filed: December 31, 2007
    Publication date: January 22, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tatsuo HARADA
  • Publication number: 20080224266
    Abstract: A lateral bipolar transistor is described, including a semiconductor substrate, a gate structure on the substrate, an emitter and a collector of a first conductivity type in the substrate, and a base of a second conductivity type in the substrate. The gate structure has a structure enclosing one or more closed areas. The emitter and the collector respectively includes a plurality of electrically connected unit emitters and a plurality of electrically connected unit collectors defined by the gate structure, which are arranged laterally intermixing with each other and separated by the substrate under the gate structure. The base includes a part under the gate structure.
    Type: Application
    Filed: January 29, 2008
    Publication date: September 18, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Sheng-Ren Chang, Hsin Chen
  • Publication number: 20080203535
    Abstract: A semiconductor device relating to the present invention comprises a base layer of an N-type impurity region. In the base layer, trenches are provided. In the each trench, a gate insulating film and a gate electrode are formed. A body layer of a P-type impurity region is formed in contact with the trenches, and in parallel adjacent to the base layer. On the main surface of the body layer, an emitter layer of an N-type impurity region is provided. On the main surface of the body layer, a contact layer of a P-type impurity region is provided spaced from the trenches. The emitter layer and the contact layer are exposed in different regions on the main surface of the body layer. A buried layer of a P-type impurity region is formed spaced from the trenches in closer to the base layer than to the contact layer in the body layer.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Inventors: Masaaki NODA, Keiki Okamoto
  • Patent number: 7411304
    Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Warren M. Farnworth
  • Patent number: 7319264
    Abstract: A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surface, and a metal film provided so as to cover at least a portion of a surface of the first main electrode and for soldering the lead terminal thereto. Here, the metal film includes a plurality of opening portions through which the surface of the first main electrode is exposed.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: January 15, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsushi Narazaki
  • Patent number: 7239007
    Abstract: A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electrically isolated and spatially separated from each other. The plural divided sub-emitter regions may typically have a uniform emitter size identical with a basic emitter size of the basic bipolar transistor. A set of the plural divided sub-emitter regions provides an intended emitter current distinctly larger than the basic emitter current by a highly accurate direct current amplification factor corresponding to an intended emitter-size magnification factor.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: July 3, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Masaru Ohki
  • Patent number: 7235860
    Abstract: A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electrically isolated and spatially separated from each other. The plural divided sub-emitter regions may typically have a uniform emitter size identical with a basic emitter size of the basic bipolar transistor. A set of the plural divided sub-emitter regions provides an intended emitter current distinctly larger than the basic emitter current by a highly accurate direct current amplification factor corresponding to an intended emitter-size magnification factor.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: June 26, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Masaru Ohki
  • Patent number: 7135756
    Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: November 14, 2006
    Assignees: STMicroelectronics S.r.l., Ovonyx, Inc.
    Inventors: Fabio Pellizzer, Giulio Casagrande, Roberto Bez
  • Patent number: 7112537
    Abstract: A method of fabricating an interconnection structure of a semiconductor device includes the steps of successively depositing an etch-stop layer and an intermetal insulating layer on a semiconductor substrate, forming a sacrificial insulating layer on the intermetal insulating layer, forming a photoresist pattern on the sacrificial insulating layer to define a trench formation region, etching the intermetal insulating layer using a mask of the photoresist pattern to form a trench, and etching the entire etch-stop layer.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: September 26, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Dong-Yeal Keum
  • Patent number: 7071514
    Abstract: A compact ESD protection device is described that uses the reverse breakdown voltage of a base-emitter junction as a trigger diode to switch a transistor that shunts the forward bias ESD current to ground. The trigger diode in series with a leakage diode provides a path to shunt the reverse bias ESD current to ground. The leakage diode is matched to the trigger diode to shunt any leakage current from the trigger diode to ground.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 4, 2006
    Assignee: Anadigics, Inc.
    Inventor: Kenneth Sean Ozard
  • Patent number: 6930373
    Abstract: The circuit has a power stage (LE) with heat generating components mounted around at least one component that generates less heat mounted in an inner region. The heat generating components are connected to at least one conducting metal body (K1) that is mounted on a cooling body (KK) in electrically insulated manner to cool the components. The cooling body encloses the inner region.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: August 16, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gerd Auerswald, Kurt Gross, Michael Kirchberger, Stefan Kulig, Hans Rappl
  • Patent number: 6853053
    Abstract: In a BJT ESD protection structure, the ESD current density is stabilized by partially blocking one or more of the emitter and n+ collector, sinker, and n-buried layer to define a comb-like structure for the partially blocked regions.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: February 8, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6798019
    Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: September 28, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Jack E. Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange