Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 ?m resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 ?m and resistivity in te range of 14 to 18 ohm cm.

Abstract: A semicoductor device includes: a collector layer made of a first conductivity type semiconductor; an intrinsic base layer formed on the collector layer and including a second conductivity type monocrystalline silicon germanium layer; a base extraction electrode formed around the intrinsic base layer and including a second conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon germanium layer; and a first conductivity type emitter layer formed in an upper portion of the intrinsic base layer. A silicon layer is formed in the upper portion of the intrinsic base layer and the emitter layer includes an upper emitter region formed in an upper portion of the silicon layer and a lower emitter region formed below and in contact with the upper emitter region.

Abstract: A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.

Abstract: A semiconductor substrate, a semiconductor chip and a semiconductor component with areas composed of a stressed monocrystalline material, and a method for production of a semiconductor component is disclosed. In one embodiment, the semiconductor chip includes relatively thick stressed layers achieving reduced switching times. For this purpose, the semiconductor substrate has one or more areas with extrinsic, permanent curvature, with the crystal structure K being compressed and/or widened and/or distorted in these areas.

Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.

Abstract: A semiconductor device (1, 20-80) has an emitter terminal (2), a collector terminal (3) and also a semiconductor body (4) provided between emitter terminal (2) and collector terminal (3). An emitter zone (5, 70) is formed in the semiconductor body (4), said emitter zone at least partially adjoining the emitter terminal (2) and also having a first interface (16) facing the emitter terminal (2) and a second interface (17) facing the collector terminal. The semiconductor device has at least one MOS structure (8, 81) which pervades the emitter zone or adjoins the latter, and which is configured such that corresponding MOS channels (11, 14) induced by the MOS structure (8, 81) within the emitter zone (5, 70) are at a distance from the first interface (16) of the emitter zone (5, 70).

Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

Abstract: A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impurities of the first conductivity type contained in the base layer. An emitter electrode of the first conductivity type contacts the emitter region, and at least a portion of the emitter electrode which is in contact with the emitter region has a single crystalline structure.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.

Abstract: Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.

Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.

Abstract: The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter region having a plurality of substantially hexagonal shaped openings defined therein, and a plurality of extrinsic base regions formed in the substrate, wherein each of the extrinsic base regions is positioned within an area defined by one of the plurality of substantially hexagonal shaped openings.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impurities of the first conductivity type contained in the base layer. An emitter electrode of the first conductivity type contacts the emitter region, and at least a portion of the emitter electrode which is in contact with the emitter region has a single crystalline structure.

Abstract: A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.

Abstract: A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n? polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: A high emission electron emitter and a method of fabricating a high emission electron emitter are disclosed. A high emission electron emitter includes an electron injection layer, an active layer of high porosity porous silicon material in contact with the electron injection layer, a contact layer of low porosity porous silicon material in contact with the active layer and including an interface surface with a heavily doped region, and an optional top electrode in contact with the contact layer. The contact layer reduces contact resistance between the active layer and the top electrode and the heavily doped region reduces resistivity of the contact layer thereby increasing electron emission efficiency and stable electron emission from the top electrode. The electron injection layer is made from an electrically conductive material such as n+ semiconductor, n+ single crystal silicon, a metal, a silicide, or a nitride.

Abstract: A method and system for providing a bipolar power transistor on a semiconductor device is disclosed. The method and system comprise providing a semiconductor substrate. The method and system includes providing an emitter base structure in the power device. The method and system further includes providing at least one oxidized slot through the emitter base structure and into the semiconductor substrate utilizing the highly inefficient portion of the emitter for this structure, thus wasted space is utilized to provide a power buss ground. This results in a smaller transistor for a given current. This is provided without any extra steps. This approach results in lower operating temperatures for a given current as compared to standard approaches.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lamination consisting of an undoped InGaAs spacer layer, n-type InP collector layer, n-type InGaAs cap layer, and collector electrode from a direction vertical to the surface of the external base layer or within an angle of 3 degrees off the vertical. In consequence, the p-type InGaAs in the external base regions remains p-type conductive and low resistive and the n-type InAlAs layer in the external emitter regions can be made highly resistive. By this method, InGaAs-base C-top HBTs can be fabricated on a smaller chip at low cost without increase of the number of processes.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter having a top surface, where the emitter is situated on the top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N+ region, instead of the electron barrier layer, is utilized to increase the gain of the bipolar transistor.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and different collector widths. The buried layer of the second component has a larger layer thickness than that of the first component; exactly one epitaxial layer is provided. The different collector widths produced as a result thereof are influenced by the outdiffusion of the dopant of the buried layers by other substances.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.

Abstract: Novel heterojunction bipolar transistors (HBT's) with high current gain and extremely low offset voltage are disclosed. Owing to the insertion of spacer/&dgr;-doped sheet/spacer at base-emitter (B-E) heterojunction in this invention, the potential spike at B-E junction can be eliminated and the confinement effect for holes are enhanced. The potential spike is not observed under large B-E bias, and the offset voltage is still relatively small with small increase. In particular, for the HBT's with large conduction band discontinuity, the method of the invention is more efficient for completely eliminating the potential spike. For the example of InP/GaInAs HBT, a maximum common-emitter current gain of 455 and above 320 at IB=5 &mgr;A, and a low offset voltage less 60 mV are achieved.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-germanium base, for example, may have a concentration of germanium greater than 20.0 atomic percent of germanium. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. According to this exemplary embodiment, the heterojunction bipolar transistor is further fabricated by fabricating an emitter over the metastable epitaxial silicon-germanium base. The heterojunction bipolar transistor is further fabricated by doping the emitter with a first dopant. The first dopant, for example, may be arsenic.

Abstract: A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: A bipolar transistor and a method for manufacturing the bipolar transistor are provided.

Abstract: A low-loss bipolar transistor comprising a collector layer composed of an n++ Si substrate and n− Si film, a base layer composed of a p− SiGe film, an emitter layer composed of an n+ Si film, a base electrode, an emitter electrode, a collector electrode, and an insulating material to coat the exposed surface including the junction boundary of the base layer and collector layer, wherein when a total length of contact boundary per unit area in the area where the emitter electrode and base electrode are adjacently arranged is assumed to be X (mm/cm2) and the dopant density of the emitter layer is assumed to be Y (atom/cm3), the expressions X≧500 and Y≧9.0×1018−3.2×1015 X are satisfied.

Abstract: A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.

Abstract: The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

Abstract: A semiconductor device is provided that comprises a gate oxide film, a gate electrode, a nitride film, a low concentration impurity area, and a high concentration impurity are. The gate oxide film is formed on a semiconductor substrate. The gate electrode is formed on a predetermined region of the gate oxide film, and an upper portion thereof is wider than a lower portion thereof by a predetermined width. The nitride film is formed at a side of the lower portion of the gate electrode, and a width of the nitride film is equal to the predetermined width. The low concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode. The high concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.

Abstract: Various embodiments of a novel transistor layout having improved electrical and heat dissipation characteristics are disclosed. Several embodiments include various intrinsic components contoured to the shape of the emitter. The various intrinsic components may include a collector layer center portion, a collector contact, a base pedestal, and/or a base contact. Additional embodiments include improved heat dissipation within single transistors. Still further embodiments include improved heat dissipation across a plurality of transistors.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.

Abstract: An exemplary embodiment of the invention is a semiconductor device comprising a substrate of a first conductivity type and a subcollector of a second conductivity type provided on the substrate. An intrinsic epitaxial layer is formed on the substrate. A collector region of the second conductivity type is adjacent the subcollector and a base region of the first conductivity type is adjacent the collector region. An emitter region of the second conductivity type is adjacent the base region and the emitter region has an emitter size. The subcollector and collector region both have a size not substantially greater than the emitter size. An alternate embodiment includes a spacer layer formed between the emitter region and the base region.

Abstract: The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.

Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer, and an emitter layer stacked sequentially. The base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.

Abstract: A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more highly doped edge layer of the second conductivity type are disposed at the surface of the substrate and are isolated from one another by pn junctions. At least one of the wells is completely surrounded by an insulating well of the first conductivity type. The doping of the insulating well is higher than that of the substrate. A method for fabricating a semiconductor component is also provided.

Abstract: An InP/InGaAlAs heterojunction bipolar transistor with the characteristics of amplification and negative-differential-resistance phenomenon is presented in the invention. The 3-terminal current-voltage characteristics of the heterojunction bipolar transistor can be controlled by the applied base current. In the large collector current regime, the heterojunction bipolar transistor has the characteristics as similar to conventional bipolar junction transistors. However, in a small collector current regime, both the transistor active region and negative-differential-resistance loci are observed. The negative-differential-resistance phenomenon is caused by the insertion of a thin base layer and a &dgr;-doped sheet. Moreover, the use of a setback layer with a thickness of 50 Å added at the emitter-base junction can suppress the diffusion of doping impurity in the base and reduce the potential spike at emitter-base heterojunction so as to improve the confinement of holes injected from base to emitter.

Abstract: According to the object, the present invention provides an electrostatic discharge (ESD) circuit, coupled between a pad and a power line. The ESD protection circuit comprises a bipolar junction transistor (BJT) . The BJT comprises a collector region having a first conductivity type, formed in a substrate, in contact with a buried layer having the first conductivity type, and coupled to the pad to become the collector of the BJT, a base region having the second conductivity type, formed on the buried layer to become the base of the BJT, and an emitter having the first conductivity type, formed in the base region and coupled to the power line to become the emitter of the BJT. The emitter has a plurality of parallel first regions and a second region connecting the first regions.

Abstract: A lateral bipolar type input/output protection device of the present invention includes a N type well formed below an emitter impurity diffusion layer of N type over a P type substrate. With such construction of the lateral bipolar type input/output protection device, a parasitic bipolar operation occurs easily and sufficient electrostatic durability without degradation of protection performance of the protection device even when a semiconductor integrated circuit is miniaturized by employing the STI isolation structure.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.