Abstract: A semiconductor bipolar transistor structure having improved electrostatic discharge (ESD) robustness is provided as well as a method of fabricating the same. Specifically, the inventive semiconductor structure a semiconductor structure comprises a bipolar transistor comprising a lightly doped intrinsic base; a heavily doped extrinsic base adjacent to said intrinsic base, a heavily doped/lightly doped base doping transition edge therebetween, said heavily doped/lightly doped base doping transition edge defined by an edge of a window; and a silicide region extending on said extrinsic base, wherein said silicide region is completely outside said window.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology.

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

Abstract: A hetero-bipolar transistor comprises: a first-conductive-type Si semiconductor substrate layer; a first Si1-xGex layer (0<x<1) formed on the first-conductive-type Si semiconductor substrate, the first Si1-xGex layer being doped with a first-conductive-type impurity; a second Si1-xGex layer formed on the first Si1-xGex layer, the second Si1-xGex layer being doped with a second-conductive-type impurity; and a Si layer formed on the second Si1-xGex layer, the Si layer being doped with the first-conductive-type impurity by a concentration higher than that of the second-conductive-type impurity.

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

Abstract: SEMICONDUCTOR DEVICE AND PROCESS OF PRODUCTION OF SAME A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.

Abstract: In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P−) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). The high-doped zone (25) which may form a contact zone has a doping concentration (P++) which is higher than that of the low-doped zone (23) and which decreases towards the low-doped zone (23).

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: A power semiconductor components has stop zones. In order to optimize the static and dynamic losses of the power semiconductor components, the stop zone is provided with donors which have at least one donor level which lies within the band gap of silicon and is at least 200 meV away from the conduction band edge of silicon.

Abstract: The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. In a device according to the invention, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N− well in a P− doped silicon substrate. A patterned Si3N4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N− base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P++ doped emitter and collector for the L-PNP. The emitter junction depth xj intersects the highly doped N+ buried base region. This N+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP.

Abstract: An emitter contact structure including a silicon substrate having a collector region, a base region within the collector region, and an emitter region within the base region. A base polysilicon layer positioned on the silicon substrate in contact with the base region and defining an aperture, with side walls, exposing the base and emitter regions of the silicon substrate. A spacer extending upwardly from the silicon substrate and formed to cover the side walls, the spacer covering the base region and partially covering the emitter region. An emitter polysilicon layer positioned entirely within the aperture in engagement with the emitter region, the spacer and the substrate without overlapping the base polysilicon layer.

Abstract: A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap on active region, inward from outside edges of the active region.

Abstract: A vertical conduction NPN bipolar transistor with a tunneling barrier of silicon carbide in the emitter providing a high emitter injection efficiency and high, stable current gain. The emitter structure comprises a heavily doped polysilicon layer atop a silicon carbide layer that contacts a shallow, heavily doped emitter region at the surface of an epitaxial silicon layer, which is disposed on a monocrystallinie silicon substrate. The silicon carbide layer is about 100 to 200 angstroms thick and has a composition selected to provide an energy band gap in the 1.8 to 3.5 eV range. The thickness and composition of the silicon carbide can be varied within the preferred ranges to tune the transistor's electrical characteristics and simplify the fabrication process.

Abstract: A bipolar transistor (100) and a method for forming the same. A diffusion source dielectric layer (118) is deposited over a semiconductor body (101). An emitter window (116) is then etched through the diffusion source dielectric layer (118). An extrinsic base region (110) is diffused from the diffusion source dielectric layer (118). The intrinsic base region (108) is then implanted. Base-emitter spacers (120) are then formed followed by the emitter electrode (124) and emitter region (126). The extrinsic base region (110) is self-aligned to the emitter eliminating the alignment tolerances for the lateral diffusion of the extrinsic base implant and an extrinsic base implant.

Abstract: A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts.

Abstract: A circuit protects against electrostatic discharge and includes a transistor connected to the circuit to be protected. A semiconductor body of a first conductivity type serves as the collector. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter. The first doped region includes a generally H-shaped doped region and a generally ring-shaped doped region forming an opening in which the second doped region serving as the emitter is received. The H-shaped doped region has a deeper junction surface than the junction surface of the ring-shaped doped region, and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region. The H-shaped doped region achieves a low collector-to-base breakdown voltage and the ring-shaped doped region achieves a low snap-back voltage.

Abstract: A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction.

Abstract: A pnp-type bipolar transistor includes a highly dop p-conducting emitter zone, a base zone and a buried n-conducting zone below the emitter zone. An additional p-conducting region is connected to the highly doped emitter zone and is disposed between the highly doped emitter zone and the buried zone. A collector zone includes a highly doped collector connection zone and a p-conducting region reaching from the collector connection zone to the buried zone.

Abstract: A SiGe alloy film containing electrically active impurity in a concentration higher than the intrinsic base layer is formed on the eaves-structured polycrystalline silicon film for base electrode. After that, SiGe only just under the opening is removed completely by dry etching under a condition that etching speed of SiGe is faster than that of Si, and subsequently the intrinsic base layer is formed.

Abstract: A semiconductor device comprises at least an emitter region of a first conductivity type, a base region of a second conductivity type, and a collector region of a first conductivity type. The base region essentially consists of Si.sub.1-X Ge.sub.X (0<X<1), further comprises regions formed in a depletion layer close to an interface between the base region and the collector region or in the collector region and in a depletion layer close to an interface between the base region and the emitter region or in the emitter region, and has a larger Ge amount at the base region-side and a smaller Ge amount at the emitter and collector sides.

Abstract: A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).

Abstract: A semiconductor integrated circuit device having a bipolar transistor and contact in the form of a wired layer by using different impurities for doping the emitter electrode and the wired layer of the device, both of which are made of polysilicon. The emitter electrode, formed on an emitter region of a p-type silicon semiconductor substrate, is doped with an n-type impurity having a low diffusion coefficient. A polysilicon wired layer, formed on an impurity diffusion region in an active region of the semiconductor substrate, is doped with another impurity that can effectively destroy native oxide films. With such an arrangement of selectively using impurities, the temperature of thermally treating the emitter region can be less than 850.degree. C.

Abstract: A protection circuit structure for an internal semiconductor integrated circuit. The protection circuit structure includes a first protection circuit having at least a first input pin and a first discharge pin, a second protection circuit having at least a second input pin and a second discharge pin and a switching device connecting between the first and second protection circuits. The switching device is biased by a potential difference between the first and second discharge pins. The switching device permits operating one of the first and second protection circuits to accomplish a discharge in replacement of an inoperative first or second discharge pin. The switching device takes the ON state when biased by a predetermined voltage or higher which interrupts the internal semiconductor integrated circuit. The switching device connects between wiring lines which respectively connect to the first and second discharge pins.

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.

Abstract: The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.

Abstract: Manufacturing a double polysilicon layer self-aligned type bipolar transistor. A polysilicon layer for emitter impurity diffusion is formed prior to the formation of a polysilicon layer for leading out a base. A first polysilicon layer containing impurities for base impurity diffusion is deposited over the entire surface of a semiconductor structure. After the first polysilicon layer is patterned into a predetermined shape, an intrinsic base layer is formed by thermally diffusing impurities from a base impurity diffusion source. Subsequently, a second polysilicon layer containing emitter impurities is formed over the base impurity diffusion source, and then patterning is performed such that the first and second polysilicon layers remain in a region narrower than the base impurity diffusion source. Thereafter, an emitter layer is formed by thermal diffusion.

Abstract: A semiconductor device including a vertical transistor, for example of the pnp type, having a p-type substrate (1) which forms the collector, with at its surface an epitaxial n-type layer (3) in which a p-type emitter region (15, 16) is formed, while the portion (9) of the epitaxial layer (3) lying between the emitter (15, 16) and the collector (1) forms the base. In this vertical transistor, the current gain is very strongly increased when the emitter is formed by a first partial emitter region which is weakly p-type doped and which extends below an insulating layer (6) and by a second partial emitter region (16) which is strongly p.sup.++ -type doped and which extends below the contact zone (26) of the emitter defined by an opening in the insulating layer (6). The respective thicknesses and doping levels of the first (15) and second (16) emitter regions are provided such that the first region is transparent to electrons and the second forms a screen against electrons.

Abstract: An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.

Abstract: A bipolar lateral transistor, for example of the pnp type, is contained in a semiconductor device. The lateral transistor has a p-type emitter region and a p-type collector region laterally spaced apart by an n-type base region. This lateral transistor is formed in an n-type epitaxial layer at the surface of a p-type substrate. The transistor further has a n.sup.++ -type buried layer. The current gain in this lateral transistor is strongly increased by forming the emitter from a first partial emitter region which is weakly p-type doped and extends below an insulating layer, and a second partial emitter region which is strongly P.sup.++ -type doped and extends below the contact zone of the emitter, which is defined by an opening in the insulating layer. The respective thicknesses and doping levels of the first and second emitter regions are provided such that the first region is transparent to electrons and the second region forms a screen against electrons.

Abstract: A semiconductor memory device, which has a memory cell comprising the following transistors: a transistor for selecting; and a bipolar transistor for memorizing, which has a base region whose base concentration as either lower than an ordinary base concentration or higher than an ordinary base concentration and which is constructed so as to generate a reverse base current.

Abstract: A finger-emitter power transistor including a substrate suitable for operating as the collector of the power transistor, an epitaxial layer superimposed over the substrate (and providing a base region for the transistor), and at least one buried emitter region (for each finger of the device) below the surface of the epitaxial layer. Each buried emitter region is provided with at least one connection area to an emitter surface metallization. The connection areas between the emitter regions and their emitter surface metallization are made in various widths to provide a ballast resistance of an adequate value.

Abstract: A semiconductor device has a semiconductor substrate including a base region and an emitter region in the base region. The emitter region in the base region has a comb-teeth-shaped outer edge. The emitter region has a window through which the base region is exposed. The window has an extended ares to reach portions of the emitter region near the comb-teeth-shaped outer edge of the emitter region. Consequently, the area of junction between the window and the emitter region os increased to suppress concentration of electrical current in the window and to improve electrical characteristics such as secondary yield breakdown strength.

Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

Abstract: This invention discloses a dual base heterojunction bipolar transistor for use in a number of different application. Current is introduced into one of the base contacts such that current is forced through the base region of the transistor to the other base contact. Because of the different resistances in the base, there will be a voltage potential between one side of the emitter mesa adjacent one of the base contacts and the other side of the emitter mesa adjacent the other base contact. This lateral voltage potential creates current crowding which forces the current density to travel to the perimeter of the transistor. Because the current travels mostly through the perimeter regions of the transistor, this concept can be used for testing for defects in the bulk of the base region by comparing the current gain without current crowding and with current crowding. Also, this concept can be used strictly as a gain control for a heterojunction bipolar transistor.

Abstract: The present invention provides a BiCMOS integrated circuit with bipolar, NMOS and PMOS transistors. In a bipolar transistor, an emitter buffer is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link. However, the n-type dopant is implant using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section. Local interconnects are formed using a "dual-gate" technique, in which a tungsten silicide cap layer is formed over polysilicon to short pn junctions in the interconnect.

Abstract: A lateral bipolar transistor and method of making which is compatible with making BICMOS circuits are disclosed. The method includes: Forming on a substrate of one conductivity type at least one layer of a semiconductor material of opposite conductivity type. Forming a first region of opposite conductivity type into one portion of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region.

Abstract: In order to simplify the structure of a power amplifying transistor and improve its high-frequency characteristics, a base electrode (7b) and a collector electrode (7c) are formed on the surface of such a power amplifying transistor, while an emitter electrode (7e) is formed on its rear surface. Since it is possible to easily ground the emitter electrode (7e) and use the base and collector electrodes (7b, 7c) as an input and an output respectively, the structure is simplified and no wiring pattern is required, whereby high-frequency characteristics can be improved.

Abstract: To eliminate misfit dislocation occurring in a hetero-interface and to provide a bipolar transistor capable of a high speed operation, the bipolar transistor is configured such that the energy band gap is progressively narrowing from part of an emitter layer towards part of a collector layer through a base layer.

Abstract: A heterojunction bipolar transistor has an n-type emitter layer of aluminum gallium arsenide and a beryllium doped base layer forming a heterojunction together with the n-type emitter layer, and the base layer is associated with a heavily doped carbon doped base region so that the beryllium content is restricted below the critical value for preventing the emitter layer from undesirable beryllium diffusion.

Abstract: Both homojunction and heterojunction bipolar transistor structures are fabricated in unique trenched configurations so as to better utilize their surface areas by employing both the vertical and horizontal portions of their base regions with equal effectiveness. An important advantage of the unique trenched configurations is that the base region of each trenched structure is of precisely the same thickness throughout--both vertical and horizontal portions. Consequently, the transit time for charge carriers to diffuse across the base region and the base transport factor are uniform because of the uniform base thickness. Moreover, the parasitic capacitance region of each trenched structure beneath base metallization contacts is only a small portion of the entire base-collector junction region.

Abstract: An amorphous Si/SiC heterojunction color-sensitive phototransistor was successfully fabricated by plasma-enhanced chemical vapor deposition. The structure is glass/ITO/a-Si(n.sup.+ -i-p.sup.+)/a-SiC(i-n.sup.+)/Al. The device is a bulk barrier transistor with a wide-bandgap amorphous SiC emitter. The phototransistor revealed a very high optical gain of 40 and a response speed of 10 us at an input light power of 5 uW and a collector current of 0.12 mA at a voltage of 14 V. The peak response occurs at 610 nm under 1 V bias and changes to 420 and 540 nm under 7- and 13-V biases, respectively.

Abstract: A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The impurity layer is formed of a polycide layer formed of a polysilicon layer doped with an impurity and a metal silicide layer laminated on the polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, or a metal silicide layer.

Abstract: A III-V compound planar HBT-FET device integrates field effect transistors (FETs) with heterojunction bipolar transistors (HBTs) formed on the same semiconductor substrate. An HBT fabricated on the substrate includes a collector, a base, and an emitter. The HBT emitter comprises a lightly doped layer of a first conductivity type deposited atop a heavily doped base layer of a second conductivity type, a lightly doped emitter cap layer of the first conductivity type deposited atop the emitter layer, and a heavily doped emitter contact layer of the first conductivity type deposited atop the emitter cap layer. A FET, isolated from the HBT by areas of ion implantation, is formed in the layers of material deposited during fabrication of the HBT. The FET has a source and a drain formed in the heavily doped emitter contact layer, a gate recess etched in the emitter contact layer between the source and drain, and a Schottky gate metal contact deposited on the lightly doped emitter cap layer exposed in the gate recess.

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: A device made by a process of making strain-free, heavily carbon-doped p-type epitaxial layers for use in high performance devices and at least one such device so made. The process essentially includes the epitaxial deposition of a strain-free, carbon-doped p-type layer in a GaAs HBT device to form the base layer thereof in a manner that includes the balancing of the strain of the crystal lattice structure caused by the carbon doping by co-doping the base layer with an isovalent and isoelectric dopant. The co-doping also improves device performance. It also effects alloy hardening, which inhibits further defect formation, improves mobility and carrier lifetime of the base layer and, by narrowing the energy gap, it improves ohmic contact formation.

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor on a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the tint, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.