Abstract: A bipolar transistor, an nMOS transistor and pMOS transistor are formed at a main surface of a p-type semiconductor substrate. The bipolar transistor includes a collector layer, a base layer and an emitter layer. Collector layer located immediately under base layer contains impurity of n-type at a concentration not more than 5xl0.sup.18 cm.sup.-3. Base layer located immediately under emitter layer has a diffusion depth not more than 0.3 .mu.m. A semiconductor device including the bipolar transistor having the above structure is used in a circuit performing small amplitude operation. Thereby, it is possible to provide the semiconductor device having the bipolar transistor, which can be manufactured at a low cost and can operate at a high speed.

Abstract: In a bipolar transistor of a type in which metal electrodes are formed in direct contact with a p-type external base region and an n-type collector region, respectively, an external base region surrounding an outer periphery of an n-type emitter region is formed. A metal electrode is formed on the emitter region with a polycrystalline silicon layer therebetween. Thereby, formation of a buried diffusion layer can be eliminated, and thus a manufacturing cost of the bipolar transistor can be reduced while achieving a high performance of the bipolar transistor.

Abstract: An N-type buried region formed in the surface area of a semiconductor substrate is electrically connected to an N-type collector region formed in an epitaxial silicon layer on the semiconductor substrate. A P-type buried region is formed to overlap part of the N-type buried region. The P-type buried region is thick in the upward and downward directions of the N-type buried region. One end portion of the P-type buried region is electrically connected to a P-type base region and the other end portion thereof is electrically connected to a base region formed in the surface area of the semiconductor layer. The base region is applied with a base potential from the base region via the buried region. An N-type emitter region is formed in the base region. The N-type buried region and the P-type buried region are simultaneously formed by use of a difference between the diffusion coefficients of impurity.

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor.A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.

Abstract: A preferred pnp bipolar phototransistor pixel element in accordance with the present invention has a p-type collector region formed in p-type semiconductor material. An n-type base region is formed in the collector region. A p-type emitter region is formed in the base region. An annular n-type capacitor region is formed in the base region surrounding and spaced-apart from the emitter region. Conductive material is disposed over the capacitor region and separated therefrom by underlying dielectric material to define the pixel element's coupling capacitor.

Abstract: A heterojunction bipolar transistor includes a compound semiconductor substrate, a collector layer disposed on the compound semiconductor substrate, a base layer disposed on the collector layer, the base layer being a semiconductor having a band gap energy and including an internal base region and an external base region, and an emitter layer disposed on the base layer and being a semiconductor having a band gap energy larger than the band gap energy of the semiconductor of the base layer. The base layer is larger in area than the emitter layer by the external base region. The external base region is sandwiched by insulating films at the external base region. Therefore, without ion-implantation to make the resistance of the collector layer below the external base region higher, i.e., without increasing the base resistance, the base-collector capacitance is reduced, resulting in an HBT having an improved high frequency gain.

Abstract: A bipolar transistor includes a base structure in a hollow space on a single crystal silicon collector region defined by a silicon oxide layer, and the base structure has an extrinsic base provided around a single crystal silicon emitter region and an intrinsic base layer of single crystal silicon germanium decreasing the thickness from a central portion toward an outer periphery so as to decrease dislocation due to thermal stress in a heat treatment for the emitter region.

Abstract: A semiconductor device having a first insulation film, a base contact and a second insulation film on a semiconductor substrate. The first and second insulation films and the base contact respectively have openings which forms a hole extending therethrough on the substrate. An end of the base contact is projected over the substrate in the hole. A base connection region is in contact with the side and bottom faces of the projected end of the base contact and with a surface of a base region in the hole. An emitter region is formed in the base region. Reduced contact resistance between the base contact and the base connection region can be obtained.

Abstract: An apparatus and method are provided for bypassing the emitter ballast resistors of a power transistor, thereby increasing transistor gain. In a power transistor of the interdigitated type, bypassing the emitter ballast resistors requires bypassing each individual ballast resistor with a capacitor in parallel. Bypassing is therefore done on the silicon chip. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, an emitter ballast resistor formed on the silicon die, and a bypass capacitor formed on the silicon die and connected in parallel with the emitter ballast resistor. The resistor may be a diffused resistor, and the capacitor may be a metal-on-polysilicon capacitor.

Abstract: A bipolar transistor is provided whose emitter surrounds the base. The transistor has in some embodiments a high ratio of the emitter area to the base area and low collector and emitter resistances. Further, a transistor is provided in which a collector contact region is surrounded by the base. Consequently, a low collector resistance is obtained in some embodiments.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped poly region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the poly region. An oxide region is provided on a portion of the first region surface adjacent to the poly region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a poly region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the poly region into the first region. The third region is then formed adjacent to the second region.

Abstract: In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation of the lateral PNP bipolar transistor and drop of yield in production thereof being prevented and a high performance (low cost) Bi-CMOS LSI being realized.

Abstract: The present invention provides a bipolar transistor in which a lightly doped n-type hot-carrier shield extends in an epitaxial layer adjacent from a poly-emitter to an extrinsic base. This hot-carrier shield minimizes performance impairment that would otherwise occur due to a hot-carrier effect. Key steps in the method of making the bipolar transistor include a differential thermal oxidation while the poly-emitter is covered with a nitride cap. After the nitride cap is removed, an n-type dopant is implanted. The unprotected poly emitter is heavily doped. The implant partially penetrates a relatively thin oxide growth, thereby forming the hot-carrier shield. Other areas, such as the extrinsic base, and a polycrystalline base extension are covered by a relatively thick oxide growth and are unaffected by the n-type implant.

Abstract: A method of producing the bipolar transistor includes forming an aperture through a triple layer over an active region of an epitaxial layer, then forming a shallow polysilicon film at the bottom of the aperture. An intrinsic base region is formed by segregating a conductive impurity to the epitaxial layer by thermally oxidizing the polysilicon film. Then an extrinsic base region is formed by diffusing impurities into the epitaxial layer from a polysilicon sidewall formed on the aperture. In the transistor fabricated according to this method, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened.

Abstract: This invention discloses a heterojunction bipolar transistor (HBT) which includes a relatively thin intrinsic collector region and a relatively thick extrinsic collector region such that collector-base capacitance is reduced and electron transit time is maintained. The fabrication of the HBT includes loading a semi-insulating substrate into an molecular beam epitaxy machine, and growing a sub-collector contact layer, a bottom collector layer and a top collector layer on the substrate. Next, the substrate is removed from the molecular beam epitaxy machine and the top collector layer is etched by a photolithographic process to produce separate intrinsic and extrinsic collector regions. Then, the substrate is again loaded into the molecular beam epitaxy machine so that the base and emitter layers can be grown. And finally, the emitter layer is etched to form an emitter mesa only over the intrinsic semiconductor region.

Abstract: A transistor includes (a) a first semiconductor layer formed by a semiconductor substrate; (b) a second semiconductor layer formed on the first semiconductor layer and having an impurity of the same conductivity type as the first layer in a concentration lower than that of the first semiconductor layer; and (c) a third semiconductor layer formed on the second semiconductor layer having an impurity of the same conductivity type as the first semiconductor layer in a concentration lower than that of the second semiconductor layer. A base region is formed in the third layer and an emitter region is formed in the base region.

Abstract: A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A base electrode (114) is formed over at least one end portion of the base-link diffusion source layer (118) and the exposed portions of the base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: A semiconductor device comprises a semiconductor substrate having a main surface, a first semiconductor region of a first conductive type, formed on the main surface of the semiconductor substrate, a surrounding of the first semiconductor region is buried with a first insulation film, a second semiconductor region of a second conductive type, formed on the first insulation film and the first semiconductor region, a second insulation film, formed on the second semiconductor region, an end portion of the second insulation film is positioned above the first insulation film, and having an opening at a central portion thereof to be positioned above the first semiconductor region, and a third semiconductor region of a first conductivity type formed on a surface of the second semiconductor region exposed through the opening of the second insulation film.

Abstract: A low-noise NPN transistor comprising a cut-off region laterally surrounding, at a given distance, the emitter region in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. The cut-off region is formed by a P ring astride a P.sup.- type well region and the epitaxial layer.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118).A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to fore an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: A process for preparing a bipolar transistor for very high frequencies is described, which is especially advantageous for the preparation of heterobipolar transistors and leads to components with low parasitic capacities and low base lead resistance. The process includes forming a structured first layer with collector zone and insulation areas surrounding the collector zone on a monocrystalline lead layer. A series of monocrystalline transistor layers are grown on the first layer over the collector zone by differential epitaxy and a series of polycrystalline layers is grown at the same time over the insulation areas. A series of polycrystalline layers is designed as a base lead.

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed.

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.

Abstract: A structural configuration and fabrication process of a bipolar junction transistor (BJT) semiconductor device having improved current gain. The fabrication process provides a P-type heavily-doped region underneath a P-type lightly-doped base region. The P-type heavily-doped region underneath the P-type lightly-doped base region prevents electron carriers from escaping from beneath the base region of the transistor, helping the collection in a collector of electron carriers emitted by an emitter of the BJT.

Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced.

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: The present invention is directed to an improved base-collector junction transistor structure capable of higher junction breakdown voltages and lower junction capacitances than bipolar transistors of the prior art. A narrow trench is used to positively affect junction breakdown voltage and junction capacitance. The trench allows the beneficial characteristics of both depletion ring and mesa structures to be utilized. Depletion zone profiles that negatively affect junction breakdown voltage are minimized by using the trench and a depletion enhancing channel.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: An electronic component especially a p-channel or n-channel permeable base transistor (PBT) is provided as a plurality of layers, fabricated in a laminated composite, and with at least one laterally structured layer provided for controlling a space charge zone, especially a base of the electronic component.

Abstract: An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

Abstract: In accordance with the invention, the emitter region of a BJT is formed prior to the formation of the base contact regions so that the base contact regions are not enlarged during a thermal cycle used to form the emitter and the base contact regions remain small. Preferably, the base contact regions are formed by ion implantation after the emitter is formed. In addition, the base interconnect links may be metal (or polycide) rather than polysilicon so that the base interconnect resistance is reduced.This results in the following advantages:(1) reduced emitter-base junction leakage(2) reduced collector-base junction capacitance.(3) reduced base interconnection series resistance.

Abstract: The invention relates to a method of making a monolithic integrated circuit with at least one CMOS field-effect transistor and one npn bipolar transistor wherein a thin oxide layer is covered with a protective polysilicon layer in both the bipolar-transistor area and the field-effect-transistor area.

Abstract: A semiconductor device includes an n-type low-resistance region (2) formed on a p-type monocrystalline semiconductor substrate (1), an n-type epitaxial layer (3) formed on the n-type low-resistance region (2), an insulating film (5) formed on the n-type epitaxial layer (3) and having a first opening selectively formed therein, and an n-type polysilicon film (8) having an overhung portion extending from the entire peripheral portion of the opening to the inside of the opening. An n-type polysilicon film (9) is formed downward from the bottom surface of the overhung portion, and a p-type monocrystalline silicon film (6) serving as a base is formed on the surface of the n-type epitaxial layer in the first opening. The base (6) is in contact with the n-type polysilicon films (8, 9), and the n-type emitter (10) is formed immediately below the n-type emitter polysilicon films (8, 9) to have an annular shape.

Abstract: A semiconductor device having a monocrystalline semiconductor layer, a first insulating film, a base leading electrode, and a second insulating film is arranged such that a predetermined pattern window is provided in the second insulating film, a third insulating film of silicon oxide is provided between two peripheries of the predetermined pattern window, a first window is provided between a side of the second insulating film and a side of the third insulating film, a second window extends from the first window and is larger than the first window so that the base leading electrode and the third insulating film have overhang portions, first spacers are provided respectively in alignment with the peripheries of the predetermined pattern window and in alignment with the sides of the third insulating film, second spacers cover the first spacers and the overhang portions, and emitter layers are provided between and in self-alignment with the second spacers.

Abstract: A self-aligned single polysilicon bipolar transistor structure and a method of formation thereof are provided. The transistor has an emitter structure characterised by T shape defined by inwardly extending sidewall spacers formed by oxidation of amorphous or polycrystalline silicon, rather than the conventional oxide deposition and anisotropic etch back. Advantageously the method compatible with bipolar CMOS processing and provides a single polysilicon self-aligned bipolar transistor with a reduced number of processing steps. Further the formation of inwardly extending sidewalls defining the emitter width reduces the emitter base junction width significantly from the minimum dimension which is defined by photolithography, while a large area emitter contact is also provided.

Abstract: A transversal bipolar transistor is structured to have a single crystal semiconductor film provided on a single crystal semiconductor region which is provided on a semiconductor substrate. The semiconductor substrate is of a first conductivity type, and the single crystal semiconductor region is of a second conductivity type which is opposite to the first conductivity type. The single crystal semiconductor film is divided in the transversal direction into a central portion of the second conductivity type for a base region and left and right portions of the first conductivity type for emitter and collector regions. The transversal bipolar transistor may be integrated with a vertical bipolar transistor commonly on the semiconductor substrate.

Abstract: A bipolar transistor has a base rink structure epitaxially grown from an overhang portion of a poly-crystal silicon base electrode and an epitaxial collector layer and an intrinsic base structure grown on a concave central portion of the base rink structure after a diffusion stage of a dopant impurity into the base rink structure, and the intrinsic base structure is electrically connected through a buried collector region passing through the concave central portion into an epitaxial collector layer, thereby maintaining the dopant impurity profile in the intrinsic base structure without deterioration of transistor characteristics.

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118). A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.

Abstract: The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor on a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the tint, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.