Abstract: An aspect of a semiconductor device includes: a collector layer of first conductive type formed on a semiconductor substrate; a graft base layer of second conductive type formed in a surface region of the collector layer; a first base leading-out region of second conductive type formed on the graft base layer; a second base leading-out region of second conductive type formed on an upper surface and a side surface of the first base leading-out region; a base layer of second conductive type formed on the collector layer; an emitter layer of first conductive type formed in a surface region of the base layer; and an emitter leading-out region formed on the emitter layer.

Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

Abstract: A Low Noise semiconductor amplifier structure formed from layers of differently doped semiconductor material. This structure when properly biased will amplify voltage signals applied to the input terminal (Base1 or signal-base), and provide the same signal, amplified at the terminal designated as the output or collector. The semiconductor material can be any of a number of semiconductor materials, Germanium, Silicon, Gallium-Arsenide or any material with suitable semi-conducting properties. The structure can be any BJT (Bipolar Junction Transistor) form. The presence of an additional, distinct highly doped layer indicated as Base2 in the BJT form, provides an electrical noise suppression function. This inhibits intrinsic electrical noise, and improves the high frequency performance of the device in conjunction with an external capacitor connected to this new Base2 (or anti-base) region.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

Abstract: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Abstract: A method of increasing mobility of charge carriers in a bipolar device comprises the steps of: creating compressive strain in the device to increase mobility of holes in an intrinsic base of the device; and creating tensile strain in the device to increase mobility of electrons in the intrinsic base of the device. The compressive and tensile strains are created by forming a stress layer in close proximity to the intrinsic base of the device. The stress layer is at least partially embedded in a base layer of the device, adjacent an emitter structure of the device. The stress layer has different lattice constant than the intrinsic base. Method and apparatus are described.

Abstract: In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.

Abstract: A semiconductor integrated circuit including a plurality of bipolar transistors that are produced by forming, in a plurality of transistor-producing regions, a first conductive type emitter layer on the front surface side of a second conductive type base layer that is formed on the surface side of a first conductive collector layer and contains germanium, the first conductive type emitter layer being formed from a semiconductor material having a band gap larger than the base layer. The concentrations of impurities contained in the emitter layers vary among the plurality of transistor-producing regions, and the germanium concentrations differ in the base-emitter junction interfaces of at least two of the transistor-producing regions, such that the ON-state voltages required for turning the plurality of bipolar transistors into an ON state differ from each other.

Abstract: According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.

Abstract: A method of manufacturing a semiconductor device having a connection terminal and a substrate on which a circuit section and an electrode are stacked in this order, the circuit section having a multilayer interconnect structure, the electrode being conductively connected to the circuit section, and the connection terminal penetrating the substrate and being conductively connected to the electrode. Part of the connection terminal is formed simultaneously with an interconnect in an interconnect layer of the circuit section.

Abstract: A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower portion. The base includes an intrinsic base (14) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

Abstract: According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.

Abstract: A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and tuning range. A second, deeper base implant is used to improve the quality factor of the device by reducing the base resistance. The varactor includes a third terminal (collector), which isolates the emitter-base junction from the substrate, providing flexibility in circuit applications. A method for fabricating a high performance varactor having the above-described structure is also provided.

Abstract: A bipolar transistor with vertical geometry comprises a base region (1) provided with a base contact (21), emitter and collector regions (2,3) arranged to extract minority carriers from the base region, and an excluding structure for counteracting entry of minority carriers into the base region via the base contact, wherein the base region has a bandgap of greater than 0.5 eV and a doping level greater than 1017 cm?3. As shown the base includes an excluding heterojunction (4) preventing entry of carriers from the base contact (21), but alternatively the base region could comprise a “high-low” doping homojunction. The construction shows improved resistance to thermal runaway even in multi-finger transistors. It is particularly useful for high power, high frequency transistors, e.g. base on gallium indium arsenide. The collector region preferably has a heterostructure.

Abstract: The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.

Abstract: In a semiconductor substrate with a top surface, a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first portion of the first region from the surface. The improvement comprising edges of the first region being spaced from associated edges of the second region such that the doping concentration of the first region at the surface intersection of corners of the junction between the first and second regions is lower than it is at some other location in the first region.

Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.

Abstract: A bipolar transistor having a collector connected to a base, the collector including an amount of carbon sufficient to prevent a conduction band barrier at a base-collector junction.

Abstract: A bipolar transistor structure includes a collector region having a first conductivity type formed in a semiconductor substrate. A base region is formed over the collector region; the base region includes a highly doped lower layer having a second conductivity type opposite the first conductivity type formed on the collector region and a relatively low doped (or undoped) upper layer formed on the highly doped lower layer. An emitter region having the first conductivity type is formed on the upper layer of the base region.

Abstract: A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.

Abstract: A semiconductor device includes a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. Here, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: A method for quantifying safe operating regions within a safe operating area (SOA) for a bipolar junction transistor (BJT) by driving the device under test (DUT) as part of a current mirror circuit and monitoring variances in the current mirror ratio for various biasing conditions.

Abstract: A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.

Abstract: In a bipolar double-poly transistor comprising a layer of base silicon (1?) on a silicon substrate (2?), a first layer of silicon dioxide (3?) on the base silicon layer (1?), an emitter window (4?) extending through the first layer (3?) of silicon dioxide and the base silicon layer (1?), a second layer (5?) of silicon dioxide in the emitter window (4?), silicon nitride spacers (6?) on the second layer (5?) of silicon dioxide in the emitter window (4?), and emitter silicon (9?) in the emitter window (4?), an isolating silicon nitride seal is provided to separate the base silicon (1?) from the emitter silicon (9?) to prevent short-circuiting between the base silicon (1?) and the emitter silicon (9?) in the transistor.

Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

Abstract: The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown selectively in an aperture formed by removing a silicon nitride film so as to form under cut.

Abstract: A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.

Abstract: By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed of single crystal, other portions such as a sidewall portion are formed of polycrystalline, and a film thickness of the sidewall portion is less than or equal to 1.5 times the film thickness of the bottom portion. In this nonselective epitaxial growth, monosilane, hydrogen, diborane, and germane are used as source gases. Then, flow rates of monosilane and hydrogen are set to 20 sccm and 20 slm respectively. Also, a growth temperature is set to 650° C., a flow rate of diborane is set to 75 sccm, and a flow rate of germane is set to 35 sccm.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A semiconductor device which can suppress an electronic breakdown. In the semiconductor device, a base electrode is connected to a base region in a base contact region defined on a surface of the base region. An N-type region having the same conductivity type as an emitter region is provided beneath a boundary portion of the base contact region to surround the base contact region. In other words, a PN-type diode constituted by the P-type base region and the N-type region is provided beneath the boundary portion of the base contact region.

Abstract: An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the BJT to improve Bvceo. The inclusion of the scattering centers allows the width of the collector region WCD (90) to be reduced leading to an improvement in Ft/Fmax.

Abstract: A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown voltage of a bipolar transistor without the J-FET.

Abstract: A base contact section of a planar structure electrically connecting a base electrode to a base region of a bipolar transistor is constructed of a repeating structure in a plan view, in which a high impurity concentration region of the same conductivity type as that of the base region and a region of the reverse conductivity type from that of the base region or low concentration region of the same conductivity type as that of the base region, arranged in an alternately manner starting with a high impurity concentration region of the same conductivity type as that of the base region from an emitter region side. With such a structure, accumulation of minor carriers in the base contact section can be suppressed, a high switching speed can be achieved and reduction in power consumption can be realized.

Abstract: A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.

Abstract: N+-type diffusion regions, P-type diffusion region and others are formed at and near a surface of an N?-type epitaxial layer on a p-type silicon substrate. Gate electrode portions are formed on P-type diffusion region located between N?-type diffusion regions and N?-type epitaxial layer with a gate insulating film therebetween. A source electrode and a drain electrode are formed. Under a field isolating film, a P-type diffusion region is formed discretely in a direction crossing a direction of a current flow in the on state. Thereby, such a semiconductor device is obtained that rising of an on resistance can be suppressed in an on state while keeping an effect of reducing an electric field.

Abstract: An NPN transistor having an epitaxial region of an N-type silicon/P-type silicon germanium/N-type silicon structure, and a PNP transistor having an epitaxial region of a P-type silicon/N-type silicon germanium/P-type silicon structure are formed on a silicon substrate after the formation of an element-isolating oxide film. At this time, the concentration distribution of germanium in the base of each of the NPN transistor and the PNP transistor is adjusted to have a peak in the collector side, and to descend toward the emitter side. Since each epitaxial layer is independently grown, the speed performance of each transistor can be adjusted to the ultimate while maintaining practical withstand voltage.

Abstract: A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-aligned relative to the self-aligned dielectric sidewall spacer providing a predetermined base-to-emitter spacing thereby. The emitter may be an n-type, InP material; the base can be a p-type InGaAs material, possibly carbon-doped. The fabrication method includes forming a emitter electrode on an emitter layer; using the emitter contact as a mask, anisotropically etching the emitter exposing the base layer; forming a self-aligned dielectric sidewall spacer upon the emitter and base; self-alignedly depositing a self-aligned base electrode; using the self-aligned base electrode as a mask, anisotropically etching the base layer to expose the subcollector; and depositing a collector electrode on the subcollector layer.

Abstract: A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.