Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter having a top surface, where the emitter is situated on the top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N+ region, instead of the electron barrier layer, is utilized to increase the gain of the bipolar transistor.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract: The semiconductor device comprises a first semiconductor layer 14 formed on a semiconductor substrate 10; an outgoing base electrode 26 formed on the first semiconductor layer 14; a base layer 32 formed on the first semiconductor layer, connected to the outgoing base electrode at a side surface of the outgoing base electrode, and formed of silicon germanium containing carbon; and a second semiconductor layer 36 formed on the base layer. The base layer 32 of silicon germanium contains carbon, which prevents the action of interstitial silicon atoms, which are very influential to diffusion of boron. As a result, when the emitter layer 36, etc. are subjected to heat processing at, e.g., about 950° C., the diffusion of boron out of the base layer 32 can be prevented.

Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.

Abstract: A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower portion. The base includes an intrinsic base (14) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.

Abstract: A bipolar junction transistor includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a semiconductor layer formed on a sidewall and a bottom of the opening and on a portion of the dielectric layer outside the opening, a spacer formed on the semiconductor layer to define a self-aligned emitter region in the opening, an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the semiconductor layer, and a salicide layer formed on the emitter conductivity layer and on the portion of the semiconductor layer extending outside the opening.

Abstract: As the top electrode material of a thin-film electron emitter, a material having a bandgap wider than that of Si and electrical conductivity is used. In particular, a conductive oxide such as an SnO2 or ITO film and a wide-bandgap semiconductor such as GaN or SiC are employed. The electron energy loss in a top electrode through which hot electrons pass can be reduced so as to enhance the electron emission efficiency. A high emission current can be obtained in the case of the same diode current as a prior art. In addition, in the case of the same emission current density as a prior art, a small driving current is enough. A bus line and driving circuits can be simplified.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.

Abstract: A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and different collector widths. The buried layer of the second component has a larger layer thickness than that of the first component; exactly one epitaxial layer is provided. The different collector widths produced as a result thereof are influenced by the outdiffusion of the dopant of the buried layers by other substances.

Abstract: A SiGe HBT BiCMOS on a SOI substrate includes a self-aligned base/emitter junction to optimize the speed of the HBT device. The disclosed SiGe BiCMOS/SOI device has a higher performance than a SiGe BiCMOS device on a bulk substrate. The disclosed device and method of fabricating the same also retains the high performance of a SiGe HBT and the low power, high-speed properties of a SOI CMOS. In addition, the disclosed method of fabricating a self-aligned base/emitter junction provides a HBT transistor having an improved frequency response.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.

Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer, an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 &mgr;m deep and 5 to 6 &mgr;wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.

Abstract: The invention relates to a trench bipolar transistor structure, having a base 7, emitter 9 and collector 4, the latter being divided into a higher doped region 3 and a lower doped drift region 5. An insulated gate 11 is provided to deplete the drift region 5 when the transistor is switched off. The gate 11 and/or doping levels in the drift region 5 are arranged to provide a substantially uniform electric field in the drift region in this state, to minimise breakdown. In particular, the gate 11 may be seminsulating and a voltage applied along the gate between connections 21,23.

Abstract: An HBT having an InP collector, a GaAsSb base and an InP emitter in which the base is constructed using a thin layer of GaAsSb. The thin base layer can be constructed of a GaAsSb material with a composition having a bulk lattice constant that matches the bulk lattice constant of the material of the collector. The thickness of the GaAsSb base layer is less than 49 nm, and preferably less that about 20 nm. Alternatively, the thin base layer is of a GaAsSb composition that includes a higher As content, resulting in a low conduction band energy discontinuity at the emitter-base junction. Such a GaAsSb base layer has a lattice constant that conforms to the lattice constant of the collector because it is thinly grown so as to be pseudomorphically “strained” over the collector. A high base doping level is used to reduce the sheet resistivity and lower the base series resistance that results from the thinly grown base layer.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract: A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

Abstract: A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity type, which has a buried layer 360 of the opposite conductivity type with sharp junctions, suitable as collector. This layer extends laterally to deep wells 371 of the opposite conductivity type, thus isolating the subsurface band 301a of the semiconductor of the first conductivity type. This band is suitable as the base and has a width 301c controlled by the proximity of the buried layer junction 360a. The emitter 310 is supplied by a surface region of the opposite conductivity type. The photomask, which is needed for implanting the low energy ions to create the extended emitter, is also used for the process step of implanting, at high energy and high dose, the ions needed (opposite conductivity type) to create the buried layer.

Abstract: A SiGe-HBT is provided with a SiGe film and a Si film grown in succession by epitaxial growth. The SiGe film is made up of a SiGe buffer layer, a SiGe graded composition layer, and a SiGe upper layer, in which the Ge content is substantially constant or changes not more than that of the SiGe graded composition layer. Even if there are fluctuations in the position of the EB junction, the EB junction is positioned in a portion of the SiGe upper layer, so fluctuations in the Ge content in the EB junction can be inhibited, and a stable high current amplification factor can be obtained. It is also possible to provide a SiGeC film instead of the SiGe film.

Abstract: A first dopant impurity producing a conductivity type for formation of an intrinsic base diffusion layer and a dopant impurity producing the opposite conductivity type are implanted into a semiconductor substrate. An exposed surface of the semiconductor substrate is irradiated with a plasma, so that many crystalline defects are produced. Next, a polysilicon film is formed under conditions that cause the grain size to increase. In a portion of the polysilicon film located near the exposed surface of the semiconductor substrate, the grain size becomes relatively small, influenced by the crystalline defects in the substrate surface. In a portion of the polysilicon film located on the silicon oxide film, the grain size becomes relatively large, uninfluenced by the crystalline defects. Thus, degradation of electrical characteristics is suppressed, and variation in resistance of the resistance element is alleviated.

Abstract: A bipolar transistor and a method for manufacturing the bipolar transistor are provided.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A bipolar transistor having base and collector regions of narrow bandgap semiconductor material and a minority-carrier excluding base contact has a base doping level greater than 1017 cm−3. The transistor has a greater dynamic range, greater AC voltage and power gain-bandwidth products and a lower base access resistance than prior art narrow band-gap bipolar transistors.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The electronic devices can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The construction of molecular electronic devices is achieved on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The molecular switchable devices in the cross-bar geometry are configurable while the conformational change is controlled by intramolecular forces that are stronger than hydrogen bonding.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.

Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills th

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112′, 212′, 312′, 412′, 512′), resulting in improved gain for the vertical bipolar device.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between a first depth and a second depth in the base. According to this exemplary embodiment, the base of the heterojunction bipolar transistor further comprises a concentration of a diffusion suppressant of a base dopant, where the concentration of the diffusion suppressant decreases between a third depth and a fourth depth so as to counteract a change in band gap in the base between the first depth and the second depth. For example, the diffusion suppressant can be carbon and the base dopant can be boron. For example, the concentration of diffusion suppressant may decrease between the third depth and fourth depth so as to counteract the change in band gap at approximately the second depth.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: The invention relates to a vertical bipolar transistor and a method for the production thereof. The aim of the invention is to produce a vertical bipolar transistor and to disclose a method for the production thereof, whereby excellent high frequency properties can be obtained for said transistor using the simplest possible production technology involving an implanted epitaxy-free collector and only one polysilicon layer spread over a large surface and which can be easily integrated into a conventional mainstream CMOS process without epitaxially produced trough areas.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector contact for coupling to the collector terminal is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.

Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.

Abstract: A structure includes an etch stop layer and a cap layer. The etch stop layer is situated over a first oxide isolation region and a second oxide isolation region in a wafer. A window is situated in the cap layer and the etch stop layer. The window exposes a surface of the wafer situated between the first oxide isolation region and the second oxide isolation region. The surface is cleaned for epitaxially growing a semiconductor. The etch stop layer can comprise, for example, silicon. The cap layer can comprise, for example, silicon nitride, amorphous silicon or polycrystalline silicon. According to one embodiment, the structure can further comprise an epitaxially grown silicon-germanium structure on the surface. According to one embodiment, the surface includes a single crystal silicon collector and a base grown on the single crystal silicon collector, where the base is an epitaxially grown silicon-germanium structure.

Abstract: A bipolar transistor comprises a base region and an an extrinsic base region being located generally adjacent to the base region. The extrinsic base region has implanted therein a dopant and a dopant diffusion-retarding substance. The dopant diffusion-retarding substance serves to reduce the diffusion of the dopant into the base region. Preferably, the dopant and diffusion-retarding substances are implanted such that there is a buffer zone in the extrinsic base region immediately adjacent to the base region into which the dopant may diffuse after implantation. The dopant may for example be boron, and the dopant diffusion-retarding substance may for example be a group IV element such as carbon or germanium.

Abstract: Various embodiments of a novel transistor layout having improved electrical and heat dissipation characteristics are disclosed. Several embodiments include various intrinsic components contoured to the shape of the emitter. The various intrinsic components may include a collector layer center portion, a collector contact, a base pedestal, and/or a base contact. Additional embodiments include improved heat dissipation within single transistors. Still further embodiments include improved heat dissipation across a plurality of transistors.

Abstract: A bipolar transistor is provided.

Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The method includes providing a semiconductor substrate (1) with an n-doped collector layer (5) surrounded by isolation areas (4), implanting antimony ions into the collector layer such that a thin highly n-doped layer (18) is formed in the uppermost portion of the collector layer, and forming a base on top of said thin highly n-doped layer (18).

Abstract: A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method includes producing an opening in a dielectric layer located over a substrate and forming a collector in the substrate by implanting a first dopant through the opening. The method further includes creating an intrinsic base region contacting the collector and constructing an emitter contacting the intrinsic base region, both of which are through the opening.