Abstract: According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.

Abstract: The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.

Abstract: Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit.

Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.

Abstract: Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.

Abstract: A resistive memory device includes a first electrode layer, a second electrode layer, and a first variable resistive layer and a second variable resistive layer stacked at least once between the first electrode layer and the second electrode layer. The first variable resistive material layer may include a metal nitride layer having a resistivity higher than that of the first electrode layer or the second electrode layer and less than or equal to that of an insulating material.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.

Abstract: A resistive memory device capable of suppressing disturbance between cells and a fabrication method thereof are provided. The resistive memory device includes a word line formed, in a first direction, on a semiconductor substrate, lower access structures, each having a pillar shape, formed on the word line, a first insulating layer formed around an outer circumference of each of the lower access structures, a heat-absorption layer formed on a surface of each of the to heat-absorption layers, a variable resistive material formed on the lower access structures, and an upper electrode formed on each variable resistive material.

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.

Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.

Abstract: The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.

Abstract: An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed.

Abstract: The PCRAM device includes a semiconductor substrate including a switching device; an interlayer insulating layer having a heating electrode contact hole exposing the switching device, a heating electrode formed to be extended along a side of the interlayer insulating layer in the heating electrode contact hole, wherein the heating electrode has a width gradually increased toward a bottom of the heating electrode and is in contact with the switching device, first and second phase-change layers formed within the heating electrode contact hole that includes the heating electrode, and a phase-change separation layer formed in the heating electrode contact hole between the first and second phase-change layers.

Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) thrilled over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.

Abstract: Some embodiments include memory cells which contain chalcogenide material having germanium in combination with one or both of antimony and tellurium. An atomic percentage of the germanium within the chalcogenide material is greater than 50%; and may be, for example, within a range of from greater than or equal to about 52% to less than or equal to about 78%. In some embodiments, the memory cell has a top electrode over the chalcogenide material, a heater element under and directly against the chalcogenide material, and a bottom electrode beneath the heater element. The heater element may be L-shaped, with the L-shape having a vertical pillar region joining with a horizontal leg region. A bottom surface of the horizontal leg region may be directly against the bottom electrode, and a top surface of the vertical pillar region may be directly against the chalcogenide material.

Abstract: A semiconductor memory device, including: plural parallel first lines; plural second lines disposed to intersect the first lines; and a memory cell array including memory cells, disposed at intersections of the first lines and the second lines, each of the memory cells configured by a rectifier element and a variable resistor connected in series. The rectifier element includes: a first semiconductor region including an impurity of a first conductivity type at a first impurity concentration; and a second semiconductor region including an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration and including an impurity of the first conductivity type at a third impurity concentration lower than the second impurity concentration, the first and second semiconductor regions being formed by silicon.

Abstract: A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.

Abstract: A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.

Abstract: Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed herein includes a first word line structure formed above a substrate, wherein the first word line structure includes a gate electrode and a nano-crystal containing layer of insulating material, a second word line structure formed above the substrate, wherein the second word line structure comprises a gate electrode and a nano-crystal containing layer of insulating material, a first implant region formed in the substrate proximate the first word line structure, wherein the first implant region defines a first bit line, and a second implant region formed in the substrate proximate the second word line structure, wherein the second implant region defines a second bit line.

Abstract: The present invention provides a castle-like shaped protect or a periphery protect or a DC chop mask for forming staggered data line patterns in semiconductor devices so as to shift the adjacent data lines from one another so as to print contacts with larger areas at one end of each data line.

Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract: A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract: Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

Abstract: First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.

Abstract: A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers.

Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

Abstract: A nonvolatile semiconductor memory device below comprises: a memory cell array configured having memory cells arranged therein disposed at intersections of a plurality of first lines and a plurality of second lines formed so as to intersect each other, and the memory cells each comprising a variable resistance element; and a control circuit configured to select and drive the first lines and the second lines. The variable resistance element is configured by a transition metal oxide film. The variable resistance element is electrically connected to a first electrode configured from a metal at a first surface and is electrically connected to a second electrode at a second surface which is on an opposite side to the first surface. A first insulating film is formed between the first electrode and the variable resistance element. The first insulating film is formed by a first material that is formed by covalent binding.

Abstract: A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.

Abstract: A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Abstract: A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.

Abstract: The present invention relates to integrating a resistive o y device on top of an IC substrate monolithically using IC-foundry compatible processes.

Abstract: According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.

Abstract: A phase change material may be processed to reduce its microcrystalline grain size and may also be processed to increase the crystallization or set programming speed of the material. For example, material doped with nitrogen to reduce grain size may be doped with titanium to reduce crystallization time.

Abstract: A spatial light modulator includes an array of pixels, with each of the pixels having a dimension smaller than a wavelength of light to be modulated. Each of the pixels further has a permittivity that can be controlled using an electronic signal applied to the pixel.

Abstract: A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction.

Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.

Abstract: A memory device includes an upper conductive layer, a lower conductive layer, and a resistive, optical or magnetic matrix positioned between the upper and lower conductive layers.

Abstract: Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials.