Abstract: A flexible substrate includes: a flexible base substrate; a plurality of display structures on a first surface of the flexible base substrate; and a barrier coating on a second surface of the flexible base substrate to prevent contaminants from penetrating into the display structures.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract: Providing for two-terminal memory cell structures and fabrication that can be achieved with a relatively low temperature process(es) is described herein. By way of example, disclosed two-terminal memory cells can be formed at least in part as a continuous deposition, potentially yielding improved efficiency in manufacturing. Furthermore, various embodiments can be compatible with some existing complementary metal oxide semiconductor fabrication processes, reducing or avoiding retooling overhead that might be associated with modifying existing fabrication processes in favor of other two-terminal memory cell fabrication techniques.

Abstract: A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: The present invention discloses a resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract: A resistive-change memory element-containing memory device including: a first memory element that includes a first resistive-change layer and a first electrode connected to the first resistive-change layer; and a second memory element that includes a second resistive-change layer and a second electrode connected to the second resistive-change layer, wherein at least one of the thickness and the material of the second resistive-change layer and the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of the thickness and the material of the first resistive-change layer and the area of the first electrode in contact with the first resistive-change layer.

Abstract: A nonvolatile memory device according to an embodiment of the present invention includes: a first wire embedded in a first wiring groove extending in an X direction formed in a first interlayer insulating film; a second interlayer insulating film formed above the first interlayer insulating film; a second wire embedded in a second wiring groove extending in a Y direction formed in the second interlayer insulating film; and a variable resistance memory cell including a variable resistive layer and a rectifying layer arranged to be held between the first wire and the second wire in a position where the first wire and the second wire intersect. A dimension in a plane perpendicular to a thickness direction of the variable resistance memory cell is specified by widths of the first and second wires.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.

Abstract: A phase-change memory and a semiconductor recording/reproducing device capable of reducing consumed power are provided. A SnxTe100-x/Sb2Te3 SL film obtained by depositing a SnxTe100-x film and a Sb2Te3 film layer by layer contains a SnTe/Sb2Te3 superlattice phase formed of SnTe and Sb2Te3, a SnSbTe alloy phase, and a Te phase. The SnTe/Sb2Te3 superlattice phase is diluted by the SnSbTe alloy phase and the Te phase. Here, X of the SnxTe100-x film is represented by 4 at. %?X?55 at. %.

Abstract: A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.

Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.

Abstract: A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.

Abstract: A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (88p and 89p) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer (9) interposed, and a resistance-change material layer (7) is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract: A nonvolatile memory device has a memory cell including a resistance change layer, a first electrode, and a second electrode. The resistance change layer switches between high and low resistance states due to the transfer of metal ions from the first electrode in response to voltages applied between the electrodes. The first electrode is formed on a first side of the resistance change layer, and provides metal ions. The second electrode is formed on a second side of the resistance change layer. A memory cell region is formed between the first electrode and the second electrode with the resistance change layer. The memory device also includes a high permittivity layer with a higher dielectric constant than the resistance change layer.

Abstract: Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

Abstract: Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a variable resistive pattern, a lower electrode structure, a heating electrode. The heating electrode includes first, second and plate portions. The first portion is extended in a first direction. The second portion is upwardly protruded from a central region of a top surface of the first portion and is in contact with the variable resistive pattern. The plate portion is extended from a lower end of the first portion in a second direction perpendicular to the first direction. The plate portion is in contact with the lower electrode structure.

Abstract: A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.

Abstract: A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided.

Abstract: Provided are a memory element and a memory device. A memory layer is provided with an ion source layer. The ion source layer includes Zr (zirconium), Cu (copper), and Al (aluminum) as a metal element together with an ion conductive material such as S (sulfur), Se (selenium), and Te (tellurium) (chalcogen element). The amount of Al in the ion source layer is 30 to 50 atomic percent. The amount of Zr is preferably 7.5 to 25 atomic percent, and more preferably, the composition ratio of Zr to the chalcogen element in total included in the ion source layer (=Zr (atomic percent)/chalcogen element in total (atomic percent)) falls within a range from 0.2 to 0.74.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract: A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element.

Abstract: A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.

Abstract: A memory element and a memory device having the stable switching characteristics with the characteristics of data retention remaining favorable are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes an ion source layer provided on the second electrode side, a resistance change layer provided between the ion source layer and the first electrode, and a barrier layer provided between the resistance change layer and the first electrode, and having conductivity higher than that of the resistance change layer.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.

Abstract: According to one embodiment, a resistance change memory includes resistance change elements arrayed with a first space in a first direction and with a second space wider than the first space in a second direction orthogonal to the first direction, second conductive layers disposed on sidewalls of the resistance change elements, each of the second conductive layers having a width greater than or equal to a half of the first space in the first direction and having a width less than a half of the second space in the second direction, the second conductive layers functioning as a first bit line extending in the first direction, a second insulating layer disposed on a sidewall of the first bit line, and not filling the second space, and a third conductive layer functioning as a second bit line extending in the first direction by filling the second space.

Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.

Abstract: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.

Abstract: A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8.

Abstract: A monolithic three-dimensional memory array is provided that includes a first memory level and a second memory level disposed above or below the first memory level. The first memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped p type region. The second memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped n type region. Numerous other aspects are also provided.

Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

Abstract: A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12).

Abstract: A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.

Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

Abstract: A semiconductor device includes a transistor including a plurality of transistor cells in a semiconductor body, each transistor cell including a control terminal and first and second load terminals. The semiconductor device further includes a first electrical connection electrically connecting the first load terminals. The semiconductor device further includes a second electrical connection electrically connecting the second load terminals. The transistor further includes a phase change material exhibiting a solid-solid phase change at a phase transition temperature Tc between 150° C. and 400° C.

Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.

Abstract: A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.

Abstract: According to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect.

Abstract: A memory cell array and a resistive variable memory device including the memory cell array are provided. The memory cell array includes a memory group. The memory cell array includes a pair of word lines, an inter-pattern insulating layer interposed between the pair of word lines, and a plurality of active pillars, each having one side contacted with the inter-pattern insulating layer and other sides surrounded by the word line.

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

Abstract: The method includes: forming a lower electrode layer above a substrate; forming a variable resistance layer on the lower electrode layer; forming an upper electrode layer on the variable resistance layer; forming a hard mask layer on the upper electrode layer; forming a photoresist mask on the hard mask layer; forming a hard mask by performing etching on the hard mask layer using the photoresist mask; and forming a nonvolatile memory element by performing etching on the upper electrode layer, the variable resistance layer, and the lower electrode layer, using the hard mask. In the forming of a photoresist mask, the photoresist mask is formed to have corner portions which recede toward the center portion in planar view.

Abstract: A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode.

Abstract: According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.

Abstract: A non-volatile memory element includes: a memory layer disposed between a first electrode and a second electrode; and a buffer layer disposed between the memory layer and the first electrode. The memory layer includes a first material layer and a second material layer. The first material layer and the second material layer are configured to exchange ionic species to change a resistance state of the memory layer.

Abstract: A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.